drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device, u16 caps);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  89                         if ((rdev->family == CHIP_R420) ||
  90                             (rdev->family == CHIP_R423) ||
  91                             (rdev->family == CHIP_RV410)) {
  92                                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  93                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  94                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  95                                         gpio->ucClkMaskShift = 0x19;
  96                                         gpio->ucDataMaskShift = 0x18;
  97                                 }
  98                         }
  99
 100                         /* some evergreen boards have bad data for this entry */
 101                         if (ASIC_IS_DCE4(rdev)) {
 102                                 if ((i == 7) &&
 103                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
 104                                     (gpio->sucI2cId.ucAccess == 0)) {
 105                                         gpio->sucI2cId.ucAccess = 0x97;
 106                                         gpio->ucDataMaskShift = 8;
 107                                         gpio->ucDataEnShift = 8;
 108                                         gpio->ucDataY_Shift = 8;
 109                                         gpio->ucDataA_Shift = 8;
 110                                 }
 111                         }
 112
 113                         /* some DCE3 boards have bad data for this entry */
 114                         if (ASIC_IS_DCE3(rdev)) {
 115                                 if ((i == 4) &&
 116                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
 117                                     (gpio->sucI2cId.ucAccess == 0x94))
 118                                         gpio->sucI2cId.ucAccess = 0x14;
 119                         }
 120
 121                         if (gpio->sucI2cId.ucAccess == id) {
 122                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 123                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 124                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 125                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 126                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 127                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 128                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 129                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 130                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 131                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 132                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 133                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 134                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 135                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 136                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 137                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 138
 139                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 140                                         i2c.hw_capable = true;
 141                                 else
 142                                         i2c.hw_capable = false;
 143
 144                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 145                                         i2c.mm_i2c = true;
 146                                 else
 147                                         i2c.mm_i2c = false;
 148
 149                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 150
 151                                 if (i2c.mask_clk_reg)
 152                                         i2c.valid = true;
 153                                 break;
 154                         }
 155                 }
 156         }
 157
 158         return i2c;
 159 }
 160
 161 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 162 {
 163         struct atom_context *ctx = rdev->mode_info.atom_context;
 164         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 165         struct radeon_i2c_bus_rec i2c;
 166         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 167         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 168         uint16_t data_offset, size;
 169         int i, num_indices;
 170         char stmp[32];
 171
 172         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 173
 174         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 175                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 176
 177                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 178                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 179
 180                 for (i = 0; i < num_indices; i++) {
 181                         gpio = &i2c_info->asGPIO_Info[i];
 182                         i2c.valid = false;
 183
 184                         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
 185                         if ((rdev->family == CHIP_R420) ||
 186                             (rdev->family == CHIP_R423) ||
 187                             (rdev->family == CHIP_RV410)) {
 188                                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
 189                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
 190                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
 191                                         gpio->ucClkMaskShift = 0x19;
 192                                         gpio->ucDataMaskShift = 0x18;
 193                                 }
 194                         }
 195
 196                         /* some evergreen boards have bad data for this entry */
 197                         if (ASIC_IS_DCE4(rdev)) {
 198                                 if ((i == 7) &&
 199                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
 200                                     (gpio->sucI2cId.ucAccess == 0)) {
 201                                         gpio->sucI2cId.ucAccess = 0x97;
 202                                         gpio->ucDataMaskShift = 8;
 203                                         gpio->ucDataEnShift = 8;
 204                                         gpio->ucDataY_Shift = 8;
 205                                         gpio->ucDataA_Shift = 8;
 206                                 }
 207                         }
 208
 209                         /* some DCE3 boards have bad data for this entry */
 210                         if (ASIC_IS_DCE3(rdev)) {
 211                                 if ((i == 4) &&
 212                                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
 213                                     (gpio->sucI2cId.ucAccess == 0x94))
 214                                         gpio->sucI2cId.ucAccess = 0x14;
 215                         }
 216
 217                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 218                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 219                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 220                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 221                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 222                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 223                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 224                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 225                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 226                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 227                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 228                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 229                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 230                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 231                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 232                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 233
 234                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 235                                 i2c.hw_capable = true;
 236                         else
 237                                 i2c.hw_capable = false;
 238
 239                         if (gpio->sucI2cId.ucAccess == 0xa0)
 240                                 i2c.mm_i2c = true;
 241                         else
 242                                 i2c.mm_i2c = false;
 243
 244                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 245
 246                         if (i2c.mask_clk_reg) {
 247                                 i2c.valid = true;
 248                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 249                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 250                         }
 251                 }
 252         }
 253 }
 254
 255 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 256                                                         u8 id)
 257 {
 258         struct atom_context *ctx = rdev->mode_info.atom_context;
 259         struct radeon_gpio_rec gpio;
 260         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 261         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 262         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 263         u16 data_offset, size;
 264         int i, num_indices;
 265
 266         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 267         gpio.valid = false;
 268
 269         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 270                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 271
 272                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 273                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 274
 275                 for (i = 0; i < num_indices; i++) {
 276                         pin = &gpio_info->asGPIO_Pin[i];
 277                         if (id == pin->ucGPIO_ID) {
 278                                 gpio.id = pin->ucGPIO_ID;
 279                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 280                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 281                                 gpio.valid = true;
 282                                 break;
 283                         }
 284                 }
 285         }
 286
 287         return gpio;
 288 }
 289
 290 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 291                                                             struct radeon_gpio_rec *gpio)
 292 {
 293         struct radeon_hpd hpd;
 294         u32 reg;
 295
 296         memset(&hpd, 0, sizeof(struct radeon_hpd));
 297
 298         if (ASIC_IS_DCE4(rdev))
 299                 reg = EVERGREEN_DC_GPIO_HPD_A;
 300         else
 301                 reg = AVIVO_DC_GPIO_HPD_A;
 302
 303         hpd.gpio = *gpio;
 304         if (gpio->reg == reg) {
 305                 switch(gpio->mask) {
 306                 case (1 << 0):
 307                         hpd.hpd = RADEON_HPD_1;
 308                         break;
 309                 case (1 << 8):
 310                         hpd.hpd = RADEON_HPD_2;
 311                         break;
 312                 case (1 << 16):
 313                         hpd.hpd = RADEON_HPD_3;
 314                         break;
 315                 case (1 << 24):
 316                         hpd.hpd = RADEON_HPD_4;
 317                         break;
 318                 case (1 << 26):
 319                         hpd.hpd = RADEON_HPD_5;
 320                         break;
 321                 case (1 << 28):
 322                         hpd.hpd = RADEON_HPD_6;
 323                         break;
 324                 default:
 325                         hpd.hpd = RADEON_HPD_NONE;
 326                         break;
 327                 }
 328         } else
 329                 hpd.hpd = RADEON_HPD_NONE;
 330         return hpd;
 331 }
 332
 333 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 334                                      uint32_t supported_device,
 335                                      int *connector_type,
 336                                      struct radeon_i2c_bus_rec *i2c_bus,
 337                                      uint16_t *line_mux,
 338                                      struct radeon_hpd *hpd)
 339 {
 340
 341         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 342         if ((dev->pdev->device == 0x791e) &&
 343             (dev->pdev->subsystem_vendor == 0x1043) &&
 344             (dev->pdev->subsystem_device == 0x826d)) {
 345                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 346                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 347                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 348         }
 349
 350         /* Asrock RS600 board lists the DVI port as HDMI */
 351         if ((dev->pdev->device == 0x7941) &&
 352             (dev->pdev->subsystem_vendor == 0x1849) &&
 353             (dev->pdev->subsystem_device == 0x7941)) {
 354                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 355                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 356                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 357         }
 358
 359         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 360         if ((dev->pdev->device == 0x796e) &&
 361             (dev->pdev->subsystem_vendor == 0x1462) &&
 362             (dev->pdev->subsystem_device == 0x7302)) {
 363                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 364                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 365                         return false;
 366         }
 367
 368         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 369         if ((dev->pdev->device == 0x7941) &&
 370             (dev->pdev->subsystem_vendor == 0x147b) &&
 371             (dev->pdev->subsystem_device == 0x2412)) {
 372                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 373                         return false;
 374         }
 375
 376         /* Falcon NW laptop lists vga ddc line for LVDS */
 377         if ((dev->pdev->device == 0x5653) &&
 378             (dev->pdev->subsystem_vendor == 0x1462) &&
 379             (dev->pdev->subsystem_device == 0x0291)) {
 380                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 381                         i2c_bus->valid = false;
 382                         *line_mux = 53;
 383                 }
 384         }
 385
 386         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 387         if ((dev->pdev->device == 0x7146) &&
 388             (dev->pdev->subsystem_vendor == 0x17af) &&
 389             (dev->pdev->subsystem_device == 0x2058)) {
 390                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 391                         return false;
 392         }
 393
 394         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 395         if ((dev->pdev->device == 0x7142) &&
 396             (dev->pdev->subsystem_vendor == 0x1458) &&
 397             (dev->pdev->subsystem_device == 0x2134)) {
 398                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 399                         return false;
 400         }
 401
 402
 403         /* Funky macbooks */
 404         if ((dev->pdev->device == 0x71C5) &&
 405             (dev->pdev->subsystem_vendor == 0x106b) &&
 406             (dev->pdev->subsystem_device == 0x0080)) {
 407                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 408                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 409                         return false;
 410                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 411                         *line_mux = 0x90;
 412         }
 413
 414         /* mac rv630, rv730, others */
 415         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 416             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 417                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 418                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 419         }
 420
 421         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 422         if ((dev->pdev->device == 0x9598) &&
 423             (dev->pdev->subsystem_vendor == 0x1043) &&
 424             (dev->pdev->subsystem_device == 0x01da)) {
 425                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 426                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 427                 }
 428         }
 429
 430         /* ASUS HD 3600 board lists the DVI port as HDMI */
 431         if ((dev->pdev->device == 0x9598) &&
 432             (dev->pdev->subsystem_vendor == 0x1043) &&
 433             (dev->pdev->subsystem_device == 0x01e4)) {
 434                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 435                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 436                 }
 437         }
 438
 439         /* ASUS HD 3450 board lists the DVI port as HDMI */
 440         if ((dev->pdev->device == 0x95C5) &&
 441             (dev->pdev->subsystem_vendor == 0x1043) &&
 442             (dev->pdev->subsystem_device == 0x01e2)) {
 443                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 444                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 445                 }
 446         }
 447
 448         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 449          * HDMI + VGA reporting as HDMI
 450          */
 451         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 452                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 453                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 454                         *line_mux = 0;
 455                 }
 456         }
 457
 458         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 459          * on the laptop and a DVI port on the docking station and
 460          * both share the same encoder, hpd pin, and ddc line.
 461          * So while the bios table is technically correct,
 462          * we drop the DVI port here since xrandr has no concept of
 463          * encoders and will try and drive both connectors
 464          * with different crtcs which isn't possible on the hardware
 465          * side and leaves no crtcs for LVDS or VGA.
 466          */
 467         if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
 468             (dev->pdev->subsystem_vendor == 0x1025) &&
 469             (dev->pdev->subsystem_device == 0x013c)) {
 470                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 471                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 472                         /* actually it's a DVI-D port not DVI-I */
 473                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 474                         return false;
 475                 }
 476         }
 477
 478         /* XFX Pine Group device rv730 reports no VGA DDC lines
 479          * even though they are wired up to record 0x93
 480          */
 481         if ((dev->pdev->device == 0x9498) &&
 482             (dev->pdev->subsystem_vendor == 0x1682) &&
 483             (dev->pdev->subsystem_device == 0x2452)) {
 484                 struct radeon_device *rdev = dev->dev_private;
 485                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 486         }
 487         return true;
 488 }
 489
 490 const int supported_devices_connector_convert[] = {
 491         DRM_MODE_CONNECTOR_Unknown,
 492         DRM_MODE_CONNECTOR_VGA,
 493         DRM_MODE_CONNECTOR_DVII,
 494         DRM_MODE_CONNECTOR_DVID,
 495         DRM_MODE_CONNECTOR_DVIA,
 496         DRM_MODE_CONNECTOR_SVIDEO,
 497         DRM_MODE_CONNECTOR_Composite,
 498         DRM_MODE_CONNECTOR_LVDS,
 499         DRM_MODE_CONNECTOR_Unknown,
 500         DRM_MODE_CONNECTOR_Unknown,
 501         DRM_MODE_CONNECTOR_HDMIA,
 502         DRM_MODE_CONNECTOR_HDMIB,
 503         DRM_MODE_CONNECTOR_Unknown,
 504         DRM_MODE_CONNECTOR_Unknown,
 505         DRM_MODE_CONNECTOR_9PinDIN,
 506         DRM_MODE_CONNECTOR_DisplayPort
 507 };
 508
 509 const uint16_t supported_devices_connector_object_id_convert[] = {
 510         CONNECTOR_OBJECT_ID_NONE,
 511         CONNECTOR_OBJECT_ID_VGA,
 512         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 513         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 514         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 515         CONNECTOR_OBJECT_ID_COMPOSITE,
 516         CONNECTOR_OBJECT_ID_SVIDEO,
 517         CONNECTOR_OBJECT_ID_LVDS,
 518         CONNECTOR_OBJECT_ID_9PIN_DIN,
 519         CONNECTOR_OBJECT_ID_9PIN_DIN,
 520         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 521         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 522         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 523         CONNECTOR_OBJECT_ID_SVIDEO
 524 };
 525
 526 const int object_connector_convert[] = {
 527         DRM_MODE_CONNECTOR_Unknown,
 528         DRM_MODE_CONNECTOR_DVII,
 529         DRM_MODE_CONNECTOR_DVII,
 530         DRM_MODE_CONNECTOR_DVID,
 531         DRM_MODE_CONNECTOR_DVID,
 532         DRM_MODE_CONNECTOR_VGA,
 533         DRM_MODE_CONNECTOR_Composite,
 534         DRM_MODE_CONNECTOR_SVIDEO,
 535         DRM_MODE_CONNECTOR_Unknown,
 536         DRM_MODE_CONNECTOR_Unknown,
 537         DRM_MODE_CONNECTOR_9PinDIN,
 538         DRM_MODE_CONNECTOR_Unknown,
 539         DRM_MODE_CONNECTOR_HDMIA,
 540         DRM_MODE_CONNECTOR_HDMIB,
 541         DRM_MODE_CONNECTOR_LVDS,
 542         DRM_MODE_CONNECTOR_9PinDIN,
 543         DRM_MODE_CONNECTOR_Unknown,
 544         DRM_MODE_CONNECTOR_Unknown,
 545         DRM_MODE_CONNECTOR_Unknown,
 546         DRM_MODE_CONNECTOR_DisplayPort,
 547         DRM_MODE_CONNECTOR_eDP,
 548         DRM_MODE_CONNECTOR_Unknown
 549 };
 550
 551 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 552 {
 553         struct radeon_device *rdev = dev->dev_private;
 554         struct radeon_mode_info *mode_info = &rdev->mode_info;
 555         struct atom_context *ctx = mode_info->atom_context;
 556         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 557         u16 size, data_offset;
 558         u8 frev, crev;
 559         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 560         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 561         ATOM_OBJECT_TABLE *router_obj;
 562         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 563         ATOM_OBJECT_HEADER *obj_header;
 564         int i, j, k, path_size, device_support;
 565         int connector_type;
 566         u16 igp_lane_info, conn_id, connector_object_id;
 567         struct radeon_i2c_bus_rec ddc_bus;
 568         struct radeon_router router;
 569         struct radeon_gpio_rec gpio;
 570         struct radeon_hpd hpd;
 571
 572         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 573                 return false;
 574
 575         if (crev < 2)
 576                 return false;
 577
 578         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 579         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 580             (ctx->bios + data_offset +
 581              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 582         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 583             (ctx->bios + data_offset +
 584              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 585         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 586             (ctx->bios + data_offset +
 587              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 588         router_obj = (ATOM_OBJECT_TABLE *)
 589                 (ctx->bios + data_offset +
 590                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 591         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 592
 593         path_size = 0;
 594         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 595                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 596                 ATOM_DISPLAY_OBJECT_PATH *path;
 597                 addr += path_size;
 598                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 599                 path_size += le16_to_cpu(path->usSize);
 600
 601                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 602                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 603
 604                         con_obj_id =
 605                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 606                             >> OBJECT_ID_SHIFT;
 607                         con_obj_num =
 608                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 609                             >> ENUM_ID_SHIFT;
 610                         con_obj_type =
 611                             (le16_to_cpu(path->usConnObjectId) &
 612                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 613
 614                         /* TODO CV support */
 615                         if (le16_to_cpu(path->usDeviceTag) ==
 616                                 ATOM_DEVICE_CV_SUPPORT)
 617                                 continue;
 618
 619                         /* IGP chips */
 620                         if ((rdev->flags & RADEON_IS_IGP) &&
 621                             (con_obj_id ==
 622                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 623                                 uint16_t igp_offset = 0;
 624                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 625
 626                                 index =
 627                                     GetIndexIntoMasterTable(DATA,
 628                                                             IntegratedSystemInfo);
 629
 630                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 631                                                            &crev, &igp_offset)) {
 632
 633                                         if (crev >= 2) {
 634                                                 igp_obj =
 635                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 636                                                          *) (ctx->bios + igp_offset);
 637
 638                                                 if (igp_obj) {
 639                                                         uint32_t slot_config, ct;
 640
 641                                                         if (con_obj_num == 1)
 642                                                                 slot_config =
 643                                                                         igp_obj->
 644                                                                         ulDDISlot1Config;
 645                                                         else
 646                                                                 slot_config =
 647                                                                         igp_obj->
 648                                                                         ulDDISlot2Config;
 649
 650                                                         ct = (slot_config >> 16) & 0xff;
 651                                                         connector_type =
 652                                                                 object_connector_convert
 653                                                                 [ct];
 654                                                         connector_object_id = ct;
 655                                                         igp_lane_info =
 656                                                                 slot_config & 0xffff;
 657                                                 } else
 658                                                         continue;
 659                                         } else
 660                                                 continue;
 661                                 } else {
 662                                         igp_lane_info = 0;
 663                                         connector_type =
 664                                                 object_connector_convert[con_obj_id];
 665                                         connector_object_id = con_obj_id;
 666                                 }
 667                         } else {
 668                                 igp_lane_info = 0;
 669                                 connector_type =
 670                                     object_connector_convert[con_obj_id];
 671                                 connector_object_id = con_obj_id;
 672                         }
 673
 674                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 675                                 continue;
 676
 677                         router.ddc_valid = false;
 678                         router.cd_valid = false;
 679                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 680                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 681
 682                                 grph_obj_id =
 683                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 684                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 685                                 grph_obj_num =
 686                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 687                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 688                                 grph_obj_type =
 689                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 690                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 691
 692                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 693                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 694                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 695                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 696                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 697                                                                 (ctx->bios + data_offset +
 698                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 699                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 700                                                         u16 caps = 0;
 701
 702                                                         while (record->ucRecordSize > 0 &&
 703                                                                record->ucRecordType > 0 &&
 704                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 705                                                                 switch (record->ucRecordType) {
 706                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 707                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 708                                                                                 record;
 709                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 710                                                                         break;
 711                                                                 }
 712                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 713                                                                         ((char *)record + record->ucRecordSize);
 714                                                         }
 715                                                         radeon_add_atom_encoder(dev,
 716                                                                                 encoder_obj,
 717                                                                                 le16_to_cpu
 718                                                                                 (path->
 719                                                                                  usDeviceTag),
 720                                                                                 caps);
 721                                                 }
 722                                         }
 723                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 724                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 725                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 726                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 727                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 728                                                                 (ctx->bios + data_offset +
 729                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 730                                                         ATOM_I2C_RECORD *i2c_record;
 731                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 732                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 733                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 734                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 735                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 736                                                                 (ctx->bios + data_offset +
 737                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 738                                                         int enum_id;
 739
 740                                                         router.router_id = router_obj_id;
 741                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 742                                                              enum_id++) {
 743                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 744                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 745                                                                         break;
 746                                                         }
 747
 748                                                         while (record->ucRecordSize > 0 &&
 749                                                                record->ucRecordType > 0 &&
 750                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 751                                                                 switch (record->ucRecordType) {
 752                                                                 case ATOM_I2C_RECORD_TYPE:
 753                                                                         i2c_record =
 754                                                                                 (ATOM_I2C_RECORD *)
 755                                                                                 record;
 756                                                                         i2c_config =
 757                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 758                                                                                 &i2c_record->sucI2cId;
 759                                                                         router.i2c_info =
 760                                                                                 radeon_lookup_i2c_gpio(rdev,
 761                                                                                                        i2c_config->
 762                                                                                                        ucAccess);
 763                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 764                                                                         break;
 765                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 766                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 767                                                                                 record;
 768                                                                         router.ddc_valid = true;
 769                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 770                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 771                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 772                                                                         break;
 773                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 774                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 775                                                                                 record;
 776                                                                         router.cd_valid = true;
 777                                                                         router.cd_mux_type = cd_path->ucMuxType;
 778                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 779                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 780                                                                         break;
 781                                                                 }
 782                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 783                                                                         ((char *)record + record->ucRecordSize);
 784                                                         }
 785                                                 }
 786                                         }
 787                                 }
 788                         }
 789
 790                         /* look up gpio for ddc, hpd */
 791                         ddc_bus.valid = false;
 792                         hpd.hpd = RADEON_HPD_NONE;
 793                         if ((le16_to_cpu(path->usDeviceTag) &
 794                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 795                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 796                                         if (le16_to_cpu(path->usConnObjectId) ==
 797                                             le16_to_cpu(con_obj->asObjects[j].
 798                                                         usObjectID)) {
 799                                                 ATOM_COMMON_RECORD_HEADER
 800                                                     *record =
 801                                                     (ATOM_COMMON_RECORD_HEADER
 802                                                      *)
 803                                                     (ctx->bios + data_offset +
 804                                                      le16_to_cpu(con_obj->
 805                                                                  asObjects[j].
 806                                                                  usRecordOffset));
 807                                                 ATOM_I2C_RECORD *i2c_record;
 808                                                 ATOM_HPD_INT_RECORD *hpd_record;
 809                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 810
 811                                                 while (record->ucRecordSize > 0 &&
 812                                                        record->ucRecordType > 0 &&
 813                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 814                                                         switch (record->ucRecordType) {
 815                                                         case ATOM_I2C_RECORD_TYPE:
 816                                                                 i2c_record =
 817                                                                     (ATOM_I2C_RECORD *)
 818                                                                         record;
 819                                                                 i2c_config =
 820                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 821                                                                         &i2c_record->sucI2cId;
 822                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 823                                                                                                  i2c_config->
 824                                                                                                  ucAccess);
 825                                                                 break;
 826                                                         case ATOM_HPD_INT_RECORD_TYPE:
 827                                                                 hpd_record =
 828                                                                         (ATOM_HPD_INT_RECORD *)
 829                                                                         record;
 830                                                                 gpio = radeon_lookup_gpio(rdev,
 831                                                                                           hpd_record->ucHPDIntGPIOID);
 832                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 833                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 834                                                                 break;
 835                                                         }
 836                                                         record =
 837                                                             (ATOM_COMMON_RECORD_HEADER
 838                                                              *) ((char *)record
 839                                                                  +
 840                                                                  record->
 841                                                                  ucRecordSize);
 842                                                 }
 843                                                 break;
 844                                         }
 845                                 }
 846                         }
 847
 848                         /* needed for aux chan transactions */
 849                         ddc_bus.hpd = hpd.hpd;
 850
 851                         conn_id = le16_to_cpu(path->usConnObjectId);
 852
 853                         if (!radeon_atom_apply_quirks
 854                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 855                              &ddc_bus, &conn_id, &hpd))
 856                                 continue;
 857
 858                         radeon_add_atom_connector(dev,
 859                                                   conn_id,
 860                                                   le16_to_cpu(path->
 861                                                               usDeviceTag),
 862                                                   connector_type, &ddc_bus,
 863                                                   igp_lane_info,
 864                                                   connector_object_id,
 865                                                   &hpd,
 866                                                   &router);
 867
 868                 }
 869         }
 870
 871         radeon_link_encoder_connector(dev);
 872
 873         return true;
 874 }
 875
 876 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 877                                                  int connector_type,
 878                                                  uint16_t devices)
 879 {
 880         struct radeon_device *rdev = dev->dev_private;
 881
 882         if (rdev->flags & RADEON_IS_IGP) {
 883                 return supported_devices_connector_object_id_convert
 884                         [connector_type];
 885         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 886                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 887                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 888                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 889                 struct atom_context *ctx = mode_info->atom_context;
 890                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 891                 uint16_t size, data_offset;
 892                 uint8_t frev, crev;
 893                 ATOM_XTMDS_INFO *xtmds;
 894
 895                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 896                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 897
 898                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 899                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 900                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 901                                 else
 902                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 903                         } else {
 904                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 905                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 906                                 else
 907                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 908                         }
 909                 } else
 910                         return supported_devices_connector_object_id_convert
 911                                 [connector_type];
 912         } else {
 913                 return supported_devices_connector_object_id_convert
 914                         [connector_type];
 915         }
 916 }
 917
 918 struct bios_connector {
 919         bool valid;
 920         uint16_t line_mux;
 921         uint16_t devices;
 922         int connector_type;
 923         struct radeon_i2c_bus_rec ddc_bus;
 924         struct radeon_hpd hpd;
 925 };
 926
 927 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 928                                                                  drm_device
 929                                                                  *dev)
 930 {
 931         struct radeon_device *rdev = dev->dev_private;
 932         struct radeon_mode_info *mode_info = &rdev->mode_info;
 933         struct atom_context *ctx = mode_info->atom_context;
 934         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 935         uint16_t size, data_offset;
 936         uint8_t frev, crev;
 937         uint16_t device_support;
 938         uint8_t dac;
 939         union atom_supported_devices *supported_devices;
 940         int i, j, max_device;
 941         struct bios_connector *bios_connectors;
 942         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 943         struct radeon_router router;
 944
 945         router.ddc_valid = false;
 946         router.cd_valid = false;
 947
 948         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 949         if (!bios_connectors)
 950                 return false;
 951
 952         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 953                                     &data_offset)) {
 954                 kfree(bios_connectors);
 955                 return false;
 956         }
 957
 958         supported_devices =
 959             (union atom_supported_devices *)(ctx->bios + data_offset);
 960
 961         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 962
 963         if (frev > 1)
 964                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 965         else
 966                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 967
 968         for (i = 0; i < max_device; i++) {
 969                 ATOM_CONNECTOR_INFO_I2C ci =
 970                     supported_devices->info.asConnInfo[i];
 971
 972                 bios_connectors[i].valid = false;
 973
 974                 if (!(device_support & (1 << i))) {
 975                         continue;
 976                 }
 977
 978                 if (i == ATOM_DEVICE_CV_INDEX) {
 979                         DRM_DEBUG_KMS("Skipping Component Video\n");
 980                         continue;
 981                 }
 982
 983                 bios_connectors[i].connector_type =
 984                     supported_devices_connector_convert[ci.sucConnectorInfo.
 985                                                         sbfAccess.
 986                                                         bfConnectorType];
 987
 988                 if (bios_connectors[i].connector_type ==
 989                     DRM_MODE_CONNECTOR_Unknown)
 990                         continue;
 991
 992                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 993
 994                 bios_connectors[i].line_mux =
 995                         ci.sucI2cId.ucAccess;
 996
 997                 /* give tv unique connector ids */
 998                 if (i == ATOM_DEVICE_TV1_INDEX) {
 999                         bios_connectors[i].ddc_bus.valid = false;
1000                         bios_connectors[i].line_mux = 50;
1001                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
1002                         bios_connectors[i].ddc_bus.valid = false;
1003                         bios_connectors[i].line_mux = 51;
1004                 } else if (i == ATOM_DEVICE_CV_INDEX) {
1005                         bios_connectors[i].ddc_bus.valid = false;
1006                         bios_connectors[i].line_mux = 52;
1007                 } else
1008                         bios_connectors[i].ddc_bus =
1009                             radeon_lookup_i2c_gpio(rdev,
1010                                                    bios_connectors[i].line_mux);
1011
1012                 if ((crev > 1) && (frev > 1)) {
1013                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
1014                         switch (isb) {
1015                         case 0x4:
1016                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1017                                 break;
1018                         case 0xa:
1019                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1020                                 break;
1021                         default:
1022                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1023                                 break;
1024                         }
1025                 } else {
1026                         if (i == ATOM_DEVICE_DFP1_INDEX)
1027                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1028                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1029                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1030                         else
1031                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1032                 }
1033
1034                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1035                  * shared with a DVI port, we'll pick up the DVI connector when we
1036                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1037                  */
1038                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1039                         bios_connectors[i].connector_type =
1040                             DRM_MODE_CONNECTOR_VGA;
1041
1042                 if (!radeon_atom_apply_quirks
1043                     (dev, (1 << i), &bios_connectors[i].connector_type,
1044                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1045                      &bios_connectors[i].hpd))
1046                         continue;
1047
1048                 bios_connectors[i].valid = true;
1049                 bios_connectors[i].devices = (1 << i);
1050
1051                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1052                         radeon_add_atom_encoder(dev,
1053                                                 radeon_get_encoder_enum(dev,
1054                                                                       (1 << i),
1055                                                                       dac),
1056                                                 (1 << i),
1057                                                 0);
1058                 else
1059                         radeon_add_legacy_encoder(dev,
1060                                                   radeon_get_encoder_enum(dev,
1061                                                                         (1 << i),
1062                                                                         dac),
1063                                                   (1 << i));
1064         }
1065
1066         /* combine shared connectors */
1067         for (i = 0; i < max_device; i++) {
1068                 if (bios_connectors[i].valid) {
1069                         for (j = 0; j < max_device; j++) {
1070                                 if (bios_connectors[j].valid && (i != j)) {
1071                                         if (bios_connectors[i].line_mux ==
1072                                             bios_connectors[j].line_mux) {
1073                                                 /* make sure not to combine LVDS */
1074                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1075                                                         bios_connectors[i].line_mux = 53;
1076                                                         bios_connectors[i].ddc_bus.valid = false;
1077                                                         continue;
1078                                                 }
1079                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1080                                                         bios_connectors[j].line_mux = 53;
1081                                                         bios_connectors[j].ddc_bus.valid = false;
1082                                                         continue;
1083                                                 }
1084                                                 /* combine analog and digital for DVI-I */
1085                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1086                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1087                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1088                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1089                                                         bios_connectors[i].devices |=
1090                                                                 bios_connectors[j].devices;
1091                                                         bios_connectors[i].connector_type =
1092                                                                 DRM_MODE_CONNECTOR_DVII;
1093                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1094                                                                 bios_connectors[i].hpd =
1095                                                                         bios_connectors[j].hpd;
1096                                                         bios_connectors[j].valid = false;
1097                                                 }
1098                                         }
1099                                 }
1100                         }
1101                 }
1102         }
1103
1104         /* add the connectors */
1105         for (i = 0; i < max_device; i++) {
1106                 if (bios_connectors[i].valid) {
1107                         uint16_t connector_object_id =
1108                                 atombios_get_connector_object_id(dev,
1109                                                       bios_connectors[i].connector_type,
1110                                                       bios_connectors[i].devices);
1111                         radeon_add_atom_connector(dev,
1112                                                   bios_connectors[i].line_mux,
1113                                                   bios_connectors[i].devices,
1114                                                   bios_connectors[i].
1115                                                   connector_type,
1116                                                   &bios_connectors[i].ddc_bus,
1117                                                   0,
1118                                                   connector_object_id,
1119                                                   &bios_connectors[i].hpd,
1120                                                   &router);
1121                 }
1122         }
1123
1124         radeon_link_encoder_connector(dev);
1125
1126         kfree(bios_connectors);
1127         return true;
1128 }
1129
1130 union firmware_info {
1131         ATOM_FIRMWARE_INFO info;
1132         ATOM_FIRMWARE_INFO_V1_2 info_12;
1133         ATOM_FIRMWARE_INFO_V1_3 info_13;
1134         ATOM_FIRMWARE_INFO_V1_4 info_14;
1135         ATOM_FIRMWARE_INFO_V2_1 info_21;
1136         ATOM_FIRMWARE_INFO_V2_2 info_22;
1137 };
1138
1139 bool radeon_atom_get_clock_info(struct drm_device *dev)
1140 {
1141         struct radeon_device *rdev = dev->dev_private;
1142         struct radeon_mode_info *mode_info = &rdev->mode_info;
1143         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1144         union firmware_info *firmware_info;
1145         uint8_t frev, crev;
1146         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1147         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1148         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1149         struct radeon_pll *spll = &rdev->clock.spll;
1150         struct radeon_pll *mpll = &rdev->clock.mpll;
1151         uint16_t data_offset;
1152
1153         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1154                                    &frev, &crev, &data_offset)) {
1155                 firmware_info =
1156                         (union firmware_info *)(mode_info->atom_context->bios +
1157                                                 data_offset);
1158                 /* pixel clocks */
1159                 p1pll->reference_freq =
1160                     le16_to_cpu(firmware_info->info.usReferenceClock);
1161                 p1pll->reference_div = 0;
1162
1163                 if (crev < 2)
1164                         p1pll->pll_out_min =
1165                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1166                 else
1167                         p1pll->pll_out_min =
1168                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1169                 p1pll->pll_out_max =
1170                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1171
1172                 if (crev >= 4) {
1173                         p1pll->lcd_pll_out_min =
1174                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1175                         if (p1pll->lcd_pll_out_min == 0)
1176                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1177                         p1pll->lcd_pll_out_max =
1178                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1179                         if (p1pll->lcd_pll_out_max == 0)
1180                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1181                 } else {
1182                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1183                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1184                 }
1185
1186                 if (p1pll->pll_out_min == 0) {
1187                         if (ASIC_IS_AVIVO(rdev))
1188                                 p1pll->pll_out_min = 64800;
1189                         else
1190                                 p1pll->pll_out_min = 20000;
1191                 }
1192
1193                 p1pll->pll_in_min =
1194                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1195                 p1pll->pll_in_max =
1196                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1197
1198                 *p2pll = *p1pll;
1199
1200                 /* system clock */
1201                 if (ASIC_IS_DCE4(rdev))
1202                         spll->reference_freq =
1203                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1204                 else
1205                         spll->reference_freq =
1206                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1207                 spll->reference_div = 0;
1208
1209                 spll->pll_out_min =
1210                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1211                 spll->pll_out_max =
1212                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1213
1214                 /* ??? */
1215                 if (spll->pll_out_min == 0) {
1216                         if (ASIC_IS_AVIVO(rdev))
1217                                 spll->pll_out_min = 64800;
1218                         else
1219                                 spll->pll_out_min = 20000;
1220                 }
1221
1222                 spll->pll_in_min =
1223                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1224                 spll->pll_in_max =
1225                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1226
1227                 /* memory clock */
1228                 if (ASIC_IS_DCE4(rdev))
1229                         mpll->reference_freq =
1230                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1231                 else
1232                         mpll->reference_freq =
1233                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1234                 mpll->reference_div = 0;
1235
1236                 mpll->pll_out_min =
1237                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1238                 mpll->pll_out_max =
1239                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1240
1241                 /* ??? */
1242                 if (mpll->pll_out_min == 0) {
1243                         if (ASIC_IS_AVIVO(rdev))
1244                                 mpll->pll_out_min = 64800;
1245                         else
1246                                 mpll->pll_out_min = 20000;
1247                 }
1248
1249                 mpll->pll_in_min =
1250                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1251                 mpll->pll_in_max =
1252                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1253
1254                 rdev->clock.default_sclk =
1255                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1256                 rdev->clock.default_mclk =
1257                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1258
1259                 if (ASIC_IS_DCE4(rdev)) {
1260                         rdev->clock.default_dispclk =
1261                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1262                         if (rdev->clock.default_dispclk == 0) {
1263                                 if (ASIC_IS_DCE5(rdev))
1264                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1265                                 else
1266                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1267                         }
1268                         rdev->clock.dp_extclk =
1269                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1270                 }
1271                 *dcpll = *p1pll;
1272
1273                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1274                 if (rdev->clock.max_pixel_clock == 0)
1275                         rdev->clock.max_pixel_clock = 40000;
1276
1277                 return true;
1278         }
1279
1280         return false;
1281 }
1282
1283 union igp_info {
1284         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1285         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1286 };
1287
1288 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1289 {
1290         struct radeon_mode_info *mode_info = &rdev->mode_info;
1291         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1292         union igp_info *igp_info;
1293         u8 frev, crev;
1294         u16 data_offset;
1295
1296         /* sideport is AMD only */
1297         if (rdev->family == CHIP_RS600)
1298                 return false;
1299
1300         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1301                                    &frev, &crev, &data_offset)) {
1302                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1303                                       data_offset);
1304                 switch (crev) {
1305                 case 1:
1306                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1307                                 return true;
1308                         break;
1309                 case 2:
1310                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1311                                 return true;
1312                         break;
1313                 default:
1314                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1315                         break;
1316                 }
1317         }
1318         return false;
1319 }
1320
1321 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1322                                    struct radeon_encoder_int_tmds *tmds)
1323 {
1324         struct drm_device *dev = encoder->base.dev;
1325         struct radeon_device *rdev = dev->dev_private;
1326         struct radeon_mode_info *mode_info = &rdev->mode_info;
1327         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1328         uint16_t data_offset;
1329         struct _ATOM_TMDS_INFO *tmds_info;
1330         uint8_t frev, crev;
1331         uint16_t maxfreq;
1332         int i;
1333
1334         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1335                                    &frev, &crev, &data_offset)) {
1336                 tmds_info =
1337                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1338                                                    data_offset);
1339
1340                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1341                 for (i = 0; i < 4; i++) {
1342                         tmds->tmds_pll[i].freq =
1343                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1344                         tmds->tmds_pll[i].value =
1345                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1346                         tmds->tmds_pll[i].value |=
1347                             (tmds_info->asMiscInfo[i].
1348                              ucPLL_VCO_Gain & 0x3f) << 6;
1349                         tmds->tmds_pll[i].value |=
1350                             (tmds_info->asMiscInfo[i].
1351                              ucPLL_DutyCycle & 0xf) << 12;
1352                         tmds->tmds_pll[i].value |=
1353                             (tmds_info->asMiscInfo[i].
1354                              ucPLL_VoltageSwing & 0xf) << 16;
1355
1356                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1357                                   tmds->tmds_pll[i].freq,
1358                                   tmds->tmds_pll[i].value);
1359
1360                         if (maxfreq == tmds->tmds_pll[i].freq) {
1361                                 tmds->tmds_pll[i].freq = 0xffffffff;
1362                                 break;
1363                         }
1364                 }
1365                 return true;
1366         }
1367         return false;
1368 }
1369
1370 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1371                                       struct radeon_atom_ss *ss,
1372                                       int id)
1373 {
1374         struct radeon_mode_info *mode_info = &rdev->mode_info;
1375         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1376         uint16_t data_offset, size;
1377         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1378         uint8_t frev, crev;
1379         int i, num_indices;
1380
1381         memset(ss, 0, sizeof(struct radeon_atom_ss));
1382         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1383                                    &frev, &crev, &data_offset)) {
1384                 ss_info =
1385                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1386
1387                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1388                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1389
1390                 for (i = 0; i < num_indices; i++) {
1391                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1392                                 ss->percentage =
1393                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1394                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1395                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1396                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1397                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1398                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1399                                 return true;
1400                         }
1401                 }
1402         }
1403         return false;
1404 }
1405
1406 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1407                                                  struct radeon_atom_ss *ss,
1408                                                  int id)
1409 {
1410         struct radeon_mode_info *mode_info = &rdev->mode_info;
1411         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1412         u16 data_offset, size;
1413         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1414         u8 frev, crev;
1415         u16 percentage = 0, rate = 0;
1416
1417         /* get any igp specific overrides */
1418         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1419                                    &frev, &crev, &data_offset)) {
1420                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1421                         (mode_info->atom_context->bios + data_offset);
1422                 switch (id) {
1423                 case ASIC_INTERNAL_SS_ON_TMDS:
1424                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1425                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1426                         break;
1427                 case ASIC_INTERNAL_SS_ON_HDMI:
1428                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1429                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1430                         break;
1431                 case ASIC_INTERNAL_SS_ON_LVDS:
1432                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1433                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1434                         break;
1435                 }
1436                 if (percentage)
1437                         ss->percentage = percentage;
1438                 if (rate)
1439                         ss->rate = rate;
1440         }
1441 }
1442
1443 union asic_ss_info {
1444         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1445         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1446         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1447 };
1448
1449 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1450                                       struct radeon_atom_ss *ss,
1451                                       int id, u32 clock)
1452 {
1453         struct radeon_mode_info *mode_info = &rdev->mode_info;
1454         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1455         uint16_t data_offset, size;
1456         union asic_ss_info *ss_info;
1457         uint8_t frev, crev;
1458         int i, num_indices;
1459
1460         memset(ss, 0, sizeof(struct radeon_atom_ss));
1461         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1462                                    &frev, &crev, &data_offset)) {
1463
1464                 ss_info =
1465                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1466
1467                 switch (frev) {
1468                 case 1:
1469                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1470                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1471
1472                         for (i = 0; i < num_indices; i++) {
1473                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1474                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1475                                         ss->percentage =
1476                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1477                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1478                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1479                                         return true;
1480                                 }
1481                         }
1482                         break;
1483                 case 2:
1484                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1485                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1486                         for (i = 0; i < num_indices; i++) {
1487                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1488                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1489                                         ss->percentage =
1490                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1491                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1492                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1493                                         return true;
1494                                 }
1495                         }
1496                         break;
1497                 case 3:
1498                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1499                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1500                         for (i = 0; i < num_indices; i++) {
1501                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1502                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1503                                         ss->percentage =
1504                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1505                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1506                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1507                                         if (rdev->flags & RADEON_IS_IGP)
1508                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1509                                         return true;
1510                                 }
1511                         }
1512                         break;
1513                 default:
1514                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1515                         break;
1516                 }
1517
1518         }
1519         return false;
1520 }
1521
1522 union lvds_info {
1523         struct _ATOM_LVDS_INFO info;
1524         struct _ATOM_LVDS_INFO_V12 info_12;
1525 };
1526
1527 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1528                                                               radeon_encoder
1529                                                               *encoder)
1530 {
1531         struct drm_device *dev = encoder->base.dev;
1532         struct radeon_device *rdev = dev->dev_private;
1533         struct radeon_mode_info *mode_info = &rdev->mode_info;
1534         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1535         uint16_t data_offset, misc;
1536         union lvds_info *lvds_info;
1537         uint8_t frev, crev;
1538         struct radeon_encoder_atom_dig *lvds = NULL;
1539         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1540
1541         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1542                                    &frev, &crev, &data_offset)) {
1543                 lvds_info =
1544                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1545                 lvds =
1546                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1547
1548                 if (!lvds)
1549                         return NULL;
1550
1551                 lvds->native_mode.clock =
1552                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1553                 lvds->native_mode.hdisplay =
1554                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1555                 lvds->native_mode.vdisplay =
1556                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1557                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1558                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1559                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1560                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1561                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1562                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1563                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1564                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1565                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1566                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1567                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1568                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1569                 lvds->panel_pwr_delay =
1570                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1571                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1572
1573                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1574                 if (misc & ATOM_VSYNC_POLARITY)
1575                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1576                 if (misc & ATOM_HSYNC_POLARITY)
1577                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1578                 if (misc & ATOM_COMPOSITESYNC)
1579                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1580                 if (misc & ATOM_INTERLACE)
1581                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1582                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1583                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1584
1585                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1586                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1587
1588                 /* set crtc values */
1589                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1590
1591                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1592
1593                 encoder->native_mode = lvds->native_mode;
1594
1595                 if (encoder_enum == 2)
1596                         lvds->linkb = true;
1597                 else
1598                         lvds->linkb = false;
1599
1600                 /* parse the lcd record table */
1601                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1602                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1603                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1604                         bool bad_record = false;
1605                         u8 *record;
1606
1607                         if ((frev == 1) && (crev < 2))
1608                                 /* absolute */
1609                                 record = (u8 *)(mode_info->atom_context->bios +
1610                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1611                         else
1612                                 /* relative */
1613                                 record = (u8 *)(mode_info->atom_context->bios +
1614                                                 data_offset +
1615                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1616                         while (*record != ATOM_RECORD_END_TYPE) {
1617                                 switch (*record) {
1618                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1619                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1620                                         break;
1621                                 case LCD_RTS_RECORD_TYPE:
1622                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1623                                         break;
1624                                 case LCD_CAP_RECORD_TYPE:
1625                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1626                                         break;
1627                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1628                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1629                                         if (fake_edid_record->ucFakeEDIDLength) {
1630                                                 struct edid *edid;
1631                                                 int edid_size =
1632                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1633                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1634                                                 if (edid) {
1635                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1636                                                                fake_edid_record->ucFakeEDIDLength);
1637
1638                                                         if (drm_edid_is_valid(edid)) {
1639                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1640                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1641                                                         } else
1642                                                                 kfree(edid);
1643                                                 }
1644                                         }
1645                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1646                                         break;
1647                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1648                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1649                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1650                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1651                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1652                                         break;
1653                                 default:
1654                                         DRM_ERROR("Bad LCD record %d\n", *record);
1655                                         bad_record = true;
1656                                         break;
1657                                 }
1658                                 if (bad_record)
1659                                         break;
1660                         }
1661                 }
1662         }
1663         return lvds;
1664 }
1665
1666 struct radeon_encoder_primary_dac *
1667 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1668 {
1669         struct drm_device *dev = encoder->base.dev;
1670         struct radeon_device *rdev = dev->dev_private;
1671         struct radeon_mode_info *mode_info = &rdev->mode_info;
1672         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1673         uint16_t data_offset;
1674         struct _COMPASSIONATE_DATA *dac_info;
1675         uint8_t frev, crev;
1676         uint8_t bg, dac;
1677         struct radeon_encoder_primary_dac *p_dac = NULL;
1678
1679         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1680                                    &frev, &crev, &data_offset)) {
1681                 dac_info = (struct _COMPASSIONATE_DATA *)
1682                         (mode_info->atom_context->bios + data_offset);
1683
1684                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1685
1686                 if (!p_dac)
1687                         return NULL;
1688
1689                 bg = dac_info->ucDAC1_BG_Adjustment;
1690                 dac = dac_info->ucDAC1_DAC_Adjustment;
1691                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1692
1693         }
1694         return p_dac;
1695 }
1696
1697 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1698                                 struct drm_display_mode *mode)
1699 {
1700         struct radeon_mode_info *mode_info = &rdev->mode_info;
1701         ATOM_ANALOG_TV_INFO *tv_info;
1702         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1703         ATOM_DTD_FORMAT *dtd_timings;
1704         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1705         u8 frev, crev;
1706         u16 data_offset, misc;
1707
1708         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1709                                     &frev, &crev, &data_offset))
1710                 return false;
1711
1712         switch (crev) {
1713         case 1:
1714                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1715                 if (index >= MAX_SUPPORTED_TV_TIMING)
1716                         return false;
1717
1718                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1719                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1720                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1721                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1722                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1723
1724                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1725                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1726                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1727                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1728                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1729
1730                 mode->flags = 0;
1731                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1732                 if (misc & ATOM_VSYNC_POLARITY)
1733                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1734                 if (misc & ATOM_HSYNC_POLARITY)
1735                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1736                 if (misc & ATOM_COMPOSITESYNC)
1737                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1738                 if (misc & ATOM_INTERLACE)
1739                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1740                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1741                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1742
1743                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1744
1745                 if (index == 1) {
1746                         /* PAL timings appear to have wrong values for totals */
1747                         mode->crtc_htotal -= 1;
1748                         mode->crtc_vtotal -= 1;
1749                 }
1750                 break;
1751         case 2:
1752                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1753                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1754                         return false;
1755
1756                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1757                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1758                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1759                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1760                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1761                         le16_to_cpu(dtd_timings->usHSyncOffset);
1762                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1763                         le16_to_cpu(dtd_timings->usHSyncWidth);
1764
1765                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1766                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1767                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1768                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1769                         le16_to_cpu(dtd_timings->usVSyncOffset);
1770                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1771                         le16_to_cpu(dtd_timings->usVSyncWidth);
1772
1773                 mode->flags = 0;
1774                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1775                 if (misc & ATOM_VSYNC_POLARITY)
1776                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1777                 if (misc & ATOM_HSYNC_POLARITY)
1778                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1779                 if (misc & ATOM_COMPOSITESYNC)
1780                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1781                 if (misc & ATOM_INTERLACE)
1782                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1783                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1784                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1785
1786                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1787                 break;
1788         }
1789         return true;
1790 }
1791
1792 enum radeon_tv_std
1793 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1794 {
1795         struct radeon_mode_info *mode_info = &rdev->mode_info;
1796         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1797         uint16_t data_offset;
1798         uint8_t frev, crev;
1799         struct _ATOM_ANALOG_TV_INFO *tv_info;
1800         enum radeon_tv_std tv_std = TV_STD_NTSC;
1801
1802         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1803                                    &frev, &crev, &data_offset)) {
1804
1805                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1806                         (mode_info->atom_context->bios + data_offset);
1807
1808                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1809                 case ATOM_TV_NTSC:
1810                         tv_std = TV_STD_NTSC;
1811                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1812                         break;
1813                 case ATOM_TV_NTSCJ:
1814                         tv_std = TV_STD_NTSC_J;
1815                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1816                         break;
1817                 case ATOM_TV_PAL:
1818                         tv_std = TV_STD_PAL;
1819                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1820                         break;
1821                 case ATOM_TV_PALM:
1822                         tv_std = TV_STD_PAL_M;
1823                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1824                         break;
1825                 case ATOM_TV_PALN:
1826                         tv_std = TV_STD_PAL_N;
1827                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1828                         break;
1829                 case ATOM_TV_PALCN:
1830                         tv_std = TV_STD_PAL_CN;
1831                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1832                         break;
1833                 case ATOM_TV_PAL60:
1834                         tv_std = TV_STD_PAL_60;
1835                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1836                         break;
1837                 case ATOM_TV_SECAM:
1838                         tv_std = TV_STD_SECAM;
1839                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1840                         break;
1841                 default:
1842                         tv_std = TV_STD_NTSC;
1843                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1844                         break;
1845                 }
1846         }
1847         return tv_std;
1848 }
1849
1850 struct radeon_encoder_tv_dac *
1851 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1852 {
1853         struct drm_device *dev = encoder->base.dev;
1854         struct radeon_device *rdev = dev->dev_private;
1855         struct radeon_mode_info *mode_info = &rdev->mode_info;
1856         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1857         uint16_t data_offset;
1858         struct _COMPASSIONATE_DATA *dac_info;
1859         uint8_t frev, crev;
1860         uint8_t bg, dac;
1861         struct radeon_encoder_tv_dac *tv_dac = NULL;
1862
1863         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1864                                    &frev, &crev, &data_offset)) {
1865
1866                 dac_info = (struct _COMPASSIONATE_DATA *)
1867                         (mode_info->atom_context->bios + data_offset);
1868
1869                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1870
1871                 if (!tv_dac)
1872                         return NULL;
1873
1874                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1875                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1876                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1877
1878                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1879                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1880                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1881
1882                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1883                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1884                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1885
1886                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1887         }
1888         return tv_dac;
1889 }
1890
1891 static const char *thermal_controller_names[] = {
1892         "NONE",
1893         "lm63",
1894         "adm1032",
1895         "adm1030",
1896         "max6649",
1897         "lm64",
1898         "f75375",
1899         "asc7xxx",
1900 };
1901
1902 static const char *pp_lib_thermal_controller_names[] = {
1903         "NONE",
1904         "lm63",
1905         "adm1032",
1906         "adm1030",
1907         "max6649",
1908         "lm64",
1909         "f75375",
1910         "RV6xx",
1911         "RV770",
1912         "adt7473",
1913         "NONE",
1914         "External GPIO",
1915         "Evergreen",
1916         "emc2103",
1917         "Sumo",
1918         "Northern Islands",
1919 };
1920
1921 union power_info {
1922         struct _ATOM_POWERPLAY_INFO info;
1923         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1924         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1925         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1926         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1927         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1928 };
1929
1930 union pplib_clock_info {
1931         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1932         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1933         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1934         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1935 };
1936
1937 union pplib_power_state {
1938         struct _ATOM_PPLIB_STATE v1;
1939         struct _ATOM_PPLIB_STATE_V2 v2;
1940 };
1941
1942 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1943                                                  int state_index,
1944                                                  u32 misc, u32 misc2)
1945 {
1946         rdev->pm.power_state[state_index].misc = misc;
1947         rdev->pm.power_state[state_index].misc2 = misc2;
1948         /* order matters! */
1949         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1950                 rdev->pm.power_state[state_index].type =
1951                         POWER_STATE_TYPE_POWERSAVE;
1952         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1953                 rdev->pm.power_state[state_index].type =
1954                         POWER_STATE_TYPE_BATTERY;
1955         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1956                 rdev->pm.power_state[state_index].type =
1957                         POWER_STATE_TYPE_BATTERY;
1958         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1959                 rdev->pm.power_state[state_index].type =
1960                         POWER_STATE_TYPE_BALANCED;
1961         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1962                 rdev->pm.power_state[state_index].type =
1963                         POWER_STATE_TYPE_PERFORMANCE;
1964                 rdev->pm.power_state[state_index].flags &=
1965                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1966         }
1967         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1968                 rdev->pm.power_state[state_index].type =
1969                         POWER_STATE_TYPE_BALANCED;
1970         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1971                 rdev->pm.power_state[state_index].type =
1972                         POWER_STATE_TYPE_DEFAULT;
1973                 rdev->pm.default_power_state_index = state_index;
1974                 rdev->pm.power_state[state_index].default_clock_mode =
1975                         &rdev->pm.power_state[state_index].clock_info[0];
1976         } else if (state_index == 0) {
1977                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1978                         RADEON_PM_MODE_NO_DISPLAY;
1979         }
1980 }
1981
1982 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1983 {
1984         struct radeon_mode_info *mode_info = &rdev->mode_info;
1985         u32 misc, misc2 = 0;
1986         int num_modes = 0, i;
1987         int state_index = 0;
1988         struct radeon_i2c_bus_rec i2c_bus;
1989         union power_info *power_info;
1990         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1991         u16 data_offset;
1992         u8 frev, crev;
1993
1994         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1995                                    &frev, &crev, &data_offset))
1996                 return state_index;
1997         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1998
1999         /* add the i2c bus for thermal/fan chip */
2000         if (power_info->info.ucOverdriveThermalController > 0) {
2001                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2002                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2003                          power_info->info.ucOverdriveControllerAddress >> 1);
2004                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2005                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2006                 if (rdev->pm.i2c_bus) {
2007                         struct i2c_board_info info = { };
2008                         const char *name = thermal_controller_names[power_info->info.
2009                                                                     ucOverdriveThermalController];
2010                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2011                         strlcpy(info.type, name, sizeof(info.type));
2012                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2013                 }
2014         }
2015         num_modes = power_info->info.ucNumOfPowerModeEntries;
2016         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2017                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2018         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2019         if (!rdev->pm.power_state)
2020                 return state_index;
2021         /* last mode is usually default, array is low to high */
2022         for (i = 0; i < num_modes; i++) {
2023                 rdev->pm.power_state[state_index].clock_info =
2024                         kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2025                 if (!rdev->pm.power_state[state_index].clock_info)
2026                         return state_index;
2027                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2028                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2029                 switch (frev) {
2030                 case 1:
2031                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2032                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2033                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2034                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2035                         /* skip invalid modes */
2036                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2037                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2038                                 continue;
2039                         rdev->pm.power_state[state_index].pcie_lanes =
2040                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2041                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2042                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2043                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2044                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2045                                         VOLTAGE_GPIO;
2046                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2047                                         radeon_lookup_gpio(rdev,
2048                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2049                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2050                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2051                                                 true;
2052                                 else
2053                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2054                                                 false;
2055                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2056                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2057                                         VOLTAGE_VDDC;
2058                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2059                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2060                         }
2061                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2062                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2063                         state_index++;
2064                         break;
2065                 case 2:
2066                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2067                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2068                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2069                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2070                         /* skip invalid modes */
2071                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2072                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2073                                 continue;
2074                         rdev->pm.power_state[state_index].pcie_lanes =
2075                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2076                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2077                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2078                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2079                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2080                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2081                                         VOLTAGE_GPIO;
2082                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2083                                         radeon_lookup_gpio(rdev,
2084                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2085                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2086                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2087                                                 true;
2088                                 else
2089                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2090                                                 false;
2091                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2092                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2093                                         VOLTAGE_VDDC;
2094                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2095                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2096                         }
2097                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2098                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2099                         state_index++;
2100                         break;
2101                 case 3:
2102                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2103                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2104                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2105                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2106                         /* skip invalid modes */
2107                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2108                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2109                                 continue;
2110                         rdev->pm.power_state[state_index].pcie_lanes =
2111                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2112                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2113                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2114                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2115                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2116                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2117                                         VOLTAGE_GPIO;
2118                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2119                                         radeon_lookup_gpio(rdev,
2120                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2121                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2122                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2123                                                 true;
2124                                 else
2125                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2126                                                 false;
2127                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2128                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2129                                         VOLTAGE_VDDC;
2130                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2131                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2132                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2133                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2134                                                 true;
2135                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2136                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2137                                 }
2138                         }
2139                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2140                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2141                         state_index++;
2142                         break;
2143                 }
2144         }
2145         /* last mode is usually default */
2146         if (rdev->pm.default_power_state_index == -1) {
2147                 rdev->pm.power_state[state_index - 1].type =
2148                         POWER_STATE_TYPE_DEFAULT;
2149                 rdev->pm.default_power_state_index = state_index - 1;
2150                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2151                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2152                 rdev->pm.power_state[state_index].flags &=
2153                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2154                 rdev->pm.power_state[state_index].misc = 0;
2155                 rdev->pm.power_state[state_index].misc2 = 0;
2156         }
2157         return state_index;
2158 }
2159
2160 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2161                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2162 {
2163         struct radeon_i2c_bus_rec i2c_bus;
2164
2165         /* add the i2c bus for thermal/fan chip */
2166         if (controller->ucType > 0) {
2167                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2168                         DRM_INFO("Internal thermal controller %s fan control\n",
2169                                  (controller->ucFanParameters &
2170                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2171                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2172                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2173                         DRM_INFO("Internal thermal controller %s fan control\n",
2174                                  (controller->ucFanParameters &
2175                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2176                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2177                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2178                         DRM_INFO("Internal thermal controller %s fan control\n",
2179                                  (controller->ucFanParameters &
2180                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2181                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2182                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2183                         DRM_INFO("Internal thermal controller %s fan control\n",
2184                                  (controller->ucFanParameters &
2185                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2186                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2187                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2188                         DRM_INFO("Internal thermal controller %s fan control\n",
2189                                  (controller->ucFanParameters &
2190                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2191                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2192                 } else if ((controller->ucType ==
2193                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2194                            (controller->ucType ==
2195                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2196                            (controller->ucType ==
2197                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2198                         DRM_INFO("Special thermal controller config\n");
2199                 } else {
2200                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2201                                  pp_lib_thermal_controller_names[controller->ucType],
2202                                  controller->ucI2cAddress >> 1,
2203                                  (controller->ucFanParameters &
2204                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2205                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2206                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2207                         if (rdev->pm.i2c_bus) {
2208                                 struct i2c_board_info info = { };
2209                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2210                                 info.addr = controller->ucI2cAddress >> 1;
2211                                 strlcpy(info.type, name, sizeof(info.type));
2212                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2213                         }
2214                 }
2215         }
2216 }
2217
2218 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2219                                                  u16 *vddc, u16 *vddci)
2220 {
2221         struct radeon_mode_info *mode_info = &rdev->mode_info;
2222         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2223         u8 frev, crev;
2224         u16 data_offset;
2225         union firmware_info *firmware_info;
2226
2227         *vddc = 0;
2228         *vddci = 0;
2229
2230         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2231                                    &frev, &crev, &data_offset)) {
2232                 firmware_info =
2233                         (union firmware_info *)(mode_info->atom_context->bios +
2234                                                 data_offset);
2235                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2236                 if ((frev == 2) && (crev >= 2))
2237                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2238         }
2239 }
2240
2241 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2242                                                        int state_index, int mode_index,
2243                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2244 {
2245         int j;
2246         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2247         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2248         u16 vddc, vddci;
2249
2250         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2251
2252         rdev->pm.power_state[state_index].misc = misc;
2253         rdev->pm.power_state[state_index].misc2 = misc2;
2254         rdev->pm.power_state[state_index].pcie_lanes =
2255                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2256                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2257         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2258         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2259                 rdev->pm.power_state[state_index].type =
2260                         POWER_STATE_TYPE_BATTERY;
2261                 break;
2262         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2263                 rdev->pm.power_state[state_index].type =
2264                         POWER_STATE_TYPE_BALANCED;
2265                 break;
2266         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2267                 rdev->pm.power_state[state_index].type =
2268                         POWER_STATE_TYPE_PERFORMANCE;
2269                 break;
2270         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2271                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2272                         rdev->pm.power_state[state_index].type =
2273                                 POWER_STATE_TYPE_PERFORMANCE;
2274                 break;
2275         }
2276         rdev->pm.power_state[state_index].flags = 0;
2277         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2278                 rdev->pm.power_state[state_index].flags |=
2279                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2280         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2281                 rdev->pm.power_state[state_index].type =
2282                         POWER_STATE_TYPE_DEFAULT;
2283                 rdev->pm.default_power_state_index = state_index;
2284                 rdev->pm.power_state[state_index].default_clock_mode =
2285                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2286                 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2287                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2288                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2289                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2290                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2291                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2292                 } else {
2293                         /* patch the table values with the default slck/mclk from firmware info */
2294                         for (j = 0; j < mode_index; j++) {
2295                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2296                                         rdev->clock.default_mclk;
2297                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2298                                         rdev->clock.default_sclk;
2299                                 if (vddc)
2300                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2301                                                 vddc;
2302                         }
2303                 }
2304         }
2305 }
2306
2307 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2308                                                    int state_index, int mode_index,
2309                                                    union pplib_clock_info *clock_info)
2310 {
2311         u32 sclk, mclk;
2312
2313         if (rdev->flags & RADEON_IS_IGP) {
2314                 if (rdev->family >= CHIP_PALM) {
2315                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2316                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2317                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2318                 } else {
2319                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2320                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2321                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2322                 }
2323         } else if (ASIC_IS_DCE4(rdev)) {
2324                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2325                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2326                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2327                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2328                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2329                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2330                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2331                         VOLTAGE_SW;
2332                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2333                         le16_to_cpu(clock_info->evergreen.usVDDC);
2334                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2335                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2336         } else {
2337                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2338                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2339                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2340                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2341                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2342                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2343                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2344                         VOLTAGE_SW;
2345                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2346                         le16_to_cpu(clock_info->r600.usVDDC);
2347         }
2348
2349         /* patch up vddc if necessary */
2350         if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2351                 u16 vddc;
2352
2353                 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2354                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2355         }
2356
2357         if (rdev->flags & RADEON_IS_IGP) {
2358                 /* skip invalid modes */
2359                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2360                         return false;
2361         } else {
2362                 /* skip invalid modes */
2363                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2364                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2365                         return false;
2366         }
2367         return true;
2368 }
2369
2370 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2371 {
2372         struct radeon_mode_info *mode_info = &rdev->mode_info;
2373         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2374         union pplib_power_state *power_state;
2375         int i, j;
2376         int state_index = 0, mode_index = 0;
2377         union pplib_clock_info *clock_info;
2378         bool valid;
2379         union power_info *power_info;
2380         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2381         u16 data_offset;
2382         u8 frev, crev;
2383
2384         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2385                                    &frev, &crev, &data_offset))
2386                 return state_index;
2387         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2388
2389         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2390         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2391                                        power_info->pplib.ucNumStates, GFP_KERNEL);
2392         if (!rdev->pm.power_state)
2393                 return state_index;
2394         /* first mode is usually default, followed by low to high */
2395         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2396                 mode_index = 0;
2397                 power_state = (union pplib_power_state *)
2398                         (mode_info->atom_context->bios + data_offset +
2399                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2400                          i * power_info->pplib.ucStateEntrySize);
2401                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2402                         (mode_info->atom_context->bios + data_offset +
2403                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2404                          (power_state->v1.ucNonClockStateIndex *
2405                           power_info->pplib.ucNonClockSize));
2406                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2407                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2408                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2409                                                              GFP_KERNEL);
2410                 if (!rdev->pm.power_state[i].clock_info)
2411                         return state_index;
2412                 if (power_info->pplib.ucStateEntrySize - 1) {
2413                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2414                                 clock_info = (union pplib_clock_info *)
2415                                         (mode_info->atom_context->bios + data_offset +
2416                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2417                                          (power_state->v1.ucClockStateIndices[j] *
2418                                           power_info->pplib.ucClockInfoSize));
2419                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2420                                                                                state_index, mode_index,
2421                                                                                clock_info);
2422                                 if (valid)
2423                                         mode_index++;
2424                         }
2425                 } else {
2426                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2427                                 rdev->clock.default_mclk;
2428                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2429                                 rdev->clock.default_sclk;
2430                         mode_index++;
2431                 }
2432                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2433                 if (mode_index) {
2434                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2435                                                                    non_clock_info);
2436                         state_index++;
2437                 }
2438         }
2439         /* if multiple clock modes, mark the lowest as no display */
2440         for (i = 0; i < state_index; i++) {
2441                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2442                         rdev->pm.power_state[i].clock_info[0].flags |=
2443                                 RADEON_PM_MODE_NO_DISPLAY;
2444         }
2445         /* first mode is usually default */
2446         if (rdev->pm.default_power_state_index == -1) {
2447                 rdev->pm.power_state[0].type =
2448                         POWER_STATE_TYPE_DEFAULT;
2449                 rdev->pm.default_power_state_index = 0;
2450                 rdev->pm.power_state[0].default_clock_mode =
2451                         &rdev->pm.power_state[0].clock_info[0];
2452         }
2453         return state_index;
2454 }
2455
2456 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2457 {
2458         struct radeon_mode_info *mode_info = &rdev->mode_info;
2459         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2460         union pplib_power_state *power_state;
2461         int i, j, non_clock_array_index, clock_array_index;
2462         int state_index = 0, mode_index = 0;
2463         union pplib_clock_info *clock_info;
2464         struct StateArray *state_array;
2465         struct ClockInfoArray *clock_info_array;
2466         struct NonClockInfoArray *non_clock_info_array;
2467         bool valid;
2468         union power_info *power_info;
2469         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2470         u16 data_offset;
2471         u8 frev, crev;
2472
2473         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2474                                    &frev, &crev, &data_offset))
2475                 return state_index;
2476         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2477
2478         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2479         state_array = (struct StateArray *)
2480                 (mode_info->atom_context->bios + data_offset +
2481                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2482         clock_info_array = (struct ClockInfoArray *)
2483                 (mode_info->atom_context->bios + data_offset +
2484                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2485         non_clock_info_array = (struct NonClockInfoArray *)
2486                 (mode_info->atom_context->bios + data_offset +
2487                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2488         rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2489                                        state_array->ucNumEntries, GFP_KERNEL);
2490         if (!rdev->pm.power_state)
2491                 return state_index;
2492         for (i = 0; i < state_array->ucNumEntries; i++) {
2493                 mode_index = 0;
2494                 power_state = (union pplib_power_state *)&state_array->states[i];
2495                 /* XXX this might be an inagua bug... */
2496                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2497                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2498                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2499                 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2500                                                              (power_state->v2.ucNumDPMLevels ?
2501                                                               power_state->v2.ucNumDPMLevels : 1),
2502                                                              GFP_KERNEL);
2503                 if (!rdev->pm.power_state[i].clock_info)
2504                         return state_index;
2505                 if (power_state->v2.ucNumDPMLevels) {
2506                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2507                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2508                                 /* XXX this might be an inagua bug... */
2509                                 if (clock_array_index >= clock_info_array->ucNumEntries)
2510                                         continue;
2511                                 clock_info = (union pplib_clock_info *)
2512                                         &clock_info_array->clockInfo[clock_array_index];
2513                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2514                                                                                state_index, mode_index,
2515                                                                                clock_info);
2516                                 if (valid)
2517                                         mode_index++;
2518                         }
2519                 } else {
2520                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2521                                 rdev->clock.default_mclk;
2522                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2523                                 rdev->clock.default_sclk;
2524                         mode_index++;
2525                 }
2526                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2527                 if (mode_index) {
2528                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2529                                                                    non_clock_info);
2530                         state_index++;
2531                 }
2532         }
2533         /* if multiple clock modes, mark the lowest as no display */
2534         for (i = 0; i < state_index; i++) {
2535                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2536                         rdev->pm.power_state[i].clock_info[0].flags |=
2537                                 RADEON_PM_MODE_NO_DISPLAY;
2538         }
2539         /* first mode is usually default */
2540         if (rdev->pm.default_power_state_index == -1) {
2541                 rdev->pm.power_state[0].type =
2542                         POWER_STATE_TYPE_DEFAULT;
2543                 rdev->pm.default_power_state_index = 0;
2544                 rdev->pm.power_state[0].default_clock_mode =
2545                         &rdev->pm.power_state[0].clock_info[0];
2546         }
2547         return state_index;
2548 }
2549
2550 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2551 {
2552         struct radeon_mode_info *mode_info = &rdev->mode_info;
2553         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2554         u16 data_offset;
2555         u8 frev, crev;
2556         int state_index = 0;
2557
2558         rdev->pm.default_power_state_index = -1;
2559
2560         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2561                                    &frev, &crev, &data_offset)) {
2562                 switch (frev) {
2563                 case 1:
2564                 case 2:
2565                 case 3:
2566                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2567                         break;
2568                 case 4:
2569                 case 5:
2570                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2571                         break;
2572                 case 6:
2573                         state_index = radeon_atombios_parse_power_table_6(rdev);
2574                         break;
2575                 default:
2576                         break;
2577                 }
2578         } else {
2579                 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2580                 if (rdev->pm.power_state) {
2581                         rdev->pm.power_state[0].clock_info =
2582                                 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2583                         if (rdev->pm.power_state[0].clock_info) {
2584                                 /* add the default mode */
2585                                 rdev->pm.power_state[state_index].type =
2586                                         POWER_STATE_TYPE_DEFAULT;
2587                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2588                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2589                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2590                                 rdev->pm.power_state[state_index].default_clock_mode =
2591                                         &rdev->pm.power_state[state_index].clock_info[0];
2592                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2593                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2594                                 rdev->pm.default_power_state_index = state_index;
2595                                 rdev->pm.power_state[state_index].flags = 0;
2596                                 state_index++;
2597                         }
2598                 }
2599         }
2600
2601         rdev->pm.num_power_states = state_index;
2602
2603         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2604         rdev->pm.current_clock_mode_index = 0;
2605         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2606 }
2607
2608 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2609 {
2610         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2611         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2612
2613         args.ucEnable = enable;
2614
2615         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2616 }
2617
2618 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2619 {
2620         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2621         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2622
2623         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2624         return le32_to_cpu(args.ulReturnEngineClock);
2625 }
2626
2627 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2628 {
2629         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2630         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2631
2632         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2633         return le32_to_cpu(args.ulReturnMemoryClock);
2634 }
2635
2636 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2637                                   uint32_t eng_clock)
2638 {
2639         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2640         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2641
2642         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2643
2644         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2645 }
2646
2647 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2648                                   uint32_t mem_clock)
2649 {
2650         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2651         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2652
2653         if (rdev->flags & RADEON_IS_IGP)
2654                 return;
2655
2656         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2657
2658         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2659 }
2660
2661 union set_voltage {
2662         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2663         struct _SET_VOLTAGE_PARAMETERS v1;
2664         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2665 };
2666
2667 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2668 {
2669         union set_voltage args;
2670         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2671         u8 frev, crev, volt_index = voltage_level;
2672
2673         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2674                 return;
2675
2676         /* 0xff01 is a flag rather then an actual voltage */
2677         if (voltage_level == 0xff01)
2678                 return;
2679
2680         switch (crev) {
2681         case 1:
2682                 args.v1.ucVoltageType = voltage_type;
2683                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2684                 args.v1.ucVoltageIndex = volt_index;
2685                 break;
2686         case 2:
2687                 args.v2.ucVoltageType = voltage_type;
2688                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2689                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2690                 break;
2691         default:
2692                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2693                 return;
2694         }
2695
2696         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2697 }
2698
2699 int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2700                              u16 *voltage)
2701 {
2702         union set_voltage args;
2703         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2704         u8 frev, crev;
2705
2706         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2707                 return -EINVAL;
2708
2709         switch (crev) {
2710         case 1:
2711                 return -EINVAL;
2712         case 2:
2713                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2714                 args.v2.ucVoltageMode = 0;
2715                 args.v2.usVoltageLevel = 0;
2716
2717                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2718
2719                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2720                 break;
2721         default:
2722                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2723                 return -EINVAL;
2724         }
2725
2726         return 0;
2727 }
2728
2729 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2730 {
2731         struct radeon_device *rdev = dev->dev_private;
2732         uint32_t bios_2_scratch, bios_6_scratch;
2733
2734         if (rdev->family >= CHIP_R600) {
2735                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2736                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2737         } else {
2738                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2739                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2740         }
2741
2742         /* let the bios control the backlight */
2743         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2744
2745         /* tell the bios not to handle mode switching */
2746         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2747
2748         if (rdev->family >= CHIP_R600) {
2749                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2750                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2751         } else {
2752                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2753                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2754         }
2755
2756 }
2757
2758 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2759 {
2760         uint32_t scratch_reg;
2761         int i;
2762
2763         if (rdev->family >= CHIP_R600)
2764                 scratch_reg = R600_BIOS_0_SCRATCH;
2765         else
2766                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2767
2768         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2769                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2770 }
2771
2772 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2773 {
2774         uint32_t scratch_reg;
2775         int i;
2776
2777         if (rdev->family >= CHIP_R600)
2778                 scratch_reg = R600_BIOS_0_SCRATCH;
2779         else
2780                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2781
2782         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2783                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2784 }
2785
2786 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2787 {
2788         struct drm_device *dev = encoder->dev;
2789         struct radeon_device *rdev = dev->dev_private;
2790         uint32_t bios_6_scratch;
2791
2792         if (rdev->family >= CHIP_R600)
2793                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2794         else
2795                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2796
2797         if (lock) {
2798                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2799                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2800         } else {
2801                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2802                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2803         }
2804
2805         if (rdev->family >= CHIP_R600)
2806                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2807         else
2808                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2809 }
2810
2811 /* at some point we may want to break this out into individual functions */
2812 void
2813 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2814                                        struct drm_encoder *encoder,
2815                                        bool connected)
2816 {
2817         struct drm_device *dev = connector->dev;
2818         struct radeon_device *rdev = dev->dev_private;
2819         struct radeon_connector *radeon_connector =
2820             to_radeon_connector(connector);
2821         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2822         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2823
2824         if (rdev->family >= CHIP_R600) {
2825                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2826                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2827                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2828         } else {
2829                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2830                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2831                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2832         }
2833
2834         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2835             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2836                 if (connected) {
2837                         DRM_DEBUG_KMS("TV1 connected\n");
2838                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2839                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2840                 } else {
2841                         DRM_DEBUG_KMS("TV1 disconnected\n");
2842                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2843                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2844                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2845                 }
2846         }
2847         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2848             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2849                 if (connected) {
2850                         DRM_DEBUG_KMS("CV connected\n");
2851                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2852                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2853                 } else {
2854                         DRM_DEBUG_KMS("CV disconnected\n");
2855                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2856                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2857                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2858                 }
2859         }
2860         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2861             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2862                 if (connected) {
2863                         DRM_DEBUG_KMS("LCD1 connected\n");
2864                         bios_0_scratch |= ATOM_S0_LCD1;
2865                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2866                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2867                 } else {
2868                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2869                         bios_0_scratch &= ~ATOM_S0_LCD1;
2870                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2871                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2872                 }
2873         }
2874         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2875             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2876                 if (connected) {
2877                         DRM_DEBUG_KMS("CRT1 connected\n");
2878                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2879                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2880                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2881                 } else {
2882                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2883                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2884                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2885                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2886                 }
2887         }
2888         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2889             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2890                 if (connected) {
2891                         DRM_DEBUG_KMS("CRT2 connected\n");
2892                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2893                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2894                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2895                 } else {
2896                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2897                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2898                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2899                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2900                 }
2901         }
2902         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2903             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2904                 if (connected) {
2905                         DRM_DEBUG_KMS("DFP1 connected\n");
2906                         bios_0_scratch |= ATOM_S0_DFP1;
2907                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2908                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2909                 } else {
2910                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2911                         bios_0_scratch &= ~ATOM_S0_DFP1;
2912                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2913                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2914                 }
2915         }
2916         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2917             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2918                 if (connected) {
2919                         DRM_DEBUG_KMS("DFP2 connected\n");
2920                         bios_0_scratch |= ATOM_S0_DFP2;
2921                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2922                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2923                 } else {
2924                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2925                         bios_0_scratch &= ~ATOM_S0_DFP2;
2926                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2927                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2928                 }
2929         }
2930         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2931             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2932                 if (connected) {
2933                         DRM_DEBUG_KMS("DFP3 connected\n");
2934                         bios_0_scratch |= ATOM_S0_DFP3;
2935                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2936                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2937                 } else {
2938                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2939                         bios_0_scratch &= ~ATOM_S0_DFP3;
2940                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2941                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2942                 }
2943         }
2944         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2945             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2946                 if (connected) {
2947                         DRM_DEBUG_KMS("DFP4 connected\n");
2948                         bios_0_scratch |= ATOM_S0_DFP4;
2949                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2950                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2951                 } else {
2952                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2953                         bios_0_scratch &= ~ATOM_S0_DFP4;
2954                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2955                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2956                 }
2957         }
2958         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2959             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2960                 if (connected) {
2961                         DRM_DEBUG_KMS("DFP5 connected\n");
2962                         bios_0_scratch |= ATOM_S0_DFP5;
2963                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2964                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2965                 } else {
2966                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2967                         bios_0_scratch &= ~ATOM_S0_DFP5;
2968                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2969                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2970                 }
2971         }
2972
2973         if (rdev->family >= CHIP_R600) {
2974                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2975                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2976                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2977         } else {
2978                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2979                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2980                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2981         }
2982 }
2983
2984 void
2985 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2986 {
2987         struct drm_device *dev = encoder->dev;
2988         struct radeon_device *rdev = dev->dev_private;
2989         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2990         uint32_t bios_3_scratch;
2991
2992         if (rdev->family >= CHIP_R600)
2993                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2994         else
2995                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2996
2997         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2998                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2999                 bios_3_scratch |= (crtc << 18);
3000         }
3001         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3002                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3003                 bios_3_scratch |= (crtc << 24);
3004         }
3005         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3006                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3007                 bios_3_scratch |= (crtc << 16);
3008         }
3009         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3010                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3011                 bios_3_scratch |= (crtc << 20);
3012         }
3013         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3014                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3015                 bios_3_scratch |= (crtc << 17);
3016         }
3017         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3018                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3019                 bios_3_scratch |= (crtc << 19);
3020         }
3021         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3022                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3023                 bios_3_scratch |= (crtc << 23);
3024         }
3025         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3026                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3027                 bios_3_scratch |= (crtc << 25);
3028         }
3029
3030         if (rdev->family >= CHIP_R600)
3031                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3032         else
3033                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3034 }
3035
3036 void
3037 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3038 {
3039         struct drm_device *dev = encoder->dev;
3040         struct radeon_device *rdev = dev->dev_private;
3041         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3042         uint32_t bios_2_scratch;
3043
3044         if (rdev->family >= CHIP_R600)
3045                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3046         else
3047                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3048
3049         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3050                 if (on)
3051                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3052                 else
3053                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3054         }
3055         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3056                 if (on)
3057                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3058                 else
3059                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3060         }
3061         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3062                 if (on)
3063                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3064                 else
3065                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3066         }
3067         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3068                 if (on)
3069                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3070                 else
3071                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3072         }
3073         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3074                 if (on)
3075                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3076                 else
3077                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3078         }
3079         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3080                 if (on)
3081                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3082                 else
3083                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3084         }
3085         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3086                 if (on)
3087                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3088                 else
3089                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3090         }
3091         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3092                 if (on)
3093                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3094                 else
3095                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3096         }
3097         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3098                 if (on)
3099                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3100                 else
3101                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3102         }
3103         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3104                 if (on)
3105                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3106                 else
3107                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3108         }
3109
3110         if (rdev->family >= CHIP_R600)
3111                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3112         else
3113                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3114 }