2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <drm/radeon_drm.h>
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
40 /* from radeon_legacy_encoder.c */
42 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
43 uint32_t supported_device);
45 /* old legacy ATI BIOS routines */
47 /* COMBIOS table offsets */
48 enum radeon_combios_table_offset {
49 /* absolute offset tables */
50 COMBIOS_ASIC_INIT_1_TABLE,
51 COMBIOS_BIOS_SUPPORT_TABLE,
52 COMBIOS_DAC_PROGRAMMING_TABLE,
53 COMBIOS_MAX_COLOR_DEPTH_TABLE,
54 COMBIOS_CRTC_INFO_TABLE,
55 COMBIOS_PLL_INFO_TABLE,
56 COMBIOS_TV_INFO_TABLE,
57 COMBIOS_DFP_INFO_TABLE,
58 COMBIOS_HW_CONFIG_INFO_TABLE,
59 COMBIOS_MULTIMEDIA_INFO_TABLE,
60 COMBIOS_TV_STD_PATCH_TABLE,
61 COMBIOS_LCD_INFO_TABLE,
62 COMBIOS_MOBILE_INFO_TABLE,
63 COMBIOS_PLL_INIT_TABLE,
64 COMBIOS_MEM_CONFIG_TABLE,
65 COMBIOS_SAVE_MASK_TABLE,
66 COMBIOS_HARDCODED_EDID_TABLE,
67 COMBIOS_ASIC_INIT_2_TABLE,
68 COMBIOS_CONNECTOR_INFO_TABLE,
69 COMBIOS_DYN_CLK_1_TABLE,
70 COMBIOS_RESERVED_MEM_TABLE,
71 COMBIOS_EXT_TMDS_INFO_TABLE,
72 COMBIOS_MEM_CLK_INFO_TABLE,
73 COMBIOS_EXT_DAC_INFO_TABLE,
74 COMBIOS_MISC_INFO_TABLE,
75 COMBIOS_CRT_INFO_TABLE,
76 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
77 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
78 COMBIOS_FAN_SPEED_INFO_TABLE,
79 COMBIOS_OVERDRIVE_INFO_TABLE,
80 COMBIOS_OEM_INFO_TABLE,
81 COMBIOS_DYN_CLK_2_TABLE,
82 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
83 COMBIOS_I2C_INFO_TABLE,
84 /* relative offset tables */
85 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
86 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
87 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
88 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
89 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
90 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
91 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
92 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
93 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
94 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
95 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
98 enum radeon_combios_ddc {
108 enum radeon_combios_connector {
109 CONNECTOR_NONE_LEGACY,
110 CONNECTOR_PROPRIETARY_LEGACY,
111 CONNECTOR_CRT_LEGACY,
112 CONNECTOR_DVI_I_LEGACY,
113 CONNECTOR_DVI_D_LEGACY,
114 CONNECTOR_CTV_LEGACY,
115 CONNECTOR_STV_LEGACY,
116 CONNECTOR_UNSUPPORTED_LEGACY
119 static const int legacy_connector_convert[] = {
120 DRM_MODE_CONNECTOR_Unknown,
121 DRM_MODE_CONNECTOR_DVID,
122 DRM_MODE_CONNECTOR_VGA,
123 DRM_MODE_CONNECTOR_DVII,
124 DRM_MODE_CONNECTOR_DVID,
125 DRM_MODE_CONNECTOR_Composite,
126 DRM_MODE_CONNECTOR_SVIDEO,
127 DRM_MODE_CONNECTOR_Unknown,
130 static uint16_t combios_get_table_offset(struct drm_device *dev,
131 enum radeon_combios_table_offset table)
133 struct radeon_device *rdev = dev->dev_private;
135 uint16_t offset = 0, check_offset;
141 /* absolute offset tables */
142 case COMBIOS_ASIC_INIT_1_TABLE:
145 case COMBIOS_BIOS_SUPPORT_TABLE:
148 case COMBIOS_DAC_PROGRAMMING_TABLE:
151 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
154 case COMBIOS_CRTC_INFO_TABLE:
157 case COMBIOS_PLL_INFO_TABLE:
160 case COMBIOS_TV_INFO_TABLE:
163 case COMBIOS_DFP_INFO_TABLE:
166 case COMBIOS_HW_CONFIG_INFO_TABLE:
169 case COMBIOS_MULTIMEDIA_INFO_TABLE:
172 case COMBIOS_TV_STD_PATCH_TABLE:
175 case COMBIOS_LCD_INFO_TABLE:
178 case COMBIOS_MOBILE_INFO_TABLE:
181 case COMBIOS_PLL_INIT_TABLE:
184 case COMBIOS_MEM_CONFIG_TABLE:
187 case COMBIOS_SAVE_MASK_TABLE:
190 case COMBIOS_HARDCODED_EDID_TABLE:
193 case COMBIOS_ASIC_INIT_2_TABLE:
196 case COMBIOS_CONNECTOR_INFO_TABLE:
199 case COMBIOS_DYN_CLK_1_TABLE:
202 case COMBIOS_RESERVED_MEM_TABLE:
205 case COMBIOS_EXT_TMDS_INFO_TABLE:
208 case COMBIOS_MEM_CLK_INFO_TABLE:
211 case COMBIOS_EXT_DAC_INFO_TABLE:
214 case COMBIOS_MISC_INFO_TABLE:
217 case COMBIOS_CRT_INFO_TABLE:
220 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
223 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
226 case COMBIOS_FAN_SPEED_INFO_TABLE:
229 case COMBIOS_OVERDRIVE_INFO_TABLE:
232 case COMBIOS_OEM_INFO_TABLE:
235 case COMBIOS_DYN_CLK_2_TABLE:
238 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
241 case COMBIOS_I2C_INFO_TABLE:
244 /* relative offset tables */
245 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
247 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
249 rev = RBIOS8(check_offset);
251 check_offset = RBIOS16(check_offset + 0x3);
253 offset = check_offset;
257 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
259 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
261 rev = RBIOS8(check_offset);
263 check_offset = RBIOS16(check_offset + 0x5);
265 offset = check_offset;
269 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
271 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
273 rev = RBIOS8(check_offset);
275 check_offset = RBIOS16(check_offset + 0x7);
277 offset = check_offset;
281 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
283 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
285 rev = RBIOS8(check_offset);
287 check_offset = RBIOS16(check_offset + 0x9);
289 offset = check_offset;
293 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
295 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
297 while (RBIOS8(check_offset++));
300 offset = check_offset;
303 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
305 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
307 check_offset = RBIOS16(check_offset + 0x11);
309 offset = check_offset;
312 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
314 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
316 check_offset = RBIOS16(check_offset + 0x13);
318 offset = check_offset;
321 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
323 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
325 check_offset = RBIOS16(check_offset + 0x15);
327 offset = check_offset;
330 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
332 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
334 check_offset = RBIOS16(check_offset + 0x17);
336 offset = check_offset;
339 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
341 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
343 check_offset = RBIOS16(check_offset + 0x2);
345 offset = check_offset;
348 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
350 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
352 check_offset = RBIOS16(check_offset + 0x4);
354 offset = check_offset;
362 size = RBIOS8(rdev->bios_header_start + 0x6);
363 /* check absolute offset tables */
364 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
365 offset = RBIOS16(rdev->bios_header_start + check_offset);
370 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
375 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
379 raw = rdev->bios + edid_info;
380 size = EDID_LENGTH * (raw[0x7e] + 1);
381 edid = kmalloc(size, GFP_KERNEL);
385 memcpy((unsigned char *)edid, raw, size);
387 if (!drm_edid_is_valid(edid)) {
392 rdev->mode_info.bios_hardcoded_edid = edid;
393 rdev->mode_info.bios_hardcoded_edid_size = size;
397 /* this is used for atom LCDs as well */
399 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
403 if (rdev->mode_info.bios_hardcoded_edid) {
404 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
406 memcpy((unsigned char *)edid,
407 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
408 rdev->mode_info.bios_hardcoded_edid_size);
415 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
416 enum radeon_combios_ddc ddc,
420 struct radeon_i2c_bus_rec i2c;
424 * DDC_NONE_DETECTED = none
425 * DDC_DVI = RADEON_GPIO_DVI_DDC
426 * DDC_VGA = RADEON_GPIO_VGA_DDC
427 * DDC_LCD = RADEON_GPIOPAD_MASK
428 * DDC_GPIO = RADEON_MDGPIO_MASK
430 * DDC_MONID = RADEON_GPIO_MONID
431 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
433 * DDC_MONID = RADEON_GPIO_MONID
434 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
436 * DDC_MONID = RADEON_GPIO_DVI_DDC
437 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
439 * DDC_MONID = RADEON_GPIO_MONID
440 * DDC_CRT2 = RADEON_GPIO_MONID
442 * DDC_MONID = RADEON_GPIOPAD_MASK
443 * DDC_CRT2 = RADEON_GPIO_MONID
446 case DDC_NONE_DETECTED:
451 ddc_line = RADEON_GPIO_DVI_DDC;
454 ddc_line = RADEON_GPIO_VGA_DDC;
457 ddc_line = RADEON_GPIOPAD_MASK;
460 ddc_line = RADEON_MDGPIO_MASK;
463 if (rdev->family == CHIP_RS300 ||
464 rdev->family == CHIP_RS400 ||
465 rdev->family == CHIP_RS480)
466 ddc_line = RADEON_GPIOPAD_MASK;
467 else if (rdev->family == CHIP_R300 ||
468 rdev->family == CHIP_R350) {
469 ddc_line = RADEON_GPIO_DVI_DDC;
472 ddc_line = RADEON_GPIO_MONID;
475 if (rdev->family == CHIP_R200 ||
476 rdev->family == CHIP_R300 ||
477 rdev->family == CHIP_R350) {
478 ddc_line = RADEON_GPIO_DVI_DDC;
480 } else if (rdev->family == CHIP_RS300 ||
481 rdev->family == CHIP_RS400 ||
482 rdev->family == CHIP_RS480)
483 ddc_line = RADEON_GPIO_MONID;
484 else if (rdev->family >= CHIP_RV350) {
485 ddc_line = RADEON_GPIO_MONID;
488 ddc_line = RADEON_GPIO_CRT2_DDC;
492 if (ddc_line == RADEON_GPIOPAD_MASK) {
493 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
494 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
495 i2c.a_clk_reg = RADEON_GPIOPAD_A;
496 i2c.a_data_reg = RADEON_GPIOPAD_A;
497 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
498 i2c.en_data_reg = RADEON_GPIOPAD_EN;
499 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
500 i2c.y_data_reg = RADEON_GPIOPAD_Y;
501 } else if (ddc_line == RADEON_MDGPIO_MASK) {
502 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
503 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
504 i2c.a_clk_reg = RADEON_MDGPIO_A;
505 i2c.a_data_reg = RADEON_MDGPIO_A;
506 i2c.en_clk_reg = RADEON_MDGPIO_EN;
507 i2c.en_data_reg = RADEON_MDGPIO_EN;
508 i2c.y_clk_reg = RADEON_MDGPIO_Y;
509 i2c.y_data_reg = RADEON_MDGPIO_Y;
511 i2c.mask_clk_reg = ddc_line;
512 i2c.mask_data_reg = ddc_line;
513 i2c.a_clk_reg = ddc_line;
514 i2c.a_data_reg = ddc_line;
515 i2c.en_clk_reg = ddc_line;
516 i2c.en_data_reg = ddc_line;
517 i2c.y_clk_reg = ddc_line;
518 i2c.y_data_reg = ddc_line;
521 if (clk_mask && data_mask) {
522 /* system specific masks */
523 i2c.mask_clk_mask = clk_mask;
524 i2c.mask_data_mask = data_mask;
525 i2c.a_clk_mask = clk_mask;
526 i2c.a_data_mask = data_mask;
527 i2c.en_clk_mask = clk_mask;
528 i2c.en_data_mask = data_mask;
529 i2c.y_clk_mask = clk_mask;
530 i2c.y_data_mask = data_mask;
531 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
532 (ddc_line == RADEON_MDGPIO_MASK)) {
533 /* default gpiopad masks */
534 i2c.mask_clk_mask = (0x20 << 8);
535 i2c.mask_data_mask = 0x80;
536 i2c.a_clk_mask = (0x20 << 8);
537 i2c.a_data_mask = 0x80;
538 i2c.en_clk_mask = (0x20 << 8);
539 i2c.en_data_mask = 0x80;
540 i2c.y_clk_mask = (0x20 << 8);
541 i2c.y_data_mask = 0x80;
543 /* default masks for ddc pads */
544 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
545 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
546 i2c.a_clk_mask = RADEON_GPIO_A_1;
547 i2c.a_data_mask = RADEON_GPIO_A_0;
548 i2c.en_clk_mask = RADEON_GPIO_EN_1;
549 i2c.en_data_mask = RADEON_GPIO_EN_0;
550 i2c.y_clk_mask = RADEON_GPIO_Y_1;
551 i2c.y_data_mask = RADEON_GPIO_Y_0;
554 switch (rdev->family) {
562 case RADEON_GPIO_DVI_DDC:
563 i2c.hw_capable = true;
566 i2c.hw_capable = false;
572 case RADEON_GPIO_DVI_DDC:
573 case RADEON_GPIO_MONID:
574 i2c.hw_capable = true;
577 i2c.hw_capable = false;
584 case RADEON_GPIO_VGA_DDC:
585 case RADEON_GPIO_DVI_DDC:
586 case RADEON_GPIO_CRT2_DDC:
587 i2c.hw_capable = true;
590 i2c.hw_capable = false;
597 case RADEON_GPIO_VGA_DDC:
598 case RADEON_GPIO_DVI_DDC:
599 i2c.hw_capable = true;
602 i2c.hw_capable = false;
611 case RADEON_GPIO_VGA_DDC:
612 case RADEON_GPIO_DVI_DDC:
613 i2c.hw_capable = true;
615 case RADEON_GPIO_MONID:
616 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
617 * reliably on some pre-r4xx hardware; not sure why.
619 i2c.hw_capable = false;
622 i2c.hw_capable = false;
627 i2c.hw_capable = false;
633 i2c.hpd = RADEON_HPD_NONE;
643 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
645 struct drm_device *dev = rdev->ddev;
646 struct radeon_i2c_bus_rec i2c;
648 u8 id, blocks, clk, data;
653 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
655 blocks = RBIOS8(offset + 2);
656 for (i = 0; i < blocks; i++) {
657 id = RBIOS8(offset + 3 + (i * 5) + 0);
659 clk = RBIOS8(offset + 3 + (i * 5) + 3);
660 data = RBIOS8(offset + 3 + (i * 5) + 4);
662 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
663 (1 << clk), (1 << data));
671 void radeon_combios_i2c_init(struct radeon_device *rdev)
673 struct drm_device *dev = rdev->ddev;
674 struct radeon_i2c_bus_rec i2c;
678 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
680 * 0x60, 0x64, 0x68, mm
684 * 0x60, 0x64, 0x68, gpiopads, mm
688 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
689 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
691 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
692 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
696 i2c.hw_capable = true;
699 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
701 if (rdev->family == CHIP_R300 ||
702 rdev->family == CHIP_R350) {
703 /* only 2 sw i2c pads */
704 } else if (rdev->family == CHIP_RS300 ||
705 rdev->family == CHIP_RS400 ||
706 rdev->family == CHIP_RS480) {
708 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
709 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
712 i2c = radeon_combios_get_i2c_info_from_table(rdev);
714 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
715 } else if ((rdev->family == CHIP_R200) ||
716 (rdev->family >= CHIP_R300)) {
718 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
719 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
722 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
723 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
725 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
726 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
730 bool radeon_combios_get_clock_info(struct drm_device *dev)
732 struct radeon_device *rdev = dev->dev_private;
734 struct radeon_pll *p1pll = &rdev->clock.p1pll;
735 struct radeon_pll *p2pll = &rdev->clock.p2pll;
736 struct radeon_pll *spll = &rdev->clock.spll;
737 struct radeon_pll *mpll = &rdev->clock.mpll;
741 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
743 rev = RBIOS8(pll_info);
746 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
747 p1pll->reference_div = RBIOS16(pll_info + 0x10);
748 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
749 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
750 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
751 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
754 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
755 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
757 p1pll->pll_in_min = 40;
758 p1pll->pll_in_max = 500;
763 spll->reference_freq = RBIOS16(pll_info + 0x1a);
764 spll->reference_div = RBIOS16(pll_info + 0x1c);
765 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
766 spll->pll_out_max = RBIOS32(pll_info + 0x22);
769 spll->pll_in_min = RBIOS32(pll_info + 0x48);
770 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
773 spll->pll_in_min = 40;
774 spll->pll_in_max = 500;
778 mpll->reference_freq = RBIOS16(pll_info + 0x26);
779 mpll->reference_div = RBIOS16(pll_info + 0x28);
780 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
781 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
784 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
785 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
788 mpll->pll_in_min = 40;
789 mpll->pll_in_max = 500;
792 /* default sclk/mclk */
793 sclk = RBIOS16(pll_info + 0xa);
794 mclk = RBIOS16(pll_info + 0x8);
800 rdev->clock.default_sclk = sclk;
801 rdev->clock.default_mclk = mclk;
803 if (RBIOS32(pll_info + 0x16))
804 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
806 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
813 bool radeon_combios_sideport_present(struct radeon_device *rdev)
815 struct drm_device *dev = rdev->ddev;
818 /* sideport is AMD only */
819 if (rdev->family == CHIP_RS400)
822 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
825 if (RBIOS16(igp_info + 0x4))
831 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
832 0x00000808, /* r100 */
833 0x00000808, /* rv100 */
834 0x00000808, /* rs100 */
835 0x00000808, /* rv200 */
836 0x00000808, /* rs200 */
837 0x00000808, /* r200 */
838 0x00000808, /* rv250 */
839 0x00000000, /* rs300 */
840 0x00000808, /* rv280 */
841 0x00000808, /* r300 */
842 0x00000808, /* r350 */
843 0x00000808, /* rv350 */
844 0x00000808, /* rv380 */
845 0x00000808, /* r420 */
846 0x00000808, /* r423 */
847 0x00000808, /* rv410 */
848 0x00000000, /* rs400 */
849 0x00000000, /* rs480 */
852 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
853 struct radeon_encoder_primary_dac *p_dac)
855 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
859 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
863 struct drm_device *dev = encoder->base.dev;
864 struct radeon_device *rdev = dev->dev_private;
866 uint8_t rev, bg, dac;
867 struct radeon_encoder_primary_dac *p_dac = NULL;
870 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
876 /* check CRT table */
877 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
879 rev = RBIOS8(dac_info) & 0x3;
881 bg = RBIOS8(dac_info + 0x2) & 0xf;
882 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
883 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
885 bg = RBIOS8(dac_info + 0x2) & 0xf;
886 dac = RBIOS8(dac_info + 0x3) & 0xf;
887 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
889 /* if the values are zeros, use the table */
890 if ((dac == 0) || (bg == 0))
897 /* Radeon 7000 (RV100) */
898 if (((dev->pdev->device == 0x5159) &&
899 (dev->pdev->subsystem_vendor == 0x174B) &&
900 (dev->pdev->subsystem_device == 0x7c28)) ||
901 /* Radeon 9100 (R200) */
902 ((dev->pdev->device == 0x514D) &&
903 (dev->pdev->subsystem_vendor == 0x174B) &&
904 (dev->pdev->subsystem_device == 0x7149))) {
905 /* vbios value is bad, use the default */
909 if (!found) /* fallback to defaults */
910 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
916 radeon_combios_get_tv_info(struct radeon_device *rdev)
918 struct drm_device *dev = rdev->ddev;
920 enum radeon_tv_std tv_std = TV_STD_NTSC;
922 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
924 if (RBIOS8(tv_info + 6) == 'T') {
925 switch (RBIOS8(tv_info + 7) & 0xf) {
927 tv_std = TV_STD_NTSC;
928 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
932 DRM_DEBUG_KMS("Default TV standard: PAL\n");
935 tv_std = TV_STD_PAL_M;
936 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
939 tv_std = TV_STD_PAL_60;
940 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
943 tv_std = TV_STD_NTSC_J;
944 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
947 tv_std = TV_STD_SCART_PAL;
948 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
951 tv_std = TV_STD_NTSC;
953 ("Unknown TV standard; defaulting to NTSC\n");
957 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
959 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
962 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
965 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
968 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
978 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
979 0x00000000, /* r100 */
980 0x00280000, /* rv100 */
981 0x00000000, /* rs100 */
982 0x00880000, /* rv200 */
983 0x00000000, /* rs200 */
984 0x00000000, /* r200 */
985 0x00770000, /* rv250 */
986 0x00290000, /* rs300 */
987 0x00560000, /* rv280 */
988 0x00780000, /* r300 */
989 0x00770000, /* r350 */
990 0x00780000, /* rv350 */
991 0x00780000, /* rv380 */
992 0x01080000, /* r420 */
993 0x01080000, /* r423 */
994 0x01080000, /* rv410 */
995 0x00780000, /* rs400 */
996 0x00780000, /* rs480 */
999 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1000 struct radeon_encoder_tv_dac *tv_dac)
1002 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1003 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1004 tv_dac->ps2_tvdac_adj = 0x00880000;
1005 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1006 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1010 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1014 struct drm_device *dev = encoder->base.dev;
1015 struct radeon_device *rdev = dev->dev_private;
1017 uint8_t rev, bg, dac;
1018 struct radeon_encoder_tv_dac *tv_dac = NULL;
1021 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1025 /* first check TV table */
1026 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1028 rev = RBIOS8(dac_info + 0x3);
1030 bg = RBIOS8(dac_info + 0xc) & 0xf;
1031 dac = RBIOS8(dac_info + 0xd) & 0xf;
1032 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1034 bg = RBIOS8(dac_info + 0xe) & 0xf;
1035 dac = RBIOS8(dac_info + 0xf) & 0xf;
1036 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1038 bg = RBIOS8(dac_info + 0x10) & 0xf;
1039 dac = RBIOS8(dac_info + 0x11) & 0xf;
1040 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1041 /* if the values are all zeros, use the table */
1042 if (tv_dac->ps2_tvdac_adj)
1044 } else if (rev > 1) {
1045 bg = RBIOS8(dac_info + 0xc) & 0xf;
1046 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1047 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1049 bg = RBIOS8(dac_info + 0xd) & 0xf;
1050 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1051 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1053 bg = RBIOS8(dac_info + 0xe) & 0xf;
1054 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1055 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1056 /* if the values are all zeros, use the table */
1057 if (tv_dac->ps2_tvdac_adj)
1060 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1063 /* then check CRT table */
1065 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1067 rev = RBIOS8(dac_info) & 0x3;
1069 bg = RBIOS8(dac_info + 0x3) & 0xf;
1070 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1071 tv_dac->ps2_tvdac_adj =
1072 (bg << 16) | (dac << 20);
1073 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1074 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1075 /* if the values are all zeros, use the table */
1076 if (tv_dac->ps2_tvdac_adj)
1079 bg = RBIOS8(dac_info + 0x4) & 0xf;
1080 dac = RBIOS8(dac_info + 0x5) & 0xf;
1081 tv_dac->ps2_tvdac_adj =
1082 (bg << 16) | (dac << 20);
1083 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1084 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1085 /* if the values are all zeros, use the table */
1086 if (tv_dac->ps2_tvdac_adj)
1090 DRM_INFO("No TV DAC info found in BIOS\n");
1094 if (!found) /* fallback to defaults */
1095 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1100 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1104 struct radeon_encoder_lvds *lvds = NULL;
1105 uint32_t fp_vert_stretch, fp_horz_stretch;
1106 uint32_t ppll_div_sel, ppll_val;
1107 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1109 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1114 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1115 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1117 /* These should be fail-safe defaults, fingers crossed */
1118 lvds->panel_pwr_delay = 200;
1119 lvds->panel_vcc_delay = 2000;
1121 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1122 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1123 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1125 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1126 lvds->native_mode.vdisplay =
1127 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1128 RADEON_VERT_PANEL_SHIFT) + 1;
1130 lvds->native_mode.vdisplay =
1131 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1133 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1134 lvds->native_mode.hdisplay =
1135 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1136 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1138 lvds->native_mode.hdisplay =
1139 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1141 if ((lvds->native_mode.hdisplay < 640) ||
1142 (lvds->native_mode.vdisplay < 480)) {
1143 lvds->native_mode.hdisplay = 640;
1144 lvds->native_mode.vdisplay = 480;
1147 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1148 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1149 if ((ppll_val & 0x000707ff) == 0x1bb)
1150 lvds->use_bios_dividers = false;
1152 lvds->panel_ref_divider =
1153 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1154 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1155 lvds->panel_fb_divider = ppll_val & 0x7ff;
1157 if ((lvds->panel_ref_divider != 0) &&
1158 (lvds->panel_fb_divider > 3))
1159 lvds->use_bios_dividers = true;
1161 lvds->panel_vcc_delay = 200;
1163 DRM_INFO("Panel info derived from registers\n");
1164 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1165 lvds->native_mode.vdisplay);
1170 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1173 struct drm_device *dev = encoder->base.dev;
1174 struct radeon_device *rdev = dev->dev_private;
1176 uint32_t panel_setup;
1179 struct radeon_encoder_lvds *lvds = NULL;
1181 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1184 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1189 for (i = 0; i < 24; i++)
1190 stmp[i] = RBIOS8(lcd_info + i + 1);
1193 DRM_INFO("Panel ID String: %s\n", stmp);
1195 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1196 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1198 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1199 lvds->native_mode.vdisplay);
1201 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1202 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1204 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1205 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1206 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1208 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1209 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1210 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1211 if ((lvds->panel_ref_divider != 0) &&
1212 (lvds->panel_fb_divider > 3))
1213 lvds->use_bios_dividers = true;
1215 panel_setup = RBIOS32(lcd_info + 0x39);
1216 lvds->lvds_gen_cntl = 0xff00;
1217 if (panel_setup & 0x1)
1218 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1220 if ((panel_setup >> 4) & 0x1)
1221 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1223 switch ((panel_setup >> 8) & 0x7) {
1225 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1228 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1237 if ((panel_setup >> 16) & 0x1)
1238 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1240 if ((panel_setup >> 17) & 0x1)
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1243 if ((panel_setup >> 18) & 0x1)
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1246 if ((panel_setup >> 23) & 0x1)
1247 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1249 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1251 for (i = 0; i < 32; i++) {
1252 tmp = RBIOS16(lcd_info + 64 + i * 2);
1256 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1257 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1258 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1260 if (hss > lvds->native_mode.hdisplay)
1263 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1264 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1265 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1267 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1268 (RBIOS8(tmp + 23) * 8);
1270 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1271 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1272 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1273 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1274 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1275 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1277 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1278 lvds->native_mode.flags = 0;
1279 /* set crtc values */
1280 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1285 DRM_INFO("No panel info found in BIOS\n");
1286 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1290 encoder->native_mode = lvds->native_mode;
1294 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1295 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1296 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1297 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1298 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1299 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1300 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1301 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1302 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1303 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1306 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1307 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1308 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1309 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1310 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1311 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1312 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1315 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1316 struct radeon_encoder_int_tmds *tmds)
1318 struct drm_device *dev = encoder->base.dev;
1319 struct radeon_device *rdev = dev->dev_private;
1322 for (i = 0; i < 4; i++) {
1323 tmds->tmds_pll[i].value =
1324 default_tmds_pll[rdev->family][i].value;
1325 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1331 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1332 struct radeon_encoder_int_tmds *tmds)
1334 struct drm_device *dev = encoder->base.dev;
1335 struct radeon_device *rdev = dev->dev_private;
1340 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1343 ver = RBIOS8(tmds_info);
1344 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1346 n = RBIOS8(tmds_info + 5) + 1;
1349 for (i = 0; i < n; i++) {
1350 tmds->tmds_pll[i].value =
1351 RBIOS32(tmds_info + i * 10 + 0x08);
1352 tmds->tmds_pll[i].freq =
1353 RBIOS16(tmds_info + i * 10 + 0x10);
1354 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1355 tmds->tmds_pll[i].freq,
1356 tmds->tmds_pll[i].value);
1358 } else if (ver == 4) {
1360 n = RBIOS8(tmds_info + 5) + 1;
1363 for (i = 0; i < n; i++) {
1364 tmds->tmds_pll[i].value =
1365 RBIOS32(tmds_info + stride + 0x08);
1366 tmds->tmds_pll[i].freq =
1367 RBIOS16(tmds_info + stride + 0x10);
1372 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1373 tmds->tmds_pll[i].freq,
1374 tmds->tmds_pll[i].value);
1378 DRM_INFO("No TMDS info found in BIOS\n");
1384 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1385 struct radeon_encoder_ext_tmds *tmds)
1387 struct drm_device *dev = encoder->base.dev;
1388 struct radeon_device *rdev = dev->dev_private;
1389 struct radeon_i2c_bus_rec i2c_bus;
1391 /* default for macs */
1392 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1393 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1395 /* XXX some macs have duallink chips */
1396 switch (rdev->mode_info.connector_table) {
1397 case CT_POWERBOOK_EXTERNAL:
1398 case CT_MINI_EXTERNAL:
1400 tmds->dvo_chip = DVO_SIL164;
1401 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1408 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1409 struct radeon_encoder_ext_tmds *tmds)
1411 struct drm_device *dev = encoder->base.dev;
1412 struct radeon_device *rdev = dev->dev_private;
1415 enum radeon_combios_ddc gpio;
1416 struct radeon_i2c_bus_rec i2c_bus;
1418 tmds->i2c_bus = NULL;
1419 if (rdev->flags & RADEON_IS_IGP) {
1420 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1421 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1422 tmds->dvo_chip = DVO_SIL164;
1423 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1425 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1427 ver = RBIOS8(offset);
1428 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1429 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1430 tmds->slave_addr >>= 1; /* 7 bit addressing */
1431 gpio = RBIOS8(offset + 4 + 3);
1432 if (gpio == DDC_LCD) {
1434 i2c_bus.valid = true;
1435 i2c_bus.hw_capable = true;
1436 i2c_bus.mm_i2c = true;
1437 i2c_bus.i2c_id = 0xa0;
1439 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1440 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1444 if (!tmds->i2c_bus) {
1445 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1452 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1454 struct radeon_device *rdev = dev->dev_private;
1455 struct radeon_i2c_bus_rec ddc_i2c;
1456 struct radeon_hpd hpd;
1458 rdev->mode_info.connector_table = radeon_connector_table;
1459 if (rdev->mode_info.connector_table == CT_NONE) {
1460 #ifdef CONFIG_PPC_PMAC
1461 if (of_machine_is_compatible("PowerBook3,3")) {
1462 /* powerbook with VGA */
1463 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1464 } else if (of_machine_is_compatible("PowerBook3,4") ||
1465 of_machine_is_compatible("PowerBook3,5")) {
1466 /* powerbook with internal tmds */
1467 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1468 } else if (of_machine_is_compatible("PowerBook5,1") ||
1469 of_machine_is_compatible("PowerBook5,2") ||
1470 of_machine_is_compatible("PowerBook5,3") ||
1471 of_machine_is_compatible("PowerBook5,4") ||
1472 of_machine_is_compatible("PowerBook5,5")) {
1473 /* powerbook with external single link tmds (sil164) */
1474 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1475 } else if (of_machine_is_compatible("PowerBook5,6")) {
1476 /* powerbook with external dual or single link tmds */
1477 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1478 } else if (of_machine_is_compatible("PowerBook5,7") ||
1479 of_machine_is_compatible("PowerBook5,8") ||
1480 of_machine_is_compatible("PowerBook5,9")) {
1481 /* PowerBook6,2 ? */
1482 /* powerbook with external dual link tmds (sil1178?) */
1483 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1484 } else if (of_machine_is_compatible("PowerBook4,1") ||
1485 of_machine_is_compatible("PowerBook4,2") ||
1486 of_machine_is_compatible("PowerBook4,3") ||
1487 of_machine_is_compatible("PowerBook6,3") ||
1488 of_machine_is_compatible("PowerBook6,5") ||
1489 of_machine_is_compatible("PowerBook6,7")) {
1491 rdev->mode_info.connector_table = CT_IBOOK;
1492 } else if (of_machine_is_compatible("PowerMac3,5")) {
1493 /* PowerMac G4 Silver radeon 7500 */
1494 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1495 } else if (of_machine_is_compatible("PowerMac4,4")) {
1497 rdev->mode_info.connector_table = CT_EMAC;
1498 } else if (of_machine_is_compatible("PowerMac10,1")) {
1499 /* mini with internal tmds */
1500 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1501 } else if (of_machine_is_compatible("PowerMac10,2")) {
1502 /* mini with external tmds */
1503 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1504 } else if (of_machine_is_compatible("PowerMac12,1")) {
1506 /* imac g5 isight */
1507 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1508 } else if ((rdev->pdev->device == 0x4a48) &&
1509 (rdev->pdev->subsystem_vendor == 0x1002) &&
1510 (rdev->pdev->subsystem_device == 0x4a48)) {
1512 rdev->mode_info.connector_table = CT_MAC_X800;
1513 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1514 of_machine_is_compatible("PowerMac7,3")) &&
1515 (rdev->pdev->device == 0x4150) &&
1516 (rdev->pdev->subsystem_vendor == 0x1002) &&
1517 (rdev->pdev->subsystem_device == 0x4150)) {
1518 /* Mac G5 tower 9600 */
1519 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1520 } else if ((rdev->pdev->device == 0x4c66) &&
1521 (rdev->pdev->subsystem_vendor == 0x1002) &&
1522 (rdev->pdev->subsystem_device == 0x4c66)) {
1523 /* SAM440ep RV250 embedded board */
1524 rdev->mode_info.connector_table = CT_SAM440EP;
1526 #endif /* CONFIG_PPC_PMAC */
1528 if (ASIC_IS_RN50(rdev))
1529 rdev->mode_info.connector_table = CT_RN50_POWER;
1532 rdev->mode_info.connector_table = CT_GENERIC;
1535 switch (rdev->mode_info.connector_table) {
1537 DRM_INFO("Connector Table: %d (generic)\n",
1538 rdev->mode_info.connector_table);
1539 /* these are the most common settings */
1540 if (rdev->flags & RADEON_SINGLE_CRTC) {
1541 /* VGA - primary dac */
1542 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1543 hpd.hpd = RADEON_HPD_NONE;
1544 radeon_add_legacy_encoder(dev,
1545 radeon_get_encoder_enum(dev,
1546 ATOM_DEVICE_CRT1_SUPPORT,
1548 ATOM_DEVICE_CRT1_SUPPORT);
1549 radeon_add_legacy_connector(dev, 0,
1550 ATOM_DEVICE_CRT1_SUPPORT,
1551 DRM_MODE_CONNECTOR_VGA,
1553 CONNECTOR_OBJECT_ID_VGA,
1555 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1557 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1558 hpd.hpd = RADEON_HPD_NONE;
1559 radeon_add_legacy_encoder(dev,
1560 radeon_get_encoder_enum(dev,
1561 ATOM_DEVICE_LCD1_SUPPORT,
1563 ATOM_DEVICE_LCD1_SUPPORT);
1564 radeon_add_legacy_connector(dev, 0,
1565 ATOM_DEVICE_LCD1_SUPPORT,
1566 DRM_MODE_CONNECTOR_LVDS,
1568 CONNECTOR_OBJECT_ID_LVDS,
1571 /* VGA - primary dac */
1572 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1573 hpd.hpd = RADEON_HPD_NONE;
1574 radeon_add_legacy_encoder(dev,
1575 radeon_get_encoder_enum(dev,
1576 ATOM_DEVICE_CRT1_SUPPORT,
1578 ATOM_DEVICE_CRT1_SUPPORT);
1579 radeon_add_legacy_connector(dev, 1,
1580 ATOM_DEVICE_CRT1_SUPPORT,
1581 DRM_MODE_CONNECTOR_VGA,
1583 CONNECTOR_OBJECT_ID_VGA,
1586 /* DVI-I - tv dac, int tmds */
1587 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1588 hpd.hpd = RADEON_HPD_1;
1589 radeon_add_legacy_encoder(dev,
1590 radeon_get_encoder_enum(dev,
1591 ATOM_DEVICE_DFP1_SUPPORT,
1593 ATOM_DEVICE_DFP1_SUPPORT);
1594 radeon_add_legacy_encoder(dev,
1595 radeon_get_encoder_enum(dev,
1596 ATOM_DEVICE_CRT2_SUPPORT,
1598 ATOM_DEVICE_CRT2_SUPPORT);
1599 radeon_add_legacy_connector(dev, 0,
1600 ATOM_DEVICE_DFP1_SUPPORT |
1601 ATOM_DEVICE_CRT2_SUPPORT,
1602 DRM_MODE_CONNECTOR_DVII,
1604 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1607 /* VGA - primary dac */
1608 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1609 hpd.hpd = RADEON_HPD_NONE;
1610 radeon_add_legacy_encoder(dev,
1611 radeon_get_encoder_enum(dev,
1612 ATOM_DEVICE_CRT1_SUPPORT,
1614 ATOM_DEVICE_CRT1_SUPPORT);
1615 radeon_add_legacy_connector(dev, 1,
1616 ATOM_DEVICE_CRT1_SUPPORT,
1617 DRM_MODE_CONNECTOR_VGA,
1619 CONNECTOR_OBJECT_ID_VGA,
1623 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1625 ddc_i2c.valid = false;
1626 hpd.hpd = RADEON_HPD_NONE;
1627 radeon_add_legacy_encoder(dev,
1628 radeon_get_encoder_enum(dev,
1629 ATOM_DEVICE_TV1_SUPPORT,
1631 ATOM_DEVICE_TV1_SUPPORT);
1632 radeon_add_legacy_connector(dev, 2,
1633 ATOM_DEVICE_TV1_SUPPORT,
1634 DRM_MODE_CONNECTOR_SVIDEO,
1636 CONNECTOR_OBJECT_ID_SVIDEO,
1641 DRM_INFO("Connector Table: %d (ibook)\n",
1642 rdev->mode_info.connector_table);
1644 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1645 hpd.hpd = RADEON_HPD_NONE;
1646 radeon_add_legacy_encoder(dev,
1647 radeon_get_encoder_enum(dev,
1648 ATOM_DEVICE_LCD1_SUPPORT,
1650 ATOM_DEVICE_LCD1_SUPPORT);
1651 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1652 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1653 CONNECTOR_OBJECT_ID_LVDS,
1656 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1657 hpd.hpd = RADEON_HPD_NONE;
1658 radeon_add_legacy_encoder(dev,
1659 radeon_get_encoder_enum(dev,
1660 ATOM_DEVICE_CRT2_SUPPORT,
1662 ATOM_DEVICE_CRT2_SUPPORT);
1663 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1664 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1665 CONNECTOR_OBJECT_ID_VGA,
1668 ddc_i2c.valid = false;
1669 hpd.hpd = RADEON_HPD_NONE;
1670 radeon_add_legacy_encoder(dev,
1671 radeon_get_encoder_enum(dev,
1672 ATOM_DEVICE_TV1_SUPPORT,
1674 ATOM_DEVICE_TV1_SUPPORT);
1675 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1676 DRM_MODE_CONNECTOR_SVIDEO,
1678 CONNECTOR_OBJECT_ID_SVIDEO,
1681 case CT_POWERBOOK_EXTERNAL:
1682 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1683 rdev->mode_info.connector_table);
1685 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1686 hpd.hpd = RADEON_HPD_NONE;
1687 radeon_add_legacy_encoder(dev,
1688 radeon_get_encoder_enum(dev,
1689 ATOM_DEVICE_LCD1_SUPPORT,
1691 ATOM_DEVICE_LCD1_SUPPORT);
1692 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1693 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1694 CONNECTOR_OBJECT_ID_LVDS,
1696 /* DVI-I - primary dac, ext tmds */
1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1698 hpd.hpd = RADEON_HPD_2; /* ??? */
1699 radeon_add_legacy_encoder(dev,
1700 radeon_get_encoder_enum(dev,
1701 ATOM_DEVICE_DFP2_SUPPORT,
1703 ATOM_DEVICE_DFP2_SUPPORT);
1704 radeon_add_legacy_encoder(dev,
1705 radeon_get_encoder_enum(dev,
1706 ATOM_DEVICE_CRT1_SUPPORT,
1708 ATOM_DEVICE_CRT1_SUPPORT);
1709 /* XXX some are SL */
1710 radeon_add_legacy_connector(dev, 1,
1711 ATOM_DEVICE_DFP2_SUPPORT |
1712 ATOM_DEVICE_CRT1_SUPPORT,
1713 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1714 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1717 ddc_i2c.valid = false;
1718 hpd.hpd = RADEON_HPD_NONE;
1719 radeon_add_legacy_encoder(dev,
1720 radeon_get_encoder_enum(dev,
1721 ATOM_DEVICE_TV1_SUPPORT,
1723 ATOM_DEVICE_TV1_SUPPORT);
1724 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1725 DRM_MODE_CONNECTOR_SVIDEO,
1727 CONNECTOR_OBJECT_ID_SVIDEO,
1730 case CT_POWERBOOK_INTERNAL:
1731 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1732 rdev->mode_info.connector_table);
1734 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1735 hpd.hpd = RADEON_HPD_NONE;
1736 radeon_add_legacy_encoder(dev,
1737 radeon_get_encoder_enum(dev,
1738 ATOM_DEVICE_LCD1_SUPPORT,
1740 ATOM_DEVICE_LCD1_SUPPORT);
1741 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1742 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1743 CONNECTOR_OBJECT_ID_LVDS,
1745 /* DVI-I - primary dac, int tmds */
1746 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1747 hpd.hpd = RADEON_HPD_1; /* ??? */
1748 radeon_add_legacy_encoder(dev,
1749 radeon_get_encoder_enum(dev,
1750 ATOM_DEVICE_DFP1_SUPPORT,
1752 ATOM_DEVICE_DFP1_SUPPORT);
1753 radeon_add_legacy_encoder(dev,
1754 radeon_get_encoder_enum(dev,
1755 ATOM_DEVICE_CRT1_SUPPORT,
1757 ATOM_DEVICE_CRT1_SUPPORT);
1758 radeon_add_legacy_connector(dev, 1,
1759 ATOM_DEVICE_DFP1_SUPPORT |
1760 ATOM_DEVICE_CRT1_SUPPORT,
1761 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1762 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1765 ddc_i2c.valid = false;
1766 hpd.hpd = RADEON_HPD_NONE;
1767 radeon_add_legacy_encoder(dev,
1768 radeon_get_encoder_enum(dev,
1769 ATOM_DEVICE_TV1_SUPPORT,
1771 ATOM_DEVICE_TV1_SUPPORT);
1772 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1773 DRM_MODE_CONNECTOR_SVIDEO,
1775 CONNECTOR_OBJECT_ID_SVIDEO,
1778 case CT_POWERBOOK_VGA:
1779 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1780 rdev->mode_info.connector_table);
1782 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1783 hpd.hpd = RADEON_HPD_NONE;
1784 radeon_add_legacy_encoder(dev,
1785 radeon_get_encoder_enum(dev,
1786 ATOM_DEVICE_LCD1_SUPPORT,
1788 ATOM_DEVICE_LCD1_SUPPORT);
1789 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1790 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1791 CONNECTOR_OBJECT_ID_LVDS,
1793 /* VGA - primary dac */
1794 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1795 hpd.hpd = RADEON_HPD_NONE;
1796 radeon_add_legacy_encoder(dev,
1797 radeon_get_encoder_enum(dev,
1798 ATOM_DEVICE_CRT1_SUPPORT,
1800 ATOM_DEVICE_CRT1_SUPPORT);
1801 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1802 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1803 CONNECTOR_OBJECT_ID_VGA,
1806 ddc_i2c.valid = false;
1807 hpd.hpd = RADEON_HPD_NONE;
1808 radeon_add_legacy_encoder(dev,
1809 radeon_get_encoder_enum(dev,
1810 ATOM_DEVICE_TV1_SUPPORT,
1812 ATOM_DEVICE_TV1_SUPPORT);
1813 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1814 DRM_MODE_CONNECTOR_SVIDEO,
1816 CONNECTOR_OBJECT_ID_SVIDEO,
1819 case CT_MINI_EXTERNAL:
1820 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1821 rdev->mode_info.connector_table);
1822 /* DVI-I - tv dac, ext tmds */
1823 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1824 hpd.hpd = RADEON_HPD_2; /* ??? */
1825 radeon_add_legacy_encoder(dev,
1826 radeon_get_encoder_enum(dev,
1827 ATOM_DEVICE_DFP2_SUPPORT,
1829 ATOM_DEVICE_DFP2_SUPPORT);
1830 radeon_add_legacy_encoder(dev,
1831 radeon_get_encoder_enum(dev,
1832 ATOM_DEVICE_CRT2_SUPPORT,
1834 ATOM_DEVICE_CRT2_SUPPORT);
1835 /* XXX are any DL? */
1836 radeon_add_legacy_connector(dev, 0,
1837 ATOM_DEVICE_DFP2_SUPPORT |
1838 ATOM_DEVICE_CRT2_SUPPORT,
1839 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1840 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1843 ddc_i2c.valid = false;
1844 hpd.hpd = RADEON_HPD_NONE;
1845 radeon_add_legacy_encoder(dev,
1846 radeon_get_encoder_enum(dev,
1847 ATOM_DEVICE_TV1_SUPPORT,
1849 ATOM_DEVICE_TV1_SUPPORT);
1850 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1851 DRM_MODE_CONNECTOR_SVIDEO,
1853 CONNECTOR_OBJECT_ID_SVIDEO,
1856 case CT_MINI_INTERNAL:
1857 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1858 rdev->mode_info.connector_table);
1859 /* DVI-I - tv dac, int tmds */
1860 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1861 hpd.hpd = RADEON_HPD_1; /* ??? */
1862 radeon_add_legacy_encoder(dev,
1863 radeon_get_encoder_enum(dev,
1864 ATOM_DEVICE_DFP1_SUPPORT,
1866 ATOM_DEVICE_DFP1_SUPPORT);
1867 radeon_add_legacy_encoder(dev,
1868 radeon_get_encoder_enum(dev,
1869 ATOM_DEVICE_CRT2_SUPPORT,
1871 ATOM_DEVICE_CRT2_SUPPORT);
1872 radeon_add_legacy_connector(dev, 0,
1873 ATOM_DEVICE_DFP1_SUPPORT |
1874 ATOM_DEVICE_CRT2_SUPPORT,
1875 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1876 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1879 ddc_i2c.valid = false;
1880 hpd.hpd = RADEON_HPD_NONE;
1881 radeon_add_legacy_encoder(dev,
1882 radeon_get_encoder_enum(dev,
1883 ATOM_DEVICE_TV1_SUPPORT,
1885 ATOM_DEVICE_TV1_SUPPORT);
1886 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1887 DRM_MODE_CONNECTOR_SVIDEO,
1889 CONNECTOR_OBJECT_ID_SVIDEO,
1892 case CT_IMAC_G5_ISIGHT:
1893 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1894 rdev->mode_info.connector_table);
1895 /* DVI-D - int tmds */
1896 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1897 hpd.hpd = RADEON_HPD_1; /* ??? */
1898 radeon_add_legacy_encoder(dev,
1899 radeon_get_encoder_enum(dev,
1900 ATOM_DEVICE_DFP1_SUPPORT,
1902 ATOM_DEVICE_DFP1_SUPPORT);
1903 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1904 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1905 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1908 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1909 hpd.hpd = RADEON_HPD_NONE;
1910 radeon_add_legacy_encoder(dev,
1911 radeon_get_encoder_enum(dev,
1912 ATOM_DEVICE_CRT2_SUPPORT,
1914 ATOM_DEVICE_CRT2_SUPPORT);
1915 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1916 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1917 CONNECTOR_OBJECT_ID_VGA,
1920 ddc_i2c.valid = false;
1921 hpd.hpd = RADEON_HPD_NONE;
1922 radeon_add_legacy_encoder(dev,
1923 radeon_get_encoder_enum(dev,
1924 ATOM_DEVICE_TV1_SUPPORT,
1926 ATOM_DEVICE_TV1_SUPPORT);
1927 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1928 DRM_MODE_CONNECTOR_SVIDEO,
1930 CONNECTOR_OBJECT_ID_SVIDEO,
1934 DRM_INFO("Connector Table: %d (emac)\n",
1935 rdev->mode_info.connector_table);
1936 /* VGA - primary dac */
1937 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1938 hpd.hpd = RADEON_HPD_NONE;
1939 radeon_add_legacy_encoder(dev,
1940 radeon_get_encoder_enum(dev,
1941 ATOM_DEVICE_CRT1_SUPPORT,
1943 ATOM_DEVICE_CRT1_SUPPORT);
1944 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1945 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1946 CONNECTOR_OBJECT_ID_VGA,
1949 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1950 hpd.hpd = RADEON_HPD_NONE;
1951 radeon_add_legacy_encoder(dev,
1952 radeon_get_encoder_enum(dev,
1953 ATOM_DEVICE_CRT2_SUPPORT,
1955 ATOM_DEVICE_CRT2_SUPPORT);
1956 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1957 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1958 CONNECTOR_OBJECT_ID_VGA,
1961 ddc_i2c.valid = false;
1962 hpd.hpd = RADEON_HPD_NONE;
1963 radeon_add_legacy_encoder(dev,
1964 radeon_get_encoder_enum(dev,
1965 ATOM_DEVICE_TV1_SUPPORT,
1967 ATOM_DEVICE_TV1_SUPPORT);
1968 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1969 DRM_MODE_CONNECTOR_SVIDEO,
1971 CONNECTOR_OBJECT_ID_SVIDEO,
1975 DRM_INFO("Connector Table: %d (rn50-power)\n",
1976 rdev->mode_info.connector_table);
1977 /* VGA - primary dac */
1978 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1979 hpd.hpd = RADEON_HPD_NONE;
1980 radeon_add_legacy_encoder(dev,
1981 radeon_get_encoder_enum(dev,
1982 ATOM_DEVICE_CRT1_SUPPORT,
1984 ATOM_DEVICE_CRT1_SUPPORT);
1985 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1986 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1987 CONNECTOR_OBJECT_ID_VGA,
1989 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1990 hpd.hpd = RADEON_HPD_NONE;
1991 radeon_add_legacy_encoder(dev,
1992 radeon_get_encoder_enum(dev,
1993 ATOM_DEVICE_CRT2_SUPPORT,
1995 ATOM_DEVICE_CRT2_SUPPORT);
1996 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1997 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1998 CONNECTOR_OBJECT_ID_VGA,
2002 DRM_INFO("Connector Table: %d (mac x800)\n",
2003 rdev->mode_info.connector_table);
2004 /* DVI - primary dac, internal tmds */
2005 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2006 hpd.hpd = RADEON_HPD_1; /* ??? */
2007 radeon_add_legacy_encoder(dev,
2008 radeon_get_encoder_enum(dev,
2009 ATOM_DEVICE_DFP1_SUPPORT,
2011 ATOM_DEVICE_DFP1_SUPPORT);
2012 radeon_add_legacy_encoder(dev,
2013 radeon_get_encoder_enum(dev,
2014 ATOM_DEVICE_CRT1_SUPPORT,
2016 ATOM_DEVICE_CRT1_SUPPORT);
2017 radeon_add_legacy_connector(dev, 0,
2018 ATOM_DEVICE_DFP1_SUPPORT |
2019 ATOM_DEVICE_CRT1_SUPPORT,
2020 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2021 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2023 /* DVI - tv dac, dvo */
2024 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2025 hpd.hpd = RADEON_HPD_2; /* ??? */
2026 radeon_add_legacy_encoder(dev,
2027 radeon_get_encoder_enum(dev,
2028 ATOM_DEVICE_DFP2_SUPPORT,
2030 ATOM_DEVICE_DFP2_SUPPORT);
2031 radeon_add_legacy_encoder(dev,
2032 radeon_get_encoder_enum(dev,
2033 ATOM_DEVICE_CRT2_SUPPORT,
2035 ATOM_DEVICE_CRT2_SUPPORT);
2036 radeon_add_legacy_connector(dev, 1,
2037 ATOM_DEVICE_DFP2_SUPPORT |
2038 ATOM_DEVICE_CRT2_SUPPORT,
2039 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2040 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2043 case CT_MAC_G5_9600:
2044 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2045 rdev->mode_info.connector_table);
2046 /* DVI - tv dac, dvo */
2047 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2048 hpd.hpd = RADEON_HPD_1; /* ??? */
2049 radeon_add_legacy_encoder(dev,
2050 radeon_get_encoder_enum(dev,
2051 ATOM_DEVICE_DFP2_SUPPORT,
2053 ATOM_DEVICE_DFP2_SUPPORT);
2054 radeon_add_legacy_encoder(dev,
2055 radeon_get_encoder_enum(dev,
2056 ATOM_DEVICE_CRT2_SUPPORT,
2058 ATOM_DEVICE_CRT2_SUPPORT);
2059 radeon_add_legacy_connector(dev, 0,
2060 ATOM_DEVICE_DFP2_SUPPORT |
2061 ATOM_DEVICE_CRT2_SUPPORT,
2062 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2063 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2065 /* ADC - primary dac, internal tmds */
2066 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2067 hpd.hpd = RADEON_HPD_2; /* ??? */
2068 radeon_add_legacy_encoder(dev,
2069 radeon_get_encoder_enum(dev,
2070 ATOM_DEVICE_DFP1_SUPPORT,
2072 ATOM_DEVICE_DFP1_SUPPORT);
2073 radeon_add_legacy_encoder(dev,
2074 radeon_get_encoder_enum(dev,
2075 ATOM_DEVICE_CRT1_SUPPORT,
2077 ATOM_DEVICE_CRT1_SUPPORT);
2078 radeon_add_legacy_connector(dev, 1,
2079 ATOM_DEVICE_DFP1_SUPPORT |
2080 ATOM_DEVICE_CRT1_SUPPORT,
2081 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2082 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2085 ddc_i2c.valid = false;
2086 hpd.hpd = RADEON_HPD_NONE;
2087 radeon_add_legacy_encoder(dev,
2088 radeon_get_encoder_enum(dev,
2089 ATOM_DEVICE_TV1_SUPPORT,
2091 ATOM_DEVICE_TV1_SUPPORT);
2092 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2093 DRM_MODE_CONNECTOR_SVIDEO,
2095 CONNECTOR_OBJECT_ID_SVIDEO,
2099 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2100 rdev->mode_info.connector_table);
2102 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2103 hpd.hpd = RADEON_HPD_NONE;
2104 radeon_add_legacy_encoder(dev,
2105 radeon_get_encoder_enum(dev,
2106 ATOM_DEVICE_LCD1_SUPPORT,
2108 ATOM_DEVICE_LCD1_SUPPORT);
2109 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2110 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2111 CONNECTOR_OBJECT_ID_LVDS,
2113 /* DVI-I - secondary dac, int tmds */
2114 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2115 hpd.hpd = RADEON_HPD_1; /* ??? */
2116 radeon_add_legacy_encoder(dev,
2117 radeon_get_encoder_enum(dev,
2118 ATOM_DEVICE_DFP1_SUPPORT,
2120 ATOM_DEVICE_DFP1_SUPPORT);
2121 radeon_add_legacy_encoder(dev,
2122 radeon_get_encoder_enum(dev,
2123 ATOM_DEVICE_CRT2_SUPPORT,
2125 ATOM_DEVICE_CRT2_SUPPORT);
2126 radeon_add_legacy_connector(dev, 1,
2127 ATOM_DEVICE_DFP1_SUPPORT |
2128 ATOM_DEVICE_CRT2_SUPPORT,
2129 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2130 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2132 /* VGA - primary dac */
2133 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2134 hpd.hpd = RADEON_HPD_NONE;
2135 radeon_add_legacy_encoder(dev,
2136 radeon_get_encoder_enum(dev,
2137 ATOM_DEVICE_CRT1_SUPPORT,
2139 ATOM_DEVICE_CRT1_SUPPORT);
2140 radeon_add_legacy_connector(dev, 2,
2141 ATOM_DEVICE_CRT1_SUPPORT,
2142 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2143 CONNECTOR_OBJECT_ID_VGA,
2146 ddc_i2c.valid = false;
2147 hpd.hpd = RADEON_HPD_NONE;
2148 radeon_add_legacy_encoder(dev,
2149 radeon_get_encoder_enum(dev,
2150 ATOM_DEVICE_TV1_SUPPORT,
2152 ATOM_DEVICE_TV1_SUPPORT);
2153 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2154 DRM_MODE_CONNECTOR_SVIDEO,
2156 CONNECTOR_OBJECT_ID_SVIDEO,
2159 case CT_MAC_G4_SILVER:
2160 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2161 rdev->mode_info.connector_table);
2162 /* DVI-I - tv dac, int tmds */
2163 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2164 hpd.hpd = RADEON_HPD_1; /* ??? */
2165 radeon_add_legacy_encoder(dev,
2166 radeon_get_encoder_enum(dev,
2167 ATOM_DEVICE_DFP1_SUPPORT,
2169 ATOM_DEVICE_DFP1_SUPPORT);
2170 radeon_add_legacy_encoder(dev,
2171 radeon_get_encoder_enum(dev,
2172 ATOM_DEVICE_CRT2_SUPPORT,
2174 ATOM_DEVICE_CRT2_SUPPORT);
2175 radeon_add_legacy_connector(dev, 0,
2176 ATOM_DEVICE_DFP1_SUPPORT |
2177 ATOM_DEVICE_CRT2_SUPPORT,
2178 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2179 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2181 /* VGA - primary dac */
2182 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2183 hpd.hpd = RADEON_HPD_NONE;
2184 radeon_add_legacy_encoder(dev,
2185 radeon_get_encoder_enum(dev,
2186 ATOM_DEVICE_CRT1_SUPPORT,
2188 ATOM_DEVICE_CRT1_SUPPORT);
2189 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2190 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2191 CONNECTOR_OBJECT_ID_VGA,
2194 ddc_i2c.valid = false;
2195 hpd.hpd = RADEON_HPD_NONE;
2196 radeon_add_legacy_encoder(dev,
2197 radeon_get_encoder_enum(dev,
2198 ATOM_DEVICE_TV1_SUPPORT,
2200 ATOM_DEVICE_TV1_SUPPORT);
2201 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2202 DRM_MODE_CONNECTOR_SVIDEO,
2204 CONNECTOR_OBJECT_ID_SVIDEO,
2208 DRM_INFO("Connector table: %d (invalid)\n",
2209 rdev->mode_info.connector_table);
2213 radeon_link_encoder_connector(dev);
2218 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2220 enum radeon_combios_connector
2222 struct radeon_i2c_bus_rec *ddc_i2c,
2223 struct radeon_hpd *hpd)
2226 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2227 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2228 if (dev->pdev->device == 0x515e &&
2229 dev->pdev->subsystem_vendor == 0x1014) {
2230 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2231 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2235 /* X300 card with extra non-existent DVI port */
2236 if (dev->pdev->device == 0x5B60 &&
2237 dev->pdev->subsystem_vendor == 0x17af &&
2238 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2239 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2246 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2248 /* Acer 5102 has non-existent TV port */
2249 if (dev->pdev->device == 0x5975 &&
2250 dev->pdev->subsystem_vendor == 0x1025 &&
2251 dev->pdev->subsystem_device == 0x009f)
2254 /* HP dc5750 has non-existent TV port */
2255 if (dev->pdev->device == 0x5974 &&
2256 dev->pdev->subsystem_vendor == 0x103c &&
2257 dev->pdev->subsystem_device == 0x280a)
2260 /* MSI S270 has non-existent TV port */
2261 if (dev->pdev->device == 0x5955 &&
2262 dev->pdev->subsystem_vendor == 0x1462 &&
2263 dev->pdev->subsystem_device == 0x0131)
2269 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2271 struct radeon_device *rdev = dev->dev_private;
2272 uint32_t ext_tmds_info;
2274 if (rdev->flags & RADEON_IS_IGP) {
2276 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2278 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2280 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2281 if (ext_tmds_info) {
2282 uint8_t rev = RBIOS8(ext_tmds_info);
2283 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2286 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2288 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2292 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2294 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2299 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2301 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2304 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2306 struct radeon_device *rdev = dev->dev_private;
2307 uint32_t conn_info, entry, devices;
2308 uint16_t tmp, connector_object_id;
2309 enum radeon_combios_ddc ddc_type;
2310 enum radeon_combios_connector connector;
2312 struct radeon_i2c_bus_rec ddc_i2c;
2313 struct radeon_hpd hpd;
2315 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2317 for (i = 0; i < 4; i++) {
2318 entry = conn_info + 2 + i * 2;
2320 if (!RBIOS16(entry))
2323 tmp = RBIOS16(entry);
2325 connector = (tmp >> 12) & 0xf;
2327 ddc_type = (tmp >> 8) & 0xf;
2329 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2331 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2333 switch (connector) {
2334 case CONNECTOR_PROPRIETARY_LEGACY:
2335 case CONNECTOR_DVI_I_LEGACY:
2336 case CONNECTOR_DVI_D_LEGACY:
2337 if ((tmp >> 4) & 0x1)
2338 hpd.hpd = RADEON_HPD_2;
2340 hpd.hpd = RADEON_HPD_1;
2343 hpd.hpd = RADEON_HPD_NONE;
2347 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2351 switch (connector) {
2352 case CONNECTOR_PROPRIETARY_LEGACY:
2353 if ((tmp >> 4) & 0x1)
2354 devices = ATOM_DEVICE_DFP2_SUPPORT;
2356 devices = ATOM_DEVICE_DFP1_SUPPORT;
2357 radeon_add_legacy_encoder(dev,
2358 radeon_get_encoder_enum
2361 radeon_add_legacy_connector(dev, i, devices,
2362 legacy_connector_convert
2365 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2368 case CONNECTOR_CRT_LEGACY:
2370 devices = ATOM_DEVICE_CRT2_SUPPORT;
2371 radeon_add_legacy_encoder(dev,
2372 radeon_get_encoder_enum
2374 ATOM_DEVICE_CRT2_SUPPORT,
2376 ATOM_DEVICE_CRT2_SUPPORT);
2378 devices = ATOM_DEVICE_CRT1_SUPPORT;
2379 radeon_add_legacy_encoder(dev,
2380 radeon_get_encoder_enum
2382 ATOM_DEVICE_CRT1_SUPPORT,
2384 ATOM_DEVICE_CRT1_SUPPORT);
2386 radeon_add_legacy_connector(dev,
2389 legacy_connector_convert
2392 CONNECTOR_OBJECT_ID_VGA,
2395 case CONNECTOR_DVI_I_LEGACY:
2398 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2399 radeon_add_legacy_encoder(dev,
2400 radeon_get_encoder_enum
2402 ATOM_DEVICE_CRT2_SUPPORT,
2404 ATOM_DEVICE_CRT2_SUPPORT);
2406 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2407 radeon_add_legacy_encoder(dev,
2408 radeon_get_encoder_enum
2410 ATOM_DEVICE_CRT1_SUPPORT,
2412 ATOM_DEVICE_CRT1_SUPPORT);
2414 /* RV100 board with external TDMS bit mis-set.
2415 * Actually uses internal TMDS, clear the bit.
2417 if (dev->pdev->device == 0x5159 &&
2418 dev->pdev->subsystem_vendor == 0x1014 &&
2419 dev->pdev->subsystem_device == 0x029A) {
2422 if ((tmp >> 4) & 0x1) {
2423 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2424 radeon_add_legacy_encoder(dev,
2425 radeon_get_encoder_enum
2427 ATOM_DEVICE_DFP2_SUPPORT,
2429 ATOM_DEVICE_DFP2_SUPPORT);
2430 connector_object_id = combios_check_dl_dvi(dev, 0);
2432 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2433 radeon_add_legacy_encoder(dev,
2434 radeon_get_encoder_enum
2436 ATOM_DEVICE_DFP1_SUPPORT,
2438 ATOM_DEVICE_DFP1_SUPPORT);
2439 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2441 radeon_add_legacy_connector(dev,
2444 legacy_connector_convert
2447 connector_object_id,
2450 case CONNECTOR_DVI_D_LEGACY:
2451 if ((tmp >> 4) & 0x1) {
2452 devices = ATOM_DEVICE_DFP2_SUPPORT;
2453 connector_object_id = combios_check_dl_dvi(dev, 1);
2455 devices = ATOM_DEVICE_DFP1_SUPPORT;
2456 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2458 radeon_add_legacy_encoder(dev,
2459 radeon_get_encoder_enum
2462 radeon_add_legacy_connector(dev, i, devices,
2463 legacy_connector_convert
2466 connector_object_id,
2469 case CONNECTOR_CTV_LEGACY:
2470 case CONNECTOR_STV_LEGACY:
2471 radeon_add_legacy_encoder(dev,
2472 radeon_get_encoder_enum
2474 ATOM_DEVICE_TV1_SUPPORT,
2476 ATOM_DEVICE_TV1_SUPPORT);
2477 radeon_add_legacy_connector(dev, i,
2478 ATOM_DEVICE_TV1_SUPPORT,
2479 legacy_connector_convert
2482 CONNECTOR_OBJECT_ID_SVIDEO,
2486 DRM_ERROR("Unknown connector type: %d\n",
2493 uint16_t tmds_info =
2494 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2496 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2498 radeon_add_legacy_encoder(dev,
2499 radeon_get_encoder_enum(dev,
2500 ATOM_DEVICE_CRT1_SUPPORT,
2502 ATOM_DEVICE_CRT1_SUPPORT);
2503 radeon_add_legacy_encoder(dev,
2504 radeon_get_encoder_enum(dev,
2505 ATOM_DEVICE_DFP1_SUPPORT,
2507 ATOM_DEVICE_DFP1_SUPPORT);
2509 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2510 hpd.hpd = RADEON_HPD_1;
2511 radeon_add_legacy_connector(dev,
2513 ATOM_DEVICE_CRT1_SUPPORT |
2514 ATOM_DEVICE_DFP1_SUPPORT,
2515 DRM_MODE_CONNECTOR_DVII,
2517 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2521 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2522 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2524 radeon_add_legacy_encoder(dev,
2525 radeon_get_encoder_enum(dev,
2526 ATOM_DEVICE_CRT1_SUPPORT,
2528 ATOM_DEVICE_CRT1_SUPPORT);
2529 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2530 hpd.hpd = RADEON_HPD_NONE;
2531 radeon_add_legacy_connector(dev,
2533 ATOM_DEVICE_CRT1_SUPPORT,
2534 DRM_MODE_CONNECTOR_VGA,
2536 CONNECTOR_OBJECT_ID_VGA,
2539 DRM_DEBUG_KMS("No connector info found\n");
2545 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2547 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2549 uint16_t lcd_ddc_info =
2550 combios_get_table_offset(dev,
2551 COMBIOS_LCD_DDC_INFO_TABLE);
2553 radeon_add_legacy_encoder(dev,
2554 radeon_get_encoder_enum(dev,
2555 ATOM_DEVICE_LCD1_SUPPORT,
2557 ATOM_DEVICE_LCD1_SUPPORT);
2560 ddc_type = RBIOS8(lcd_ddc_info + 2);
2564 combios_setup_i2c_bus(rdev,
2566 RBIOS32(lcd_ddc_info + 3),
2567 RBIOS32(lcd_ddc_info + 7));
2568 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2572 combios_setup_i2c_bus(rdev,
2574 RBIOS32(lcd_ddc_info + 3),
2575 RBIOS32(lcd_ddc_info + 7));
2576 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2580 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2583 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2585 ddc_i2c.valid = false;
2587 hpd.hpd = RADEON_HPD_NONE;
2588 radeon_add_legacy_connector(dev,
2590 ATOM_DEVICE_LCD1_SUPPORT,
2591 DRM_MODE_CONNECTOR_LVDS,
2593 CONNECTOR_OBJECT_ID_LVDS,
2598 /* check TV table */
2599 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2601 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2603 if (RBIOS8(tv_info + 6) == 'T') {
2604 if (radeon_apply_legacy_tv_quirks(dev)) {
2605 hpd.hpd = RADEON_HPD_NONE;
2606 ddc_i2c.valid = false;
2607 radeon_add_legacy_encoder(dev,
2608 radeon_get_encoder_enum
2610 ATOM_DEVICE_TV1_SUPPORT,
2612 ATOM_DEVICE_TV1_SUPPORT);
2613 radeon_add_legacy_connector(dev, 6,
2614 ATOM_DEVICE_TV1_SUPPORT,
2615 DRM_MODE_CONNECTOR_SVIDEO,
2617 CONNECTOR_OBJECT_ID_SVIDEO,
2624 radeon_link_encoder_connector(dev);
2629 static const char *thermal_controller_names[] = {
2635 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2637 struct drm_device *dev = rdev->ddev;
2638 u16 offset, misc, misc2 = 0;
2639 u8 rev, blocks, tmp;
2640 int state_index = 0;
2641 struct radeon_i2c_bus_rec i2c_bus;
2643 rdev->pm.default_power_state_index = -1;
2645 /* allocate 2 power states */
2646 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2647 if (rdev->pm.power_state) {
2648 /* allocate 1 clock mode per state */
2649 rdev->pm.power_state[0].clock_info =
2650 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2651 rdev->pm.power_state[1].clock_info =
2652 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2653 if (!rdev->pm.power_state[0].clock_info ||
2654 !rdev->pm.power_state[1].clock_info)
2659 /* check for a thermal chip */
2660 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2662 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2664 rev = RBIOS8(offset);
2667 thermal_controller = RBIOS8(offset + 3);
2668 gpio = RBIOS8(offset + 4) & 0x3f;
2669 i2c_addr = RBIOS8(offset + 5);
2670 } else if (rev == 1) {
2671 thermal_controller = RBIOS8(offset + 4);
2672 gpio = RBIOS8(offset + 5) & 0x3f;
2673 i2c_addr = RBIOS8(offset + 6);
2674 } else if (rev == 2) {
2675 thermal_controller = RBIOS8(offset + 4);
2676 gpio = RBIOS8(offset + 5) & 0x3f;
2677 i2c_addr = RBIOS8(offset + 6);
2678 clk_bit = RBIOS8(offset + 0xa);
2679 data_bit = RBIOS8(offset + 0xb);
2681 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2682 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2683 thermal_controller_names[thermal_controller],
2685 if (gpio == DDC_LCD) {
2687 i2c_bus.valid = true;
2688 i2c_bus.hw_capable = true;
2689 i2c_bus.mm_i2c = true;
2690 i2c_bus.i2c_id = 0xa0;
2691 } else if (gpio == DDC_GPIO)
2692 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2694 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2695 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2696 if (rdev->pm.i2c_bus) {
2697 struct i2c_board_info info = { };
2698 const char *name = thermal_controller_names[thermal_controller];
2699 info.addr = i2c_addr >> 1;
2700 strlcpy(info.type, name, sizeof(info.type));
2701 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2705 /* boards with a thermal chip, but no overdrive table */
2707 /* Asus 9600xt has an f75375 on the monid bus */
2708 if ((dev->pdev->device == 0x4152) &&
2709 (dev->pdev->subsystem_vendor == 0x1043) &&
2710 (dev->pdev->subsystem_device == 0xc002)) {
2711 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2712 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2713 if (rdev->pm.i2c_bus) {
2714 struct i2c_board_info info = { };
2715 const char *name = "f75375";
2717 strlcpy(info.type, name, sizeof(info.type));
2718 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2719 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2725 if (rdev->flags & RADEON_IS_MOBILITY) {
2726 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2728 rev = RBIOS8(offset);
2729 blocks = RBIOS8(offset + 0x2);
2730 /* power mode 0 tends to be the only valid one */
2731 rdev->pm.power_state[state_index].num_clock_modes = 1;
2732 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2733 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2734 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2735 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2737 rdev->pm.power_state[state_index].type =
2738 POWER_STATE_TYPE_BATTERY;
2739 misc = RBIOS16(offset + 0x5 + 0x0);
2741 misc2 = RBIOS16(offset + 0x5 + 0xe);
2742 rdev->pm.power_state[state_index].misc = misc;
2743 rdev->pm.power_state[state_index].misc2 = misc2;
2745 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2747 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2750 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2752 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2754 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2755 RBIOS16(offset + 0x5 + 0xb) * 4;
2756 tmp = RBIOS8(offset + 0x5 + 0xd);
2757 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2759 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2760 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2761 if (entries && voltage_table_offset) {
2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2763 RBIOS16(voltage_table_offset) * 4;
2764 tmp = RBIOS8(voltage_table_offset + 0x2);
2765 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2769 switch ((misc2 & 0x700) >> 8) {
2772 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2775 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2778 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2781 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2784 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2788 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2790 rdev->pm.power_state[state_index].pcie_lanes =
2791 RBIOS8(offset + 0x5 + 0x10);
2792 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2795 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2798 /* XXX figure out some good default low power mode for desktop cards */
2802 /* add the default mode */
2803 rdev->pm.power_state[state_index].type =
2804 POWER_STATE_TYPE_DEFAULT;
2805 rdev->pm.power_state[state_index].num_clock_modes = 1;
2806 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2807 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2808 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2809 if ((state_index > 0) &&
2810 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2811 rdev->pm.power_state[state_index].clock_info[0].voltage =
2812 rdev->pm.power_state[0].clock_info[0].voltage;
2814 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2815 rdev->pm.power_state[state_index].pcie_lanes = 16;
2816 rdev->pm.power_state[state_index].flags = 0;
2817 rdev->pm.default_power_state_index = state_index;
2818 rdev->pm.num_power_states = state_index + 1;
2820 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2821 rdev->pm.current_clock_mode_index = 0;
2825 rdev->pm.default_power_state_index = state_index;
2826 rdev->pm.num_power_states = 0;
2828 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2829 rdev->pm.current_clock_mode_index = 0;
2832 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2834 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2835 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2840 switch (tmds->dvo_chip) {
2843 radeon_i2c_put_byte(tmds->i2c_bus,
2846 radeon_i2c_put_byte(tmds->i2c_bus,
2849 radeon_i2c_put_byte(tmds->i2c_bus,
2852 radeon_i2c_put_byte(tmds->i2c_bus,
2855 radeon_i2c_put_byte(tmds->i2c_bus,
2860 /* sil 1178 - untested */
2879 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2881 struct drm_device *dev = encoder->dev;
2882 struct radeon_device *rdev = dev->dev_private;
2883 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2885 uint8_t blocks, slave_addr, rev;
2887 uint32_t reg, val, and_mask, or_mask;
2888 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2893 if (rdev->flags & RADEON_IS_IGP) {
2894 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2895 rev = RBIOS8(offset);
2897 rev = RBIOS8(offset);
2899 blocks = RBIOS8(offset + 3);
2901 while (blocks > 0) {
2902 id = RBIOS16(index);
2906 reg = (id & 0x1fff) * 4;
2907 val = RBIOS32(index);
2912 reg = (id & 0x1fff) * 4;
2913 and_mask = RBIOS32(index);
2915 or_mask = RBIOS32(index);
2918 val = (val & and_mask) | or_mask;
2922 val = RBIOS16(index);
2927 val = RBIOS16(index);
2932 slave_addr = id & 0xff;
2933 slave_addr >>= 1; /* 7 bit addressing */
2935 reg = RBIOS8(index);
2937 val = RBIOS8(index);
2939 radeon_i2c_put_byte(tmds->i2c_bus,
2944 DRM_ERROR("Unknown id %d\n", id >> 13);
2953 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2955 index = offset + 10;
2956 id = RBIOS16(index);
2957 while (id != 0xffff) {
2961 reg = (id & 0x1fff) * 4;
2962 val = RBIOS32(index);
2966 reg = (id & 0x1fff) * 4;
2967 and_mask = RBIOS32(index);
2969 or_mask = RBIOS32(index);
2972 val = (val & and_mask) | or_mask;
2976 val = RBIOS16(index);
2982 and_mask = RBIOS32(index);
2984 or_mask = RBIOS32(index);
2986 val = RREG32_PLL(reg);
2987 val = (val & and_mask) | or_mask;
2988 WREG32_PLL(reg, val);
2992 val = RBIOS8(index);
2994 radeon_i2c_put_byte(tmds->i2c_bus,
2999 DRM_ERROR("Unknown id %d\n", id >> 13);
3002 id = RBIOS16(index);
3010 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3012 struct radeon_device *rdev = dev->dev_private;
3015 while (RBIOS16(offset)) {
3016 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3017 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3018 uint32_t val, and_mask, or_mask;
3024 val = RBIOS32(offset);
3029 val = RBIOS32(offset);
3034 and_mask = RBIOS32(offset);
3036 or_mask = RBIOS32(offset);
3044 and_mask = RBIOS32(offset);
3046 or_mask = RBIOS32(offset);
3054 val = RBIOS16(offset);
3059 val = RBIOS16(offset);
3066 (RADEON_CLK_PWRMGT_CNTL) &
3073 if ((RREG32(RADEON_MC_STATUS) &
3089 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3091 struct radeon_device *rdev = dev->dev_private;
3094 while (RBIOS8(offset)) {
3095 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3096 uint8_t addr = (RBIOS8(offset) & 0x3f);
3097 uint32_t val, shift, tmp;
3098 uint32_t and_mask, or_mask;
3103 val = RBIOS32(offset);
3105 WREG32_PLL(addr, val);
3108 shift = RBIOS8(offset) * 8;
3110 and_mask = RBIOS8(offset) << shift;
3111 and_mask |= ~(0xff << shift);
3113 or_mask = RBIOS8(offset) << shift;
3115 tmp = RREG32_PLL(addr);
3118 WREG32_PLL(addr, tmp);
3134 (RADEON_CLK_PWRMGT_CNTL) &
3142 (RADEON_CLK_PWRMGT_CNTL) &
3149 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3150 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3152 uint32_t mclk_cntl =
3155 mclk_cntl &= 0xffff0000;
3156 /*mclk_cntl |= 0x00001111;*//* ??? */
3157 WREG32_PLL(RADEON_MCLK_CNTL,
3162 (RADEON_CLK_PWRMGT_CNTL,
3164 ~RADEON_CG_NO1_DEBUG_0);
3179 static void combios_parse_ram_reset_table(struct drm_device *dev,
3182 struct radeon_device *rdev = dev->dev_private;
3186 uint8_t val = RBIOS8(offset);
3187 while (val != 0xff) {
3191 uint32_t channel_complete_mask;
3193 if (ASIC_IS_R300(rdev))
3194 channel_complete_mask =
3195 R300_MEM_PWRUP_COMPLETE;
3197 channel_complete_mask =
3198 RADEON_MEM_PWRUP_COMPLETE;
3201 if ((RREG32(RADEON_MEM_STR_CNTL) &
3202 channel_complete_mask) ==
3203 channel_complete_mask)
3207 uint32_t or_mask = RBIOS16(offset);
3210 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3211 tmp &= RADEON_SDRAM_MODE_MASK;
3213 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3215 or_mask = val << 24;
3216 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3217 tmp &= RADEON_B3MEM_RESET_MASK;
3219 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3221 val = RBIOS8(offset);
3226 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3227 int mem_addr_mapping)
3229 struct radeon_device *rdev = dev->dev_private;
3234 mem_cntl = RREG32(RADEON_MEM_CNTL);
3235 if (mem_cntl & RV100_HALF_MODE)
3238 mem_cntl &= ~(0xff << 8);
3239 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3240 WREG32(RADEON_MEM_CNTL, mem_cntl);
3241 RREG32(RADEON_MEM_CNTL);
3245 /* something like this???? */
3247 addr = ram * 1024 * 1024;
3248 /* write to each page */
3249 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3250 /* read back and verify */
3251 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3258 static void combios_write_ram_size(struct drm_device *dev)
3260 struct radeon_device *rdev = dev->dev_private;
3263 uint32_t mem_size = 0;
3264 uint32_t mem_cntl = 0;
3266 /* should do something smarter here I guess... */
3267 if (rdev->flags & RADEON_IS_IGP)
3270 /* first check detected mem table */
3271 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3273 rev = RBIOS8(offset);
3275 mem_cntl = RBIOS32(offset + 1);
3276 mem_size = RBIOS16(offset + 5);
3277 if ((rdev->family < CHIP_R200) &&
3278 !ASIC_IS_RN50(rdev))
3279 WREG32(RADEON_MEM_CNTL, mem_cntl);
3285 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3287 rev = RBIOS8(offset - 1);
3289 if ((rdev->family < CHIP_R200)
3290 && !ASIC_IS_RN50(rdev)) {
3292 int mem_addr_mapping = 0;
3294 while (RBIOS8(offset)) {
3295 ram = RBIOS8(offset);
3298 if (mem_addr_mapping != 0x25)
3301 combios_detect_ram(dev, ram,
3308 mem_size = RBIOS8(offset);
3310 mem_size = RBIOS8(offset);
3311 mem_size *= 2; /* convert to MB */
3316 mem_size *= (1024 * 1024); /* convert to bytes */
3317 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3320 void radeon_combios_asic_init(struct drm_device *dev)
3322 struct radeon_device *rdev = dev->dev_private;
3325 /* port hardcoded mac stuff from radeonfb */
3326 if (rdev->bios == NULL)
3330 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3332 combios_parse_mmio_table(dev, table);
3335 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3337 combios_parse_pll_table(dev, table);
3340 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3342 combios_parse_mmio_table(dev, table);
3344 if (!(rdev->flags & RADEON_IS_IGP)) {
3347 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3349 combios_parse_mmio_table(dev, table);
3352 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3354 combios_parse_ram_reset_table(dev, table);
3358 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3360 combios_parse_mmio_table(dev, table);
3362 /* write CONFIG_MEMSIZE */
3363 combios_write_ram_size(dev);
3366 /* quirk for rs4xx HP nx6125 laptop to make it resume
3367 * - it hangs on resume inside the dynclk 1 table.
3369 if (rdev->family == CHIP_RS480 &&
3370 rdev->pdev->subsystem_vendor == 0x103c &&
3371 rdev->pdev->subsystem_device == 0x308b)
3374 /* quirk for rs4xx HP dv5000 laptop to make it resume
3375 * - it hangs on resume inside the dynclk 1 table.
3377 if (rdev->family == CHIP_RS480 &&
3378 rdev->pdev->subsystem_vendor == 0x103c &&
3379 rdev->pdev->subsystem_device == 0x30a4)
3382 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3383 * - it hangs on resume inside the dynclk 1 table.
3385 if (rdev->family == CHIP_RS480 &&
3386 rdev->pdev->subsystem_vendor == 0x103c &&
3387 rdev->pdev->subsystem_device == 0x30ae)
3390 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3391 * - it hangs on resume inside the dynclk 1 table.
3393 if (rdev->family == CHIP_RS480 &&
3394 rdev->pdev->subsystem_vendor == 0x103c &&
3395 rdev->pdev->subsystem_device == 0x280a)
3399 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3401 combios_parse_pll_table(dev, table);
3405 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3407 struct radeon_device *rdev = dev->dev_private;
3408 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3410 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3411 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3412 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3414 /* let the bios control the backlight */
3415 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3417 /* tell the bios not to handle mode switching */
3418 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3419 RADEON_ACC_MODE_CHANGE);
3421 /* tell the bios a driver is loaded */
3422 bios_7_scratch |= RADEON_DRV_LOADED;
3424 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3425 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3426 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3429 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3431 struct drm_device *dev = encoder->dev;
3432 struct radeon_device *rdev = dev->dev_private;
3433 uint32_t bios_6_scratch;
3435 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3438 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3440 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3442 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3446 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3447 struct drm_encoder *encoder,
3450 struct drm_device *dev = connector->dev;
3451 struct radeon_device *rdev = dev->dev_private;
3452 struct radeon_connector *radeon_connector =
3453 to_radeon_connector(connector);
3454 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3455 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3456 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3458 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3459 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3461 DRM_DEBUG_KMS("TV1 connected\n");
3463 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3464 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3465 bios_5_scratch |= RADEON_TV1_ON;
3466 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3468 DRM_DEBUG_KMS("TV1 disconnected\n");
3469 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3470 bios_5_scratch &= ~RADEON_TV1_ON;
3471 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3474 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3475 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3477 DRM_DEBUG_KMS("LCD1 connected\n");
3478 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3479 bios_5_scratch |= RADEON_LCD1_ON;
3480 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3482 DRM_DEBUG_KMS("LCD1 disconnected\n");
3483 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3484 bios_5_scratch &= ~RADEON_LCD1_ON;
3485 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3488 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3489 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3491 DRM_DEBUG_KMS("CRT1 connected\n");
3492 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3493 bios_5_scratch |= RADEON_CRT1_ON;
3494 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3496 DRM_DEBUG_KMS("CRT1 disconnected\n");
3497 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3498 bios_5_scratch &= ~RADEON_CRT1_ON;
3499 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3502 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3503 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3505 DRM_DEBUG_KMS("CRT2 connected\n");
3506 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3507 bios_5_scratch |= RADEON_CRT2_ON;
3508 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3510 DRM_DEBUG_KMS("CRT2 disconnected\n");
3511 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3512 bios_5_scratch &= ~RADEON_CRT2_ON;
3513 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3516 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3517 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3519 DRM_DEBUG_KMS("DFP1 connected\n");
3520 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3521 bios_5_scratch |= RADEON_DFP1_ON;
3522 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3524 DRM_DEBUG_KMS("DFP1 disconnected\n");
3525 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3526 bios_5_scratch &= ~RADEON_DFP1_ON;
3527 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3530 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3531 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3533 DRM_DEBUG_KMS("DFP2 connected\n");
3534 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3535 bios_5_scratch |= RADEON_DFP2_ON;
3536 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3538 DRM_DEBUG_KMS("DFP2 disconnected\n");
3539 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3540 bios_5_scratch &= ~RADEON_DFP2_ON;
3541 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3544 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3545 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3549 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3551 struct drm_device *dev = encoder->dev;
3552 struct radeon_device *rdev = dev->dev_private;
3553 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3554 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3556 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3557 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3558 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3560 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3561 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3562 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3564 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3565 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3566 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3568 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3569 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3570 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3572 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3573 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3574 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3576 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3577 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3578 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3580 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3584 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3586 struct drm_device *dev = encoder->dev;
3587 struct radeon_device *rdev = dev->dev_private;
3588 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3589 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3591 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3593 bios_6_scratch |= RADEON_TV_DPMS_ON;
3595 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3597 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3599 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3601 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3605 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3607 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3609 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3611 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3613 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3615 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);