drivers/gpu/drm/radeon/radeon_kfd.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/fdtable.h>
  25 #include <linux/uaccess.h>
  26 #include <drm/drmP.h>
  27 #include "radeon.h"
  28 #include "cikd.h"
  29 #include "cik_reg.h"
  30 #include "radeon_kfd.h"
  31 #include "radeon_ucode.h"
  32 #include <linux/firmware.h>
  33
  34 #define CIK_PIPE_PER_MEC        (4)
  35
  36 struct kgd_mem {
  37         struct radeon_sa_bo *sa_bo;
  38         uint64_t gpu_addr;
  39         void *ptr;
  40 };
  41
  42 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size);
  43 static void fini_sa_manager(struct kgd_dev *kgd);
  44
  45 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
  46                 enum kgd_memory_pool pool, struct kgd_mem **mem);
  47
  48 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem);
  49
  50 static uint64_t get_vmem_size(struct kgd_dev *kgd);
  51 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
  52
  53 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
  54 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
  55
  56 /*
  57  * Register access functions
  58  */
  59
  60 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
  61                 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
  62                 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
  63
  64 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
  65                                         unsigned int vmid);
  66
  67 static int kgd_init_memory(struct kgd_dev *kgd);
  68
  69 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
  70                                 uint32_t hpd_size, uint64_t hpd_gpu_addr);
  71
  72 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
  73                         uint32_t queue_id, uint32_t __user *wptr);
  74
  75 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
  76                                 uint32_t pipe_id, uint32_t queue_id);
  77
  78 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
  79                                 unsigned int timeout, uint32_t pipe_id,
  80                                 uint32_t queue_id);
  81
  82 static const struct kfd2kgd_calls kfd2kgd = {
  83         .init_sa_manager = init_sa_manager,
  84         .fini_sa_manager = fini_sa_manager,
  85         .allocate_mem = allocate_mem,
  86         .free_mem = free_mem,
  87         .get_vmem_size = get_vmem_size,
  88         .get_gpu_clock_counter = get_gpu_clock_counter,
  89         .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
  90         .program_sh_mem_settings = kgd_program_sh_mem_settings,
  91         .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
  92         .init_memory = kgd_init_memory,
  93         .init_pipeline = kgd_init_pipeline,
  94         .hqd_load = kgd_hqd_load,
  95         .hqd_is_occupied = kgd_hqd_is_occupied,
  96         .hqd_destroy = kgd_hqd_destroy,
  97         .get_fw_version = get_fw_version
  98 };
  99
 100 static const struct kgd2kfd_calls *kgd2kfd;
 101
 102 bool radeon_kfd_init(void)
 103 {
 104 #if defined(CONFIG_HSA_AMD_MODULE)
 105         bool (*kgd2kfd_init_p)(unsigned, const struct kfd2kgd_calls*,
 106                                 const struct kgd2kfd_calls**);
 107
 108         kgd2kfd_init_p = symbol_request(kgd2kfd_init);
 109
 110         if (kgd2kfd_init_p == NULL)
 111                 return false;
 112
 113         if (!kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
 114                 symbol_put(kgd2kfd_init);
 115                 kgd2kfd = NULL;
 116
 117                 return false;
 118         }
 119
 120         return true;
 121 #elif defined(CONFIG_HSA_AMD)
 122         if (!kgd2kfd_init(KFD_INTERFACE_VERSION, &kfd2kgd, &kgd2kfd)) {
 123                 kgd2kfd = NULL;
 124
 125                 return false;
 126         }
 127
 128         return true;
 129 #else
 130         return false;
 131 #endif
 132 }
 133
 134 void radeon_kfd_fini(void)
 135 {
 136         if (kgd2kfd) {
 137                 kgd2kfd->exit();
 138                 symbol_put(kgd2kfd_init);
 139         }
 140 }
 141
 142 void radeon_kfd_device_probe(struct radeon_device *rdev)
 143 {
 144         if (kgd2kfd)
 145                 rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev, rdev->pdev);
 146 }
 147
 148 void radeon_kfd_device_init(struct radeon_device *rdev)
 149 {
 150         if (rdev->kfd) {
 151                 struct kgd2kfd_shared_resources gpu_resources = {
 152                         .compute_vmid_bitmap = 0xFF00,
 153
 154                         .first_compute_pipe = 1,
 155                         .compute_pipe_count = 8 - 1,
 156                 };
 157
 158                 radeon_doorbell_get_kfd_info(rdev,
 159                                 &gpu_resources.doorbell_physical_address,
 160                                 &gpu_resources.doorbell_aperture_size,
 161                                 &gpu_resources.doorbell_start_offset);
 162
 163                 kgd2kfd->device_init(rdev->kfd, &gpu_resources);
 164         }
 165 }
 166
 167 void radeon_kfd_device_fini(struct radeon_device *rdev)
 168 {
 169         if (rdev->kfd) {
 170                 kgd2kfd->device_exit(rdev->kfd);
 171                 rdev->kfd = NULL;
 172         }
 173 }
 174
 175 void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
 176 {
 177         if (rdev->kfd)
 178                 kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
 179 }
 180
 181 void radeon_kfd_suspend(struct radeon_device *rdev)
 182 {
 183         if (rdev->kfd)
 184                 kgd2kfd->suspend(rdev->kfd);
 185 }
 186
 187 int radeon_kfd_resume(struct radeon_device *rdev)
 188 {
 189         int r = 0;
 190
 191         if (rdev->kfd)
 192                 r = kgd2kfd->resume(rdev->kfd);
 193
 194         return r;
 195 }
 196
 197 static u32 pool_to_domain(enum kgd_memory_pool p)
 198 {
 199         switch (p) {
 200         case KGD_POOL_FRAMEBUFFER: return RADEON_GEM_DOMAIN_VRAM;
 201         default: return RADEON_GEM_DOMAIN_GTT;
 202         }
 203 }
 204
 205 static int init_sa_manager(struct kgd_dev *kgd, unsigned int size)
 206 {
 207         struct radeon_device *rdev = (struct radeon_device *)kgd;
 208         int r;
 209
 210         BUG_ON(kgd == NULL);
 211
 212         r = radeon_sa_bo_manager_init(rdev, &rdev->kfd_bo,
 213                                       size,
 214                                       RADEON_GPU_PAGE_SIZE,
 215                                       RADEON_GEM_DOMAIN_GTT,
 216                                       RADEON_GEM_GTT_WC);
 217
 218         if (r)
 219                 return r;
 220
 221         r = radeon_sa_bo_manager_start(rdev, &rdev->kfd_bo);
 222         if (r)
 223                 radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
 224
 225         return r;
 226 }
 227
 228 static void fini_sa_manager(struct kgd_dev *kgd)
 229 {
 230         struct radeon_device *rdev = (struct radeon_device *)kgd;
 231
 232         BUG_ON(kgd == NULL);
 233
 234         radeon_sa_bo_manager_suspend(rdev, &rdev->kfd_bo);
 235         radeon_sa_bo_manager_fini(rdev, &rdev->kfd_bo);
 236 }
 237
 238 static int allocate_mem(struct kgd_dev *kgd, size_t size, size_t alignment,
 239                 enum kgd_memory_pool pool, struct kgd_mem **mem)
 240 {
 241         struct radeon_device *rdev = (struct radeon_device *)kgd;
 242         u32 domain;
 243         int r;
 244
 245         BUG_ON(kgd == NULL);
 246
 247         domain = pool_to_domain(pool);
 248         if (domain != RADEON_GEM_DOMAIN_GTT) {
 249                 dev_err(rdev->dev,
 250                         "Only allowed to allocate gart memory for kfd\n");
 251                 return -EINVAL;
 252         }
 253
 254         *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
 255         if ((*mem) == NULL)
 256                 return -ENOMEM;
 257
 258         r = radeon_sa_bo_new(rdev, &rdev->kfd_bo, &(*mem)->sa_bo, size,
 259                                 alignment);
 260         if (r) {
 261                 dev_err(rdev->dev, "failed to get memory for kfd (%d)\n", r);
 262                 return r;
 263         }
 264
 265         (*mem)->ptr = radeon_sa_bo_cpu_addr((*mem)->sa_bo);
 266         (*mem)->gpu_addr = radeon_sa_bo_gpu_addr((*mem)->sa_bo);
 267
 268         return 0;
 269 }
 270
 271 static void free_mem(struct kgd_dev *kgd, struct kgd_mem *mem)
 272 {
 273         struct radeon_device *rdev = (struct radeon_device *)kgd;
 274
 275         BUG_ON(kgd == NULL);
 276
 277         radeon_sa_bo_free(rdev, &mem->sa_bo, NULL);
 278         kfree(mem);
 279 }
 280
 281 static uint64_t get_vmem_size(struct kgd_dev *kgd)
 282 {
 283         struct radeon_device *rdev = (struct radeon_device *)kgd;
 284
 285         BUG_ON(kgd == NULL);
 286
 287         return rdev->mc.real_vram_size;
 288 }
 289
 290 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
 291 {
 292         struct radeon_device *rdev = (struct radeon_device *)kgd;
 293
 294         return rdev->asic->get_gpu_clock_counter(rdev);
 295 }
 296
 297 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
 298 {
 299         struct radeon_device *rdev = (struct radeon_device *)kgd;
 300
 301         /* The sclk is in quantas of 10kHz */
 302         return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
 303 }
 304
 305 static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
 306 {
 307         return (struct radeon_device *)kgd;
 308 }
 309
 310 static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
 311 {
 312         struct radeon_device *rdev = get_radeon_device(kgd);
 313
 314         writel(value, (void __iomem *)(rdev->rmmio + offset));
 315 }
 316
 317 static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
 318 {
 319         struct radeon_device *rdev = get_radeon_device(kgd);
 320
 321         return readl((void __iomem *)(rdev->rmmio + offset));
 322 }
 323
 324 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
 325                         uint32_t queue, uint32_t vmid)
 326 {
 327         struct radeon_device *rdev = get_radeon_device(kgd);
 328         uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
 329
 330         mutex_lock(&rdev->srbm_mutex);
 331         write_register(kgd, SRBM_GFX_CNTL, value);
 332 }
 333
 334 static void unlock_srbm(struct kgd_dev *kgd)
 335 {
 336         struct radeon_device *rdev = get_radeon_device(kgd);
 337
 338         write_register(kgd, SRBM_GFX_CNTL, 0);
 339         mutex_unlock(&rdev->srbm_mutex);
 340 }
 341
 342 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
 343                                 uint32_t queue_id)
 344 {
 345         uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
 346         uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
 347
 348         lock_srbm(kgd, mec, pipe, queue_id, 0);
 349 }
 350
 351 static void release_queue(struct kgd_dev *kgd)
 352 {
 353         unlock_srbm(kgd);
 354 }
 355
 356 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
 357                                         uint32_t sh_mem_config,
 358                                         uint32_t sh_mem_ape1_base,
 359                                         uint32_t sh_mem_ape1_limit,
 360                                         uint32_t sh_mem_bases)
 361 {
 362         lock_srbm(kgd, 0, 0, 0, vmid);
 363
 364         write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
 365         write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
 366         write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
 367         write_register(kgd, SH_MEM_BASES, sh_mem_bases);
 368
 369         unlock_srbm(kgd);
 370 }
 371
 372 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
 373                                         unsigned int vmid)
 374 {
 375         /*
 376          * We have to assume that there is no outstanding mapping.
 377          * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
 378          * because a mapping is in progress or because a mapping finished and
 379          * the SW cleared it.
 380          * So the protocol is to always wait & clear.
 381          */
 382         uint32_t pasid_mapping = (pasid == 0) ? 0 :
 383                                 (uint32_t)pasid | ATC_VMID_PASID_MAPPING_VALID;
 384
 385         write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
 386                         pasid_mapping);
 387
 388         while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
 389                                                                 (1U << vmid)))
 390                 cpu_relax();
 391         write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
 392
 393         /* Mapping vmid to pasid also for IH block */
 394         write_register(kgd, IH_VMID_0_LUT + vmid * sizeof(uint32_t),
 395                         pasid_mapping);
 396
 397         return 0;
 398 }
 399
 400 static int kgd_init_memory(struct kgd_dev *kgd)
 401 {
 402         /*
 403          * Configure apertures:
 404          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
 405          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
 406          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
 407          */
 408         int i;
 409         uint32_t sh_mem_bases = PRIVATE_BASE(0x6000) | SHARED_BASE(0x6000);
 410
 411         for (i = 8; i < 16; i++) {
 412                 uint32_t sh_mem_config;
 413
 414                 lock_srbm(kgd, 0, 0, 0, i);
 415
 416                 sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
 417                 sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
 418
 419                 write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
 420
 421                 write_register(kgd, SH_MEM_BASES, sh_mem_bases);
 422
 423                 /* Scratch aperture is not supported for now. */
 424                 write_register(kgd, SH_STATIC_MEM_CONFIG, 0);
 425
 426                 /* APE1 disabled for now. */
 427                 write_register(kgd, SH_MEM_APE1_BASE, 1);
 428                 write_register(kgd, SH_MEM_APE1_LIMIT, 0);
 429
 430                 unlock_srbm(kgd);
 431         }
 432
 433         return 0;
 434 }
 435
 436 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
 437                                 uint32_t hpd_size, uint64_t hpd_gpu_addr)
 438 {
 439         uint32_t mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
 440         uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
 441
 442         lock_srbm(kgd, mec, pipe, 0, 0);
 443         write_register(kgd, CP_HPD_EOP_BASE_ADDR,
 444                         lower_32_bits(hpd_gpu_addr >> 8));
 445         write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI,
 446                         upper_32_bits(hpd_gpu_addr >> 8));
 447         write_register(kgd, CP_HPD_EOP_VMID, 0);
 448         write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size);
 449         unlock_srbm(kgd);
 450
 451         return 0;
 452 }
 453
 454 static inline struct cik_mqd *get_mqd(void *mqd)
 455 {
 456         return (struct cik_mqd *)mqd;
 457 }
 458
 459 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 460                         uint32_t queue_id, uint32_t __user *wptr)
 461 {
 462         uint32_t wptr_shadow, is_wptr_shadow_valid;
 463         struct cik_mqd *m;
 464
 465         m = get_mqd(mqd);
 466
 467         is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
 468
 469         acquire_queue(kgd, pipe_id, queue_id);
 470         write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
 471         write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
 472         write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
 473
 474         write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
 475         write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
 476         write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
 477
 478         write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
 479         write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
 480         write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
 481
 482         write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
 483
 484         write_register(kgd, CP_HQD_PERSISTENT_STATE,
 485                         m->cp_hqd_persistent_state);
 486         write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
 487         write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
 488
 489         write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
 490                         m->cp_hqd_atomic0_preop_lo);
 491
 492         write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
 493                         m->cp_hqd_atomic0_preop_hi);
 494
 495         write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
 496                         m->cp_hqd_atomic1_preop_lo);
 497
 498         write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
 499                         m->cp_hqd_atomic1_preop_hi);
 500
 501         write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
 502                         m->cp_hqd_pq_rptr_report_addr_lo);
 503
 504         write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 505                         m->cp_hqd_pq_rptr_report_addr_hi);
 506
 507         write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
 508
 509         write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
 510                         m->cp_hqd_pq_wptr_poll_addr_lo);
 511
 512         write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
 513                         m->cp_hqd_pq_wptr_poll_addr_hi);
 514
 515         write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
 516                         m->cp_hqd_pq_doorbell_control);
 517
 518         write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
 519
 520         write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
 521
 522         write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
 523         write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
 524
 525         write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
 526
 527         if (is_wptr_shadow_valid)
 528                 write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
 529
 530         write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
 531         release_queue(kgd);
 532
 533         return 0;
 534 }
 535
 536 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 537                                 uint32_t pipe_id, uint32_t queue_id)
 538 {
 539         uint32_t act;
 540         bool retval = false;
 541         uint32_t low, high;
 542
 543         acquire_queue(kgd, pipe_id, queue_id);
 544         act = read_register(kgd, CP_HQD_ACTIVE);
 545         if (act) {
 546                 low = lower_32_bits(queue_address >> 8);
 547                 high = upper_32_bits(queue_address >> 8);
 548
 549                 if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
 550                                 high == read_register(kgd, CP_HQD_PQ_BASE_HI))
 551                         retval = true;
 552         }
 553         release_queue(kgd);
 554         return retval;
 555 }
 556
 557 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
 558                                 unsigned int timeout, uint32_t pipe_id,
 559                                 uint32_t queue_id)
 560 {
 561         uint32_t temp;
 562
 563         acquire_queue(kgd, pipe_id, queue_id);
 564         write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
 565
 566         write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
 567
 568         while (true) {
 569                 temp = read_register(kgd, CP_HQD_ACTIVE);
 570                 if (temp & 0x1)
 571                         break;
 572                 if (timeout == 0) {
 573                         pr_err("kfd: cp queue preemption time out (%dms)\n",
 574                                 temp);
 575                         release_queue(kgd);
 576                         return -ETIME;
 577                 }
 578                 msleep(20);
 579                 timeout -= 20;
 580         }
 581
 582         release_queue(kgd);
 583         return 0;
 584 }
 585
 586 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 587 {
 588         struct radeon_device *rdev = (struct radeon_device *) kgd;
 589         const union radeon_firmware_header *hdr;
 590
 591         BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
 592
 593         switch (type) {
 594         case KGD_ENGINE_PFP:
 595                 hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
 596                 break;
 597
 598         case KGD_ENGINE_ME:
 599                 hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
 600                 break;
 601
 602         case KGD_ENGINE_CE:
 603                 hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
 604                 break;
 605
 606         case KGD_ENGINE_MEC1:
 607                 hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
 608                 break;
 609
 610         case KGD_ENGINE_MEC2:
 611                 hdr = (const union radeon_firmware_header *)
 612                                                         rdev->mec2_fw->data;
 613                 break;
 614
 615         case KGD_ENGINE_RLC:
 616                 hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
 617                 break;
 618
 619         case KGD_ENGINE_SDMA:
 620                 hdr = (const union radeon_firmware_header *)
 621                                                         rdev->sdma_fw->data;
 622                 break;
 623
 624         default:
 625                 return 0;
 626         }
 627
 628         if (hdr == NULL)
 629                 return 0;
 630
 631         /* Only 12 bit in use*/
 632         return hdr->common.ucode_version;
 633 }