2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #define RADEON_IDLE_LOOP_MS 100
28 #define RADEON_RECLOCK_DELAY_MS 200
29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
30 #define RADEON_WAIT_IDLE_TIMEOUT 200
32 static void radeon_pm_idle_work_handler(struct work_struct *work);
33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
35 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
37 struct radeon_bo *bo, *n;
39 if (list_empty(&rdev->gem.objects))
42 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
43 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
44 ttm_bo_unmap_virtual(&bo->tbo);
47 if (rdev->gart.table.vram.robj)
48 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
50 if (rdev->stollen_vga_memory)
51 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
53 if (rdev->r600_blit.shader_obj)
54 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
57 static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
62 radeon_get_power_state(rdev, rdev->pm.planned_action);
64 mutex_lock(&rdev->ddev->struct_mutex);
65 mutex_lock(&rdev->vram_mutex);
66 mutex_lock(&rdev->cp.mutex);
68 /* gui idle int has issues on older chips it seems */
69 if (rdev->family >= CHIP_R600) {
70 /* wait for GPU idle */
71 rdev->pm.gui_idle = false;
72 rdev->irq.gui_idle = true;
74 wait_event_interruptible_timeout(
75 rdev->irq.idle_queue, rdev->pm.gui_idle,
76 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
77 rdev->irq.gui_idle = false;
80 radeon_unmap_vram_bos(rdev);
83 for (i = 0; i < rdev->num_crtc; i++) {
84 if (rdev->pm.active_crtcs & (1 << i)) {
85 rdev->pm.req_vblank |= (1 << i);
86 drm_vblank_get(rdev->ddev, i);
91 radeon_set_power_state(rdev, static_switch);
94 for (i = 0; i < rdev->num_crtc; i++) {
95 if (rdev->pm.req_vblank & (1 << i)) {
96 rdev->pm.req_vblank &= ~(1 << i);
97 drm_vblank_put(rdev->ddev, i);
102 /* update display watermarks based on new power state */
103 radeon_update_bandwidth_info(rdev);
104 if (rdev->pm.active_crtc_count)
105 radeon_bandwidth_update(rdev);
107 rdev->pm.planned_action = PM_ACTION_NONE;
109 mutex_unlock(&rdev->cp.mutex);
110 mutex_unlock(&rdev->vram_mutex);
111 mutex_unlock(&rdev->ddev->struct_mutex);
114 static ssize_t radeon_get_power_state_static(struct device *dev,
115 struct device_attribute *attr,
118 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
119 struct radeon_device *rdev = ddev->dev_private;
121 return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
122 rdev->pm.current_clock_mode_index);
125 static ssize_t radeon_set_power_state_static(struct device *dev,
126 struct device_attribute *attr,
130 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
131 struct radeon_device *rdev = ddev->dev_private;
134 if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
135 DRM_ERROR("Invalid power state!\n");
139 mutex_lock(&rdev->pm.mutex);
140 if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
141 (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
142 if ((rdev->pm.active_crtc_count > 1) &&
143 (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
144 DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
147 rdev->pm.state = PM_STATE_DISABLED;
148 rdev->pm.planned_action = PM_ACTION_NONE;
149 rdev->pm.requested_power_state_index = ps;
150 rdev->pm.requested_clock_mode_index = cm;
151 radeon_pm_set_clocks(rdev, true);
154 DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
155 mutex_unlock(&rdev->pm.mutex);
160 static ssize_t radeon_get_dynpm(struct device *dev,
161 struct device_attribute *attr,
164 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
165 struct radeon_device *rdev = ddev->dev_private;
167 return snprintf(buf, PAGE_SIZE, "%s\n",
168 (rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
171 static ssize_t radeon_set_dynpm(struct device *dev,
172 struct device_attribute *attr,
176 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
177 struct radeon_device *rdev = ddev->dev_private;
178 int tmp = simple_strtoul(buf, NULL, 10);
181 /* update power mode info */
182 radeon_pm_compute_clocks(rdev);
184 mutex_lock(&rdev->pm.mutex);
185 rdev->pm.state = PM_STATE_DISABLED;
186 rdev->pm.planned_action = PM_ACTION_NONE;
187 mutex_unlock(&rdev->pm.mutex);
188 DRM_INFO("radeon: dynamic power management disabled\n");
189 } else if (tmp == 1) {
190 if (rdev->pm.num_power_states > 1) {
192 mutex_lock(&rdev->pm.mutex);
193 rdev->pm.state = PM_STATE_PAUSED;
194 rdev->pm.planned_action = PM_ACTION_DEFAULT;
195 radeon_get_power_state(rdev, rdev->pm.planned_action);
196 mutex_unlock(&rdev->pm.mutex);
197 /* update power mode info */
198 radeon_pm_compute_clocks(rdev);
199 DRM_INFO("radeon: dynamic power management enabled\n");
201 DRM_ERROR("dynpm not valid on this system\n");
203 DRM_ERROR("Invalid setting: %d\n", tmp);
208 static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
209 static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
212 static const char *pm_state_names[4] = {
219 static const char *pm_state_types[5] = {
227 static void radeon_print_power_mode_info(struct radeon_device *rdev)
232 DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
233 for (i = 0; i < rdev->pm.num_power_states; i++) {
234 if (rdev->pm.default_power_state_index == i)
238 DRM_INFO("State %d %s %s\n", i,
239 pm_state_types[rdev->pm.power_state[i].type],
240 is_default ? "(default)" : "");
241 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
242 DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
243 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
244 DRM_INFO("\tSingle display only\n");
245 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
246 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
247 if (rdev->flags & RADEON_IS_IGP)
248 DRM_INFO("\t\t%d engine: %d\n",
250 rdev->pm.power_state[i].clock_info[j].sclk * 10);
252 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
254 rdev->pm.power_state[i].clock_info[j].sclk * 10,
255 rdev->pm.power_state[i].clock_info[j].mclk * 10);
260 void radeon_sync_with_vblank(struct radeon_device *rdev)
262 if (rdev->pm.active_crtcs) {
263 rdev->pm.vblank_sync = false;
265 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
266 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
270 int radeon_pm_init(struct radeon_device *rdev)
272 rdev->pm.state = PM_STATE_DISABLED;
273 rdev->pm.planned_action = PM_ACTION_NONE;
274 rdev->pm.can_upclock = true;
275 rdev->pm.can_downclock = true;
278 if (rdev->is_atom_bios)
279 radeon_atombios_get_power_modes(rdev);
281 radeon_combios_get_power_modes(rdev);
282 radeon_print_power_mode_info(rdev);
285 if (radeon_debugfs_pm_init(rdev)) {
286 DRM_ERROR("Failed to register debugfs file for PM!\n");
289 /* where's the best place to put this? */
290 device_create_file(rdev->dev, &dev_attr_power_state);
291 device_create_file(rdev->dev, &dev_attr_dynpm);
293 INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
295 if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
296 rdev->pm.state = PM_STATE_PAUSED;
297 DRM_INFO("radeon: dynamic power management enabled\n");
300 DRM_INFO("radeon: power management initialized\n");
305 void radeon_pm_fini(struct radeon_device *rdev)
307 if (rdev->pm.state != PM_STATE_DISABLED) {
309 cancel_delayed_work_sync(&rdev->pm.idle_work);
310 /* reset default clocks */
311 rdev->pm.state = PM_STATE_DISABLED;
312 rdev->pm.planned_action = PM_ACTION_DEFAULT;
313 radeon_pm_set_clocks(rdev, false);
314 } else if ((rdev->pm.current_power_state_index !=
315 rdev->pm.default_power_state_index) ||
316 (rdev->pm.current_clock_mode_index != 0)) {
317 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
318 rdev->pm.requested_clock_mode_index = 0;
319 mutex_lock(&rdev->pm.mutex);
320 radeon_pm_set_clocks(rdev, true);
321 mutex_unlock(&rdev->pm.mutex);
324 device_remove_file(rdev->dev, &dev_attr_power_state);
325 device_remove_file(rdev->dev, &dev_attr_dynpm);
327 if (rdev->pm.i2c_bus)
328 radeon_i2c_destroy(rdev->pm.i2c_bus);
331 void radeon_pm_compute_clocks(struct radeon_device *rdev)
333 struct drm_device *ddev = rdev->ddev;
334 struct drm_crtc *crtc;
335 struct radeon_crtc *radeon_crtc;
337 if (rdev->pm.state == PM_STATE_DISABLED)
340 mutex_lock(&rdev->pm.mutex);
342 rdev->pm.active_crtcs = 0;
343 rdev->pm.active_crtc_count = 0;
344 list_for_each_entry(crtc,
345 &ddev->mode_config.crtc_list, head) {
346 radeon_crtc = to_radeon_crtc(crtc);
347 if (radeon_crtc->enabled) {
348 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
349 rdev->pm.active_crtc_count++;
353 if (rdev->pm.active_crtc_count > 1) {
354 if (rdev->pm.state == PM_STATE_ACTIVE) {
355 cancel_delayed_work(&rdev->pm.idle_work);
357 rdev->pm.state = PM_STATE_PAUSED;
358 rdev->pm.planned_action = PM_ACTION_UPCLOCK;
359 radeon_pm_set_clocks(rdev, false);
361 DRM_DEBUG("radeon: dynamic power management deactivated\n");
363 } else if (rdev->pm.active_crtc_count == 1) {
364 /* TODO: Increase clocks if needed for current mode */
366 if (rdev->pm.state == PM_STATE_MINIMUM) {
367 rdev->pm.state = PM_STATE_ACTIVE;
368 rdev->pm.planned_action = PM_ACTION_UPCLOCK;
369 radeon_pm_set_clocks(rdev, false);
371 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
372 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
373 } else if (rdev->pm.state == PM_STATE_PAUSED) {
374 rdev->pm.state = PM_STATE_ACTIVE;
375 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
376 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
377 DRM_DEBUG("radeon: dynamic power management activated\n");
379 } else { /* count == 0 */
380 if (rdev->pm.state != PM_STATE_MINIMUM) {
381 cancel_delayed_work(&rdev->pm.idle_work);
383 rdev->pm.state = PM_STATE_MINIMUM;
384 rdev->pm.planned_action = PM_ACTION_MINIMUM;
385 radeon_pm_set_clocks(rdev, false);
389 mutex_unlock(&rdev->pm.mutex);
392 bool radeon_pm_in_vbl(struct radeon_device *rdev)
394 u32 stat_crtc = 0, vbl = 0, position = 0;
397 if (ASIC_IS_DCE4(rdev)) {
398 if (rdev->pm.active_crtcs & (1 << 0)) {
399 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
400 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
401 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
402 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
404 if (rdev->pm.active_crtcs & (1 << 1)) {
405 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
406 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
407 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
408 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
410 if (rdev->pm.active_crtcs & (1 << 2)) {
411 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
412 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
413 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
414 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
416 if (rdev->pm.active_crtcs & (1 << 3)) {
417 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
418 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
419 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
420 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
422 if (rdev->pm.active_crtcs & (1 << 4)) {
423 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
424 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
425 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
426 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
428 if (rdev->pm.active_crtcs & (1 << 5)) {
429 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
430 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
431 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
432 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
434 } else if (ASIC_IS_AVIVO(rdev)) {
435 if (rdev->pm.active_crtcs & (1 << 0)) {
436 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
437 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
439 if (rdev->pm.active_crtcs & (1 << 1)) {
440 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
441 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
443 if (position < vbl && position > 1)
446 if (rdev->pm.active_crtcs & (1 << 0)) {
447 stat_crtc = RREG32(RADEON_CRTC_STATUS);
448 if (!(stat_crtc & 1))
451 if (rdev->pm.active_crtcs & (1 << 1)) {
452 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
453 if (!(stat_crtc & 1))
458 if (position < vbl && position > 1)
464 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
467 bool in_vbl = radeon_pm_in_vbl(rdev);
470 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
471 finish ? "exit" : "entry");
475 static void radeon_pm_idle_work_handler(struct work_struct *work)
477 struct radeon_device *rdev;
479 rdev = container_of(work, struct radeon_device,
482 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
483 mutex_lock(&rdev->pm.mutex);
484 if (rdev->pm.state == PM_STATE_ACTIVE) {
485 unsigned long irq_flags;
486 int not_processed = 0;
488 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
489 if (!list_empty(&rdev->fence_drv.emited)) {
490 struct list_head *ptr;
491 list_for_each(ptr, &rdev->fence_drv.emited) {
492 /* count up to 3, that's enought info */
493 if (++not_processed >= 3)
497 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
499 if (not_processed >= 3) { /* should upclock */
500 if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
501 rdev->pm.planned_action = PM_ACTION_NONE;
502 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
503 rdev->pm.can_upclock) {
504 rdev->pm.planned_action =
506 rdev->pm.action_timeout = jiffies +
507 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
509 } else if (not_processed == 0) { /* should downclock */
510 if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
511 rdev->pm.planned_action = PM_ACTION_NONE;
512 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
513 rdev->pm.can_downclock) {
514 rdev->pm.planned_action =
516 rdev->pm.action_timeout = jiffies +
517 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
521 if (rdev->pm.planned_action != PM_ACTION_NONE &&
522 jiffies > rdev->pm.action_timeout) {
523 radeon_pm_set_clocks(rdev, false);
526 mutex_unlock(&rdev->pm.mutex);
527 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
529 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
530 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
536 #if defined(CONFIG_DEBUG_FS)
538 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
540 struct drm_info_node *node = (struct drm_info_node *) m->private;
541 struct drm_device *dev = node->minor->dev;
542 struct radeon_device *rdev = dev->dev_private;
544 seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
545 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
546 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
547 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
548 if (rdev->asic->get_memory_clock)
549 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
550 if (rdev->asic->get_pcie_lanes)
551 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
556 static struct drm_info_list radeon_pm_info_list[] = {
557 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
561 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
563 #if defined(CONFIG_DEBUG_FS)
564 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));