2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <ttm/ttm_bo_api.h>
33 #include <ttm/ttm_bo_driver.h>
34 #include <ttm/ttm_placement.h>
35 #include <ttm/ttm_module.h>
36 #include <ttm/ttm_page_alloc.h>
38 #include <drm/radeon_drm.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/swiotlb.h>
42 #include <linux/swap.h>
43 #include <linux/pagemap.h>
44 #include <linux/debugfs.h>
45 #include "radeon_reg.h"
48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
50 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
51 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
53 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
55 struct radeon_mman *mman;
56 struct radeon_device *rdev;
58 mman = container_of(bdev, struct radeon_mman, bdev);
59 rdev = container_of(mman, struct radeon_device, mman);
67 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
69 return ttm_mem_global_init(ref->object);
72 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
74 ttm_mem_global_release(ref->object);
77 static int radeon_ttm_global_init(struct radeon_device *rdev)
79 struct drm_global_reference *global_ref;
82 rdev->mman.mem_global_referenced = false;
83 global_ref = &rdev->mman.mem_global_ref;
84 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
85 global_ref->size = sizeof(struct ttm_mem_global);
86 global_ref->init = &radeon_ttm_mem_global_init;
87 global_ref->release = &radeon_ttm_mem_global_release;
88 r = drm_global_item_ref(global_ref);
90 DRM_ERROR("Failed setting up TTM memory accounting "
95 rdev->mman.bo_global_ref.mem_glob =
96 rdev->mman.mem_global_ref.object;
97 global_ref = &rdev->mman.bo_global_ref.ref;
98 global_ref->global_type = DRM_GLOBAL_TTM_BO;
99 global_ref->size = sizeof(struct ttm_bo_global);
100 global_ref->init = &ttm_bo_global_init;
101 global_ref->release = &ttm_bo_global_release;
102 r = drm_global_item_ref(global_ref);
104 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
105 drm_global_item_unref(&rdev->mman.mem_global_ref);
109 rdev->mman.mem_global_referenced = true;
113 static void radeon_ttm_global_fini(struct radeon_device *rdev)
115 if (rdev->mman.mem_global_referenced) {
116 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
117 drm_global_item_unref(&rdev->mman.mem_global_ref);
118 rdev->mman.mem_global_referenced = false;
122 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
127 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
128 struct ttm_mem_type_manager *man)
130 struct radeon_device *rdev;
132 rdev = radeon_get_rdev(bdev);
137 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
138 man->available_caching = TTM_PL_MASK_CACHING;
139 man->default_caching = TTM_PL_FLAG_CACHED;
142 man->func = &ttm_bo_manager_func;
143 man->gpu_offset = rdev->mc.gtt_start;
144 man->available_caching = TTM_PL_MASK_CACHING;
145 man->default_caching = TTM_PL_FLAG_CACHED;
146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
148 if (rdev->flags & RADEON_IS_AGP) {
149 if (!rdev->ddev->agp) {
150 DRM_ERROR("AGP is not enabled for memory type %u\n",
154 if (!rdev->ddev->agp->cant_use_aperture)
155 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
156 man->available_caching = TTM_PL_FLAG_UNCACHED |
158 man->default_caching = TTM_PL_FLAG_WC;
163 /* "On-card" video ram */
164 man->func = &ttm_bo_manager_func;
165 man->gpu_offset = rdev->mc.vram_start;
166 man->flags = TTM_MEMTYPE_FLAG_FIXED |
167 TTM_MEMTYPE_FLAG_MAPPABLE;
168 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
169 man->default_caching = TTM_PL_FLAG_WC;
172 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
178 static void radeon_evict_flags(struct ttm_buffer_object *bo,
179 struct ttm_placement *placement)
181 static struct ttm_place placements = {
184 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
187 struct radeon_bo *rbo;
189 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
190 placement->placement = &placements;
191 placement->busy_placement = &placements;
192 placement->num_placement = 1;
193 placement->num_busy_placement = 1;
196 rbo = container_of(bo, struct radeon_bo, tbo);
197 switch (bo->mem.mem_type) {
199 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
200 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
202 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
206 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
208 *placement = rbo->placement;
211 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
213 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
215 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
218 static void radeon_move_null(struct ttm_buffer_object *bo,
219 struct ttm_mem_reg *new_mem)
221 struct ttm_mem_reg *old_mem = &bo->mem;
223 BUG_ON(old_mem->mm_node != NULL);
225 new_mem->mm_node = NULL;
228 static int radeon_move_blit(struct ttm_buffer_object *bo,
229 bool evict, bool no_wait_gpu,
230 struct ttm_mem_reg *new_mem,
231 struct ttm_mem_reg *old_mem)
233 struct radeon_device *rdev;
234 uint64_t old_start, new_start;
235 struct radeon_fence *fence;
239 rdev = radeon_get_rdev(bo->bdev);
240 ridx = radeon_copy_ring_index(rdev);
241 old_start = old_mem->start << PAGE_SHIFT;
242 new_start = new_mem->start << PAGE_SHIFT;
244 switch (old_mem->mem_type) {
246 old_start += rdev->mc.vram_start;
249 old_start += rdev->mc.gtt_start;
252 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
255 switch (new_mem->mem_type) {
257 new_start += rdev->mc.vram_start;
260 new_start += rdev->mc.gtt_start;
263 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
266 if (!rdev->ring[ridx].ready) {
267 DRM_ERROR("Trying to move memory with ring turned off.\n");
271 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
273 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
274 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
276 return PTR_ERR(fence);
278 r = ttm_bo_move_accel_cleanup(bo, &fence->base,
279 evict, no_wait_gpu, new_mem);
280 radeon_fence_unref(&fence);
284 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
285 bool evict, bool interruptible,
287 struct ttm_mem_reg *new_mem)
289 struct radeon_device *rdev;
290 struct ttm_mem_reg *old_mem = &bo->mem;
291 struct ttm_mem_reg tmp_mem;
292 struct ttm_place placements;
293 struct ttm_placement placement;
296 rdev = radeon_get_rdev(bo->bdev);
298 tmp_mem.mm_node = NULL;
299 placement.num_placement = 1;
300 placement.placement = &placements;
301 placement.num_busy_placement = 1;
302 placement.busy_placement = &placements;
305 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
306 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
307 interruptible, no_wait_gpu);
312 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
317 r = ttm_tt_bind(bo->ttm, &tmp_mem);
321 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
325 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
327 ttm_bo_mem_put(bo, &tmp_mem);
331 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
332 bool evict, bool interruptible,
334 struct ttm_mem_reg *new_mem)
336 struct radeon_device *rdev;
337 struct ttm_mem_reg *old_mem = &bo->mem;
338 struct ttm_mem_reg tmp_mem;
339 struct ttm_placement placement;
340 struct ttm_place placements;
343 rdev = radeon_get_rdev(bo->bdev);
345 tmp_mem.mm_node = NULL;
346 placement.num_placement = 1;
347 placement.placement = &placements;
348 placement.num_busy_placement = 1;
349 placement.busy_placement = &placements;
352 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
353 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
354 interruptible, no_wait_gpu);
358 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
362 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
367 ttm_bo_mem_put(bo, &tmp_mem);
371 static int radeon_bo_move(struct ttm_buffer_object *bo,
372 bool evict, bool interruptible,
374 struct ttm_mem_reg *new_mem)
376 struct radeon_device *rdev;
377 struct ttm_mem_reg *old_mem = &bo->mem;
380 rdev = radeon_get_rdev(bo->bdev);
381 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
382 radeon_move_null(bo, new_mem);
385 if ((old_mem->mem_type == TTM_PL_TT &&
386 new_mem->mem_type == TTM_PL_SYSTEM) ||
387 (old_mem->mem_type == TTM_PL_SYSTEM &&
388 new_mem->mem_type == TTM_PL_TT)) {
390 radeon_move_null(bo, new_mem);
393 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
394 rdev->asic->copy.copy == NULL) {
399 if (old_mem->mem_type == TTM_PL_VRAM &&
400 new_mem->mem_type == TTM_PL_SYSTEM) {
401 r = radeon_move_vram_ram(bo, evict, interruptible,
402 no_wait_gpu, new_mem);
403 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
404 new_mem->mem_type == TTM_PL_VRAM) {
405 r = radeon_move_ram_vram(bo, evict, interruptible,
406 no_wait_gpu, new_mem);
408 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
413 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
419 /* update statistics */
420 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
424 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
426 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
427 struct radeon_device *rdev = radeon_get_rdev(bdev);
429 mem->bus.addr = NULL;
431 mem->bus.size = mem->num_pages << PAGE_SHIFT;
433 mem->bus.is_iomem = false;
434 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
436 switch (mem->mem_type) {
442 if (rdev->flags & RADEON_IS_AGP) {
443 /* RADEON_IS_AGP is set only if AGP is active */
444 mem->bus.offset = mem->start << PAGE_SHIFT;
445 mem->bus.base = rdev->mc.agp_base;
446 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
451 mem->bus.offset = mem->start << PAGE_SHIFT;
452 /* check if it's visible */
453 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
455 mem->bus.base = rdev->mc.aper_base;
456 mem->bus.is_iomem = true;
459 * Alpha: use bus.addr to hold the ioremap() return,
460 * so we can modify bus.base below.
462 if (mem->placement & TTM_PL_FLAG_WC)
464 ioremap_wc(mem->bus.base + mem->bus.offset,
468 ioremap_nocache(mem->bus.base + mem->bus.offset,
472 * Alpha: Use just the bus offset plus
473 * the hose/domain memory base for bus.base.
474 * It then can be used to build PTEs for VRAM
475 * access, as done in ttm_bo_vm_fault().
477 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
478 rdev->ddev->hose->dense_mem_base;
487 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
492 * TTM backend functions.
494 struct radeon_ttm_tt {
495 struct ttm_dma_tt ttm;
496 struct radeon_device *rdev;
500 struct mm_struct *usermm;
504 /* prepare the sg table with the user pages */
505 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
507 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
508 struct radeon_ttm_tt *gtt = (void *)ttm;
509 unsigned pinned = 0, nents;
512 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
513 enum dma_data_direction direction = write ?
514 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
516 if (current->mm != gtt->usermm)
519 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
520 /* check that we only pin down anonymous memory
521 to prevent problems with writeback */
522 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
523 struct vm_area_struct *vma;
524 vma = find_vma(gtt->usermm, gtt->userptr);
525 if (!vma || vma->vm_file || vma->vm_end < end)
530 unsigned num_pages = ttm->num_pages - pinned;
531 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
532 struct page **pages = ttm->pages + pinned;
534 r = get_user_pages(current, current->mm, userptr, num_pages,
535 write, 0, pages, NULL);
541 } while (pinned < ttm->num_pages);
543 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
544 ttm->num_pages << PAGE_SHIFT,
550 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
551 if (nents != ttm->sg->nents)
554 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
555 gtt->ttm.dma_address, ttm->num_pages);
563 release_pages(ttm->pages, pinned, 0);
567 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
569 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
570 struct radeon_ttm_tt *gtt = (void *)ttm;
571 struct scatterlist *sg;
574 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
575 enum dma_data_direction direction = write ?
576 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
578 /* free the sg table and pages again */
579 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
581 for_each_sg(ttm->sg->sgl, sg, ttm->sg->nents, i) {
582 struct page *page = sg_page(sg);
584 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
585 set_page_dirty(page);
587 mark_page_accessed(page);
588 page_cache_release(page);
591 sg_free_table(ttm->sg);
594 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
595 struct ttm_mem_reg *bo_mem)
597 struct radeon_ttm_tt *gtt = (void*)ttm;
598 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
599 RADEON_GART_PAGE_WRITE;
603 radeon_ttm_tt_pin_userptr(ttm);
604 flags &= ~RADEON_GART_PAGE_WRITE;
607 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
608 if (!ttm->num_pages) {
609 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
610 ttm->num_pages, bo_mem, ttm);
612 if (ttm->caching_state == tt_cached)
613 flags |= RADEON_GART_PAGE_SNOOP;
614 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
615 ttm->pages, gtt->ttm.dma_address, flags);
617 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
618 ttm->num_pages, (unsigned)gtt->offset);
624 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
626 struct radeon_ttm_tt *gtt = (void *)ttm;
628 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
631 radeon_ttm_tt_unpin_userptr(ttm);
636 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
638 struct radeon_ttm_tt *gtt = (void *)ttm;
640 ttm_dma_tt_fini(>t->ttm);
644 static struct ttm_backend_func radeon_backend_func = {
645 .bind = &radeon_ttm_backend_bind,
646 .unbind = &radeon_ttm_backend_unbind,
647 .destroy = &radeon_ttm_backend_destroy,
650 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
651 unsigned long size, uint32_t page_flags,
652 struct page *dummy_read_page)
654 struct radeon_device *rdev;
655 struct radeon_ttm_tt *gtt;
657 rdev = radeon_get_rdev(bdev);
659 if (rdev->flags & RADEON_IS_AGP) {
660 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
661 size, page_flags, dummy_read_page);
665 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
669 gtt->ttm.ttm.func = &radeon_backend_func;
671 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
675 return >t->ttm.ttm;
678 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
680 if (!ttm || ttm->func != &radeon_backend_func)
682 return (struct radeon_ttm_tt *)ttm;
685 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
687 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
688 struct radeon_device *rdev;
691 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
693 if (ttm->state != tt_unpopulated)
696 if (gtt && gtt->userptr) {
697 ttm->sg = kcalloc(1, sizeof(struct sg_table), GFP_KERNEL);
701 ttm->page_flags |= TTM_PAGE_FLAG_SG;
702 ttm->state = tt_unbound;
706 if (slave && ttm->sg) {
707 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
708 gtt->ttm.dma_address, ttm->num_pages);
709 ttm->state = tt_unbound;
713 rdev = radeon_get_rdev(ttm->bdev);
715 if (rdev->flags & RADEON_IS_AGP) {
716 return ttm_agp_tt_populate(ttm);
720 #ifdef CONFIG_SWIOTLB
721 if (swiotlb_nr_tbl()) {
722 return ttm_dma_populate(>t->ttm, rdev->dev);
726 r = ttm_pool_populate(ttm);
731 for (i = 0; i < ttm->num_pages; i++) {
732 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
734 PCI_DMA_BIDIRECTIONAL);
735 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
737 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
738 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
739 gtt->ttm.dma_address[i] = 0;
741 ttm_pool_unpopulate(ttm);
748 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
750 struct radeon_device *rdev;
751 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
753 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
755 if (gtt && gtt->userptr) {
757 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
764 rdev = radeon_get_rdev(ttm->bdev);
766 if (rdev->flags & RADEON_IS_AGP) {
767 ttm_agp_tt_unpopulate(ttm);
772 #ifdef CONFIG_SWIOTLB
773 if (swiotlb_nr_tbl()) {
774 ttm_dma_unpopulate(>t->ttm, rdev->dev);
779 for (i = 0; i < ttm->num_pages; i++) {
780 if (gtt->ttm.dma_address[i]) {
781 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
782 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
786 ttm_pool_unpopulate(ttm);
789 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
792 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
798 gtt->usermm = current->mm;
799 gtt->userflags = flags;
803 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
805 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
810 return !!gtt->userptr;
813 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
815 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
820 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
823 static struct ttm_bo_driver radeon_bo_driver = {
824 .ttm_tt_create = &radeon_ttm_tt_create,
825 .ttm_tt_populate = &radeon_ttm_tt_populate,
826 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
827 .invalidate_caches = &radeon_invalidate_caches,
828 .init_mem_type = &radeon_init_mem_type,
829 .evict_flags = &radeon_evict_flags,
830 .move = &radeon_bo_move,
831 .verify_access = &radeon_verify_access,
832 .move_notify = &radeon_bo_move_notify,
833 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
834 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
835 .io_mem_free = &radeon_ttm_io_mem_free,
838 int radeon_ttm_init(struct radeon_device *rdev)
842 r = radeon_ttm_global_init(rdev);
846 /* No others user of address space so set it to 0 */
847 r = ttm_bo_device_init(&rdev->mman.bdev,
848 rdev->mman.bo_global_ref.ref.object,
850 rdev->ddev->anon_inode->i_mapping,
851 DRM_FILE_PAGE_OFFSET,
854 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
857 rdev->mman.initialized = true;
858 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
859 rdev->mc.real_vram_size >> PAGE_SHIFT);
861 DRM_ERROR("Failed initializing VRAM heap.\n");
864 /* Change the size here instead of the init above so only lpfn is affected */
865 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
867 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
868 RADEON_GEM_DOMAIN_VRAM, 0,
869 NULL, &rdev->stollen_vga_memory);
873 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
876 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
877 radeon_bo_unreserve(rdev->stollen_vga_memory);
879 radeon_bo_unref(&rdev->stollen_vga_memory);
882 DRM_INFO("radeon: %uM of VRAM memory ready\n",
883 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
884 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
885 rdev->mc.gtt_size >> PAGE_SHIFT);
887 DRM_ERROR("Failed initializing GTT heap.\n");
890 DRM_INFO("radeon: %uM of GTT memory ready.\n",
891 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
893 r = radeon_ttm_debugfs_init(rdev);
895 DRM_ERROR("Failed to init debugfs\n");
901 void radeon_ttm_fini(struct radeon_device *rdev)
905 if (!rdev->mman.initialized)
907 radeon_ttm_debugfs_fini(rdev);
908 if (rdev->stollen_vga_memory) {
909 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
911 radeon_bo_unpin(rdev->stollen_vga_memory);
912 radeon_bo_unreserve(rdev->stollen_vga_memory);
914 radeon_bo_unref(&rdev->stollen_vga_memory);
916 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
917 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
918 ttm_bo_device_release(&rdev->mman.bdev);
919 radeon_gart_fini(rdev);
920 radeon_ttm_global_fini(rdev);
921 rdev->mman.initialized = false;
922 DRM_INFO("radeon: ttm finalized\n");
925 /* this should only be called at bootup or when userspace
927 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
929 struct ttm_mem_type_manager *man;
931 if (!rdev->mman.initialized)
934 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
935 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
936 man->size = size >> PAGE_SHIFT;
939 static struct vm_operations_struct radeon_ttm_vm_ops;
940 static const struct vm_operations_struct *ttm_vm_ops = NULL;
942 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
944 struct ttm_buffer_object *bo;
945 struct radeon_device *rdev;
948 bo = (struct ttm_buffer_object *)vma->vm_private_data;
950 return VM_FAULT_NOPAGE;
952 rdev = radeon_get_rdev(bo->bdev);
953 down_read(&rdev->pm.mclk_lock);
954 r = ttm_vm_ops->fault(vma, vmf);
955 up_read(&rdev->pm.mclk_lock);
959 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
961 struct drm_file *file_priv;
962 struct radeon_device *rdev;
965 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
969 file_priv = filp->private_data;
970 rdev = file_priv->minor->dev->dev_private;
974 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
975 if (unlikely(r != 0)) {
978 if (unlikely(ttm_vm_ops == NULL)) {
979 ttm_vm_ops = vma->vm_ops;
980 radeon_ttm_vm_ops = *ttm_vm_ops;
981 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
983 vma->vm_ops = &radeon_ttm_vm_ops;
987 #if defined(CONFIG_DEBUG_FS)
989 static int radeon_mm_dump_table(struct seq_file *m, void *data)
991 struct drm_info_node *node = (struct drm_info_node *)m->private;
992 unsigned ttm_pl = *(int *)node->info_ent->data;
993 struct drm_device *dev = node->minor->dev;
994 struct radeon_device *rdev = dev->dev_private;
995 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv;
997 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
999 spin_lock(&glob->lru_lock);
1000 ret = drm_mm_dump_table(m, mm);
1001 spin_unlock(&glob->lru_lock);
1005 static int ttm_pl_vram = TTM_PL_VRAM;
1006 static int ttm_pl_tt = TTM_PL_TT;
1008 static struct drm_info_list radeon_ttm_debugfs_list[] = {
1009 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1010 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1011 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1012 #ifdef CONFIG_SWIOTLB
1013 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1017 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1019 struct radeon_device *rdev = inode->i_private;
1020 i_size_write(inode, rdev->mc.mc_vram_size);
1021 filep->private_data = inode->i_private;
1025 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1026 size_t size, loff_t *pos)
1028 struct radeon_device *rdev = f->private_data;
1032 if (size & 0x3 || *pos & 0x3)
1036 unsigned long flags;
1039 if (*pos >= rdev->mc.mc_vram_size)
1042 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1043 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1044 if (rdev->family >= CHIP_CEDAR)
1045 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1046 value = RREG32(RADEON_MM_DATA);
1047 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1049 r = put_user(value, (uint32_t *)buf);
1062 static const struct file_operations radeon_ttm_vram_fops = {
1063 .owner = THIS_MODULE,
1064 .open = radeon_ttm_vram_open,
1065 .read = radeon_ttm_vram_read,
1066 .llseek = default_llseek
1069 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1071 struct radeon_device *rdev = inode->i_private;
1072 i_size_write(inode, rdev->mc.gtt_size);
1073 filep->private_data = inode->i_private;
1077 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1078 size_t size, loff_t *pos)
1080 struct radeon_device *rdev = f->private_data;
1085 loff_t p = *pos / PAGE_SIZE;
1086 unsigned off = *pos & ~PAGE_MASK;
1087 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1091 if (p >= rdev->gart.num_cpu_pages)
1094 page = rdev->gart.pages[p];
1099 r = copy_to_user(buf, ptr, cur_size);
1100 kunmap(rdev->gart.pages[p]);
1102 r = clear_user(buf, cur_size);
1116 static const struct file_operations radeon_ttm_gtt_fops = {
1117 .owner = THIS_MODULE,
1118 .open = radeon_ttm_gtt_open,
1119 .read = radeon_ttm_gtt_read,
1120 .llseek = default_llseek
1125 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1127 #if defined(CONFIG_DEBUG_FS)
1130 struct drm_minor *minor = rdev->ddev->primary;
1131 struct dentry *ent, *root = minor->debugfs_root;
1133 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1134 rdev, &radeon_ttm_vram_fops);
1136 return PTR_ERR(ent);
1137 rdev->mman.vram = ent;
1139 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1140 rdev, &radeon_ttm_gtt_fops);
1142 return PTR_ERR(ent);
1143 rdev->mman.gtt = ent;
1145 count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1147 #ifdef CONFIG_SWIOTLB
1148 if (!swiotlb_nr_tbl())
1152 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1159 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1161 #if defined(CONFIG_DEBUG_FS)
1163 debugfs_remove(rdev->mman.vram);
1164 rdev->mman.vram = NULL;
1166 debugfs_remove(rdev->mman.gtt);
1167 rdev->mman.gtt = NULL;