2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
39 /* 1 second timeout */
40 #define UVD_IDLE_TIMEOUT_MS 1000
43 #define FIRMWARE_R600 "radeon/R600_uvd.bin"
44 #define FIRMWARE_RS780 "radeon/RS780_uvd.bin"
45 #define FIRMWARE_RV770 "radeon/RV770_uvd.bin"
46 #define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
47 #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
48 #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin"
49 #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin"
50 #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin"
52 MODULE_FIRMWARE(FIRMWARE_R600);
53 MODULE_FIRMWARE(FIRMWARE_RS780);
54 MODULE_FIRMWARE(FIRMWARE_RV770);
55 MODULE_FIRMWARE(FIRMWARE_RV710);
56 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
57 MODULE_FIRMWARE(FIRMWARE_SUMO);
58 MODULE_FIRMWARE(FIRMWARE_TAHITI);
59 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
61 static void radeon_uvd_idle_work_handler(struct work_struct *work);
63 int radeon_uvd_init(struct radeon_device *rdev)
65 unsigned long bo_size;
69 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
71 switch (rdev->family) {
77 fw_name = FIRMWARE_R600;
82 fw_name = FIRMWARE_RS780;
86 fw_name = FIRMWARE_RV770;
92 fw_name = FIRMWARE_RV710;
100 fw_name = FIRMWARE_CYPRESS;
110 fw_name = FIRMWARE_SUMO;
118 fw_name = FIRMWARE_TAHITI;
126 fw_name = FIRMWARE_BONAIRE;
133 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
135 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
140 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
141 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
142 RADEON_GPU_PAGE_SIZE;
143 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
144 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
145 NULL, &rdev->uvd.vcpu_bo);
147 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
151 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
153 radeon_bo_unref(&rdev->uvd.vcpu_bo);
154 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
158 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
159 &rdev->uvd.gpu_addr);
161 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
162 radeon_bo_unref(&rdev->uvd.vcpu_bo);
163 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
167 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
169 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
173 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
175 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
176 atomic_set(&rdev->uvd.handles[i], 0);
177 rdev->uvd.filp[i] = NULL;
178 rdev->uvd.img_size[i] = 0;
184 void radeon_uvd_fini(struct radeon_device *rdev)
188 if (rdev->uvd.vcpu_bo == NULL)
191 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
193 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
194 radeon_bo_unpin(rdev->uvd.vcpu_bo);
195 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
198 radeon_bo_unref(&rdev->uvd.vcpu_bo);
200 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
202 release_firmware(rdev->uvd_fw);
205 int radeon_uvd_suspend(struct radeon_device *rdev)
211 if (rdev->uvd.vcpu_bo == NULL)
214 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
215 if (atomic_read(&rdev->uvd.handles[i]))
218 if (i == RADEON_MAX_UVD_HANDLES)
221 size = radeon_bo_size(rdev->uvd.vcpu_bo);
222 size -= rdev->uvd_fw->size;
224 ptr = rdev->uvd.cpu_addr;
225 ptr += rdev->uvd_fw->size;
227 rdev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
228 memcpy(rdev->uvd.saved_bo, ptr, size);
233 int radeon_uvd_resume(struct radeon_device *rdev)
238 if (rdev->uvd.vcpu_bo == NULL)
241 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
243 size = radeon_bo_size(rdev->uvd.vcpu_bo);
244 size -= rdev->uvd_fw->size;
246 ptr = rdev->uvd.cpu_addr;
247 ptr += rdev->uvd_fw->size;
249 if (rdev->uvd.saved_bo != NULL) {
250 memcpy(ptr, rdev->uvd.saved_bo, size);
251 kfree(rdev->uvd.saved_bo);
252 rdev->uvd.saved_bo = NULL;
254 memset(ptr, 0, size);
259 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
260 uint32_t allowed_domains)
264 for (i = 0; i < rbo->placement.num_placement; ++i) {
265 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
266 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
269 /* If it must be in VRAM it must be in the first segment as well */
270 if (allowed_domains == RADEON_GEM_DOMAIN_VRAM)
273 /* abort if we already have more than one placement */
274 if (rbo->placement.num_placement > 1)
277 /* add another 256MB segment */
278 rbo->placements[1] = rbo->placements[0];
279 rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
280 rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT;
281 rbo->placement.num_placement++;
282 rbo->placement.num_busy_placement++;
285 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
288 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
289 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
290 if (handle != 0 && rdev->uvd.filp[i] == filp) {
291 struct radeon_fence *fence;
293 radeon_uvd_note_usage(rdev);
295 r = radeon_uvd_get_destroy_msg(rdev,
296 R600_RING_TYPE_UVD_INDEX, handle, &fence);
298 DRM_ERROR("Error destroying UVD (%d)!\n", r);
302 radeon_fence_wait(fence, false);
303 radeon_fence_unref(&fence);
305 rdev->uvd.filp[i] = NULL;
306 atomic_set(&rdev->uvd.handles[i], 0);
311 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
313 unsigned stream_type = msg[4];
314 unsigned width = msg[6];
315 unsigned height = msg[7];
316 unsigned dpb_size = msg[9];
317 unsigned pitch = msg[28];
319 unsigned width_in_mb = width / 16;
320 unsigned height_in_mb = ALIGN(height / 16, 2);
322 unsigned image_size, tmp, min_dpb_size;
324 image_size = width * height;
325 image_size += image_size / 2;
326 image_size = ALIGN(image_size, 1024);
328 switch (stream_type) {
331 /* reference picture buffer */
332 min_dpb_size = image_size * 17;
334 /* macroblock context buffer */
335 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
337 /* IT surface buffer */
338 min_dpb_size += width_in_mb * height_in_mb * 32;
343 /* reference picture buffer */
344 min_dpb_size = image_size * 3;
347 min_dpb_size += width_in_mb * height_in_mb * 128;
349 /* IT surface buffer */
350 min_dpb_size += width_in_mb * 64;
352 /* DB surface buffer */
353 min_dpb_size += width_in_mb * 128;
356 tmp = max(width_in_mb, height_in_mb);
357 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
362 /* reference picture buffer */
363 min_dpb_size = image_size * 3;
368 /* reference picture buffer */
369 min_dpb_size = image_size * 3;
372 min_dpb_size += width_in_mb * height_in_mb * 64;
374 /* IT surface buffer */
375 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
379 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
384 DRM_ERROR("Invalid UVD decoding target pitch!\n");
388 if (dpb_size < min_dpb_size) {
389 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
390 dpb_size, min_dpb_size);
394 buf_sizes[0x1] = dpb_size;
395 buf_sizes[0x2] = image_size;
399 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
400 unsigned offset, unsigned buf_sizes[])
402 int32_t *msg, msg_type, handle;
403 unsigned img_size = 0;
410 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
414 f = reservation_object_get_excl(bo->tbo.resv);
416 r = radeon_fence_wait((struct radeon_fence *)f, false);
418 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
423 r = radeon_bo_kmap(bo, &ptr);
425 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
435 DRM_ERROR("Invalid UVD handle!\n");
440 /* it's a decode msg, calc buffer sizes */
441 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
442 /* calc image size (width * height) */
443 img_size = msg[6] * msg[7];
444 radeon_bo_kunmap(bo);
448 } else if (msg_type == 2) {
449 /* it's a destroy msg, free the handle */
450 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
451 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0);
452 radeon_bo_kunmap(bo);
455 /* it's a create msg, calc image size (width * height) */
456 img_size = msg[7] * msg[8];
457 radeon_bo_kunmap(bo);
460 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
464 /* it's a create msg, no special handling needed */
467 /* create or decode, validate the handle */
468 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
469 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
473 /* handle not found try to alloc a new one */
474 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
475 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
476 p->rdev->uvd.filp[i] = p->filp;
477 p->rdev->uvd.img_size[i] = img_size;
482 DRM_ERROR("No more free UVD handles!\n");
486 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
487 int data0, int data1,
488 unsigned buf_sizes[], bool *has_msg_cmd)
490 struct radeon_cs_chunk *relocs_chunk;
491 struct radeon_bo_list *reloc;
492 unsigned idx, cmd, offset;
496 relocs_chunk = p->chunk_relocs;
497 offset = radeon_get_ib_value(p, data0);
498 idx = radeon_get_ib_value(p, data1);
499 if (idx >= relocs_chunk->length_dw) {
500 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
501 idx, relocs_chunk->length_dw);
505 reloc = &p->relocs[(idx / 4)];
506 start = reloc->gpu_offset;
507 end = start + radeon_bo_size(reloc->robj);
510 p->ib.ptr[data0] = start & 0xFFFFFFFF;
511 p->ib.ptr[data1] = start >> 32;
513 cmd = radeon_get_ib_value(p, p->idx) >> 1;
517 DRM_ERROR("invalid reloc offset %X!\n", offset);
520 if ((end - start) < buf_sizes[cmd]) {
521 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
522 (unsigned)(end - start), buf_sizes[cmd]);
526 } else if (cmd != 0x100) {
527 DRM_ERROR("invalid UVD command %X!\n", cmd);
531 if ((start >> 28) != ((end - 1) >> 28)) {
532 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
537 /* TODO: is this still necessary on NI+ ? */
538 if ((cmd == 0 || cmd == 0x3) &&
539 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
540 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
547 DRM_ERROR("More than one message in a UVD-IB!\n");
551 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
554 } else if (!*has_msg_cmd) {
555 DRM_ERROR("Message needed before other commands are send!\n");
562 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
563 struct radeon_cs_packet *pkt,
564 int *data0, int *data1,
565 unsigned buf_sizes[],
571 for (i = 0; i <= pkt->count; ++i) {
572 switch (pkt->reg + i*4) {
573 case UVD_GPCOM_VCPU_DATA0:
576 case UVD_GPCOM_VCPU_DATA1:
579 case UVD_GPCOM_VCPU_CMD:
580 r = radeon_uvd_cs_reloc(p, *data0, *data1,
581 buf_sizes, has_msg_cmd);
585 case UVD_ENGINE_CNTL:
588 DRM_ERROR("Invalid reg 0x%X!\n",
597 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
599 struct radeon_cs_packet pkt;
600 int r, data0 = 0, data1 = 0;
602 /* does the IB has a msg command */
603 bool has_msg_cmd = false;
605 /* minimum buffer sizes */
606 unsigned buf_sizes[] = {
608 [0x00000001] = 32 * 1024 * 1024,
609 [0x00000002] = 2048 * 1152 * 3,
613 if (p->chunk_ib->length_dw % 16) {
614 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
615 p->chunk_ib->length_dw);
619 if (p->chunk_relocs == NULL) {
620 DRM_ERROR("No relocation chunk !\n");
626 r = radeon_cs_packet_parse(p, &pkt, p->idx);
630 case RADEON_PACKET_TYPE0:
631 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
632 buf_sizes, &has_msg_cmd);
636 case RADEON_PACKET_TYPE2:
637 p->idx += pkt.count + 2;
640 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
643 } while (p->idx < p->chunk_ib->length_dw);
646 DRM_ERROR("UVD-IBs need a msg command!\n");
653 static int radeon_uvd_send_msg(struct radeon_device *rdev,
654 int ring, uint64_t addr,
655 struct radeon_fence **fence)
660 r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
664 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
666 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
667 ib.ptr[3] = addr >> 32;
668 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
670 for (i = 6; i < 16; ++i)
671 ib.ptr[i] = PACKET2(0);
674 r = radeon_ib_schedule(rdev, &ib, NULL, false);
677 *fence = radeon_fence_ref(ib.fence);
679 radeon_ib_free(rdev, &ib);
683 /* multiple fence commands without any stream commands in between can
684 crash the vcpu so just try to emmit a dummy create/destroy msg to
686 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
687 uint32_t handle, struct radeon_fence **fence)
689 /* we use the last page of the vcpu bo for the UVD message */
690 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
691 RADEON_GPU_PAGE_SIZE;
693 uint32_t *msg = rdev->uvd.cpu_addr + offs;
694 uint64_t addr = rdev->uvd.gpu_addr + offs;
698 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
702 /* stitch together an UVD create msg */
703 msg[0] = cpu_to_le32(0x00000de4);
704 msg[1] = cpu_to_le32(0x00000000);
705 msg[2] = cpu_to_le32(handle);
706 msg[3] = cpu_to_le32(0x00000000);
707 msg[4] = cpu_to_le32(0x00000000);
708 msg[5] = cpu_to_le32(0x00000000);
709 msg[6] = cpu_to_le32(0x00000000);
710 msg[7] = cpu_to_le32(0x00000780);
711 msg[8] = cpu_to_le32(0x00000440);
712 msg[9] = cpu_to_le32(0x00000000);
713 msg[10] = cpu_to_le32(0x01b37000);
714 for (i = 11; i < 1024; ++i)
715 msg[i] = cpu_to_le32(0x0);
717 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
718 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
722 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
723 uint32_t handle, struct radeon_fence **fence)
725 /* we use the last page of the vcpu bo for the UVD message */
726 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
727 RADEON_GPU_PAGE_SIZE;
729 uint32_t *msg = rdev->uvd.cpu_addr + offs;
730 uint64_t addr = rdev->uvd.gpu_addr + offs;
734 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
738 /* stitch together an UVD destroy msg */
739 msg[0] = cpu_to_le32(0x00000de4);
740 msg[1] = cpu_to_le32(0x00000002);
741 msg[2] = cpu_to_le32(handle);
742 msg[3] = cpu_to_le32(0x00000000);
743 for (i = 4; i < 1024; ++i)
744 msg[i] = cpu_to_le32(0x0);
746 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
747 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
752 * radeon_uvd_count_handles - count number of open streams
754 * @rdev: radeon_device pointer
755 * @sd: number of SD streams
756 * @hd: number of HD streams
758 * Count the number of open SD/HD streams as a hint for power mangement
760 static void radeon_uvd_count_handles(struct radeon_device *rdev,
761 unsigned *sd, unsigned *hd)
768 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
769 if (!atomic_read(&rdev->uvd.handles[i]))
772 if (rdev->uvd.img_size[i] >= 720*576)
779 static void radeon_uvd_idle_work_handler(struct work_struct *work)
781 struct radeon_device *rdev =
782 container_of(work, struct radeon_device, uvd.idle_work.work);
784 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
785 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
786 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
788 radeon_dpm_enable_uvd(rdev, false);
790 radeon_set_uvd_clocks(rdev, 0, 0);
793 schedule_delayed_work(&rdev->uvd.idle_work,
794 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
798 void radeon_uvd_note_usage(struct radeon_device *rdev)
800 bool streams_changed = false;
801 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
802 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
803 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
805 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
806 unsigned hd = 0, sd = 0;
807 radeon_uvd_count_handles(rdev, &sd, &hd);
808 if ((rdev->pm.dpm.sd != sd) ||
809 (rdev->pm.dpm.hd != hd)) {
810 rdev->pm.dpm.sd = sd;
811 rdev->pm.dpm.hd = hd;
812 /* disable this for now */
813 /*streams_changed = true;*/
817 if (set_clocks || streams_changed) {
818 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
819 radeon_dpm_enable_uvd(rdev, true);
821 radeon_set_uvd_clocks(rdev, 53300, 40000);
826 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
827 unsigned target_freq,
831 unsigned post_div = vco_freq / target_freq;
833 /* adjust to post divider minimum value */
834 if (post_div < pd_min)
837 /* we alway need a frequency less than or equal the target */
838 if ((vco_freq / post_div) > target_freq)
841 /* post dividers above a certain value must be even */
842 if (post_div > pd_even && post_div % 2)
849 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
851 * @rdev: radeon_device pointer
854 * @vco_min: minimum VCO frequency
855 * @vco_max: maximum VCO frequency
856 * @fb_factor: factor to multiply vco freq with
857 * @fb_mask: limit and bitmask for feedback divider
858 * @pd_min: post divider minimum
859 * @pd_max: post divider maximum
860 * @pd_even: post divider must be even above this value
861 * @optimal_fb_div: resulting feedback divider
862 * @optimal_vclk_div: resulting vclk post divider
863 * @optimal_dclk_div: resulting dclk post divider
865 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
866 * Returns zero on success -EINVAL on error.
868 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
869 unsigned vclk, unsigned dclk,
870 unsigned vco_min, unsigned vco_max,
871 unsigned fb_factor, unsigned fb_mask,
872 unsigned pd_min, unsigned pd_max,
874 unsigned *optimal_fb_div,
875 unsigned *optimal_vclk_div,
876 unsigned *optimal_dclk_div)
878 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
880 /* start off with something large */
881 unsigned optimal_score = ~0;
883 /* loop through vco from low to high */
884 vco_min = max(max(vco_min, vclk), dclk);
885 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
887 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
888 unsigned vclk_div, dclk_div, score;
890 do_div(fb_div, ref_freq);
892 /* fb div out of range ? */
893 if (fb_div > fb_mask)
894 break; /* it can oly get worse */
898 /* calc vclk divider with current vco freq */
899 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
901 if (vclk_div > pd_max)
902 break; /* vco is too big, it has to stop */
904 /* calc dclk divider with current vco freq */
905 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
907 if (vclk_div > pd_max)
908 break; /* vco is too big, it has to stop */
910 /* calc score with current vco freq */
911 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
913 /* determine if this vco setting is better than current optimal settings */
914 if (score < optimal_score) {
915 *optimal_fb_div = fb_div;
916 *optimal_vclk_div = vclk_div;
917 *optimal_dclk_div = dclk_div;
918 optimal_score = score;
919 if (optimal_score == 0)
920 break; /* it can't get better than this */
924 /* did we found a valid setup ? */
925 if (optimal_score == ~0)
931 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
932 unsigned cg_upll_func_cntl)
936 /* make sure UPLL_CTLREQ is deasserted */
937 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
941 /* assert UPLL_CTLREQ */
942 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
944 /* wait for CTLACK and CTLACK2 to get asserted */
945 for (i = 0; i < 100; ++i) {
946 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
947 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
952 /* deassert UPLL_CTLREQ */
953 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
956 DRM_ERROR("Timeout setting UVD clocks!\n");