2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
26 #include "radeon_asic.h"
30 * rv770_copy_dma - copy pages using the DMA engine
32 * @rdev: radeon_device pointer
33 * @src_offset: src GPU address
34 * @dst_offset: dst GPU address
35 * @num_gpu_pages: number of GPU pages to xfer
36 * @resv: reservation object to sync to
38 * Copy GPU paging using the DMA engine (r7xx).
39 * Used by the radeon ttm implementation to move pages if
40 * registered as the asic copy callback.
42 struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
43 uint64_t src_offset, uint64_t dst_offset,
44 unsigned num_gpu_pages,
45 struct reservation_object *resv)
47 struct radeon_semaphore *sem = NULL;
48 struct radeon_fence *fence;
49 int ring_index = rdev->asic->copy.dma_ring_index;
50 struct radeon_ring *ring = &rdev->ring[ring_index];
51 u32 size_in_dw, cur_size_in_dw;
55 r = radeon_semaphore_create(rdev, &sem);
57 DRM_ERROR("radeon: moving bo (%d).\n", r);
61 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
62 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
63 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
65 DRM_ERROR("radeon: moving bo (%d).\n", r);
66 radeon_semaphore_free(rdev, &sem, NULL);
70 radeon_semaphore_sync_resv(rdev, sem, resv, false);
71 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
73 for (i = 0; i < num_loops; i++) {
74 cur_size_in_dw = size_in_dw;
75 if (cur_size_in_dw > 0xFFFF)
76 cur_size_in_dw = 0xFFFF;
77 size_in_dw -= cur_size_in_dw;
78 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
79 radeon_ring_write(ring, dst_offset & 0xfffffffc);
80 radeon_ring_write(ring, src_offset & 0xfffffffc);
81 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
82 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
83 src_offset += cur_size_in_dw * 4;
84 dst_offset += cur_size_in_dw * 4;
87 r = radeon_fence_emit(rdev, &fence, ring->idx);
89 radeon_ring_unlock_undo(rdev, ring);
90 radeon_semaphore_free(rdev, &sem, NULL);
94 radeon_ring_unlock_commit(rdev, ring, false);
95 radeon_semaphore_free(rdev, &sem, fence);