drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_flip_work.h>
  21 #include <drm/drm_plane_helper.h>
  22 #ifdef CONFIG_DRM_ANALOGIX_DP
  23 #include <drm/bridge/analogix_dp.h>
  24 #endif
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <linux/iopoll.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/component.h>
  35
  36 #include <linux/reset.h>
  37 #include <linux/delay.h>
  38
  39 #include "rockchip_drm_drv.h"
  40 #include "rockchip_drm_gem.h"
  41 #include "rockchip_drm_fb.h"
  42 #include "rockchip_drm_psr.h"
  43 #include "rockchip_drm_vop.h"
  44
  45 #define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \
  46                 vop_mask_write(x, off, mask, shift, v, write_mask, true)
  47
  48 #define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \
  49                 vop_mask_write(x, off, mask, shift, v, write_mask, false)
  50
  51 #define REG_SET(x, base, reg, v, mode) \
  52                 __REG_SET_##mode(x, base + reg.offset, \
  53                                  reg.mask, reg.shift, v, reg.write_mask)
  54 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
  55                 __REG_SET_##mode(x, base + reg.offset, \
  56                                  mask, reg.shift, v, reg.write_mask)
  57
  58 #define VOP_WIN_SET(x, win, name, v) \
  59                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  60 #define VOP_SCL_SET(x, win, name, v) \
  61                 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
  62 #define VOP_SCL_SET_EXT(x, win, name, v) \
  63                 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
  64 #define VOP_CTRL_SET(x, name, v) \
  65                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  66
  67 #define VOP_INTR_GET(vop, name) \
  68                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  69
  70 #define VOP_INTR_SET(vop, name, mask, v) \
  71                 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
  72 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  73         do { \
  74                 int i, reg = 0, mask = 0; \
  75                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  76                         if (vop->data->intr->intrs[i] & type) { \
  77                                 reg |= (v) << i; \
  78                                 mask |= 1 << i; \
  79                         } \
  80                 } \
  81                 VOP_INTR_SET(vop, name, mask, reg); \
  82         } while (0)
  83 #define VOP_INTR_GET_TYPE(vop, name, type) \
  84                 vop_get_intr_type(vop, &vop->data->intr->name, type)
  85
  86 #define VOP_WIN_GET(x, win, name) \
  87                 vop_read_reg(x, win->base, &win->phy->name)
  88
  89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  90                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  91
  92 #define to_vop(x) container_of(x, struct vop, crtc)
  93 #define to_vop_win(x) container_of(x, struct vop_win, base)
  94
  95 enum vop_pending {
  96         VOP_PENDING_FB_UNREF,
  97 };
  98
  99 struct vop_win {
 100         struct drm_plane base;
 101         const struct vop_win_data *data;
 102         struct vop *vop;
 103 };
 104
 105 struct vop {
 106         struct drm_crtc crtc;
 107         struct device *dev;
 108         struct drm_device *drm_dev;
 109         bool is_enabled;
 110
 111         /* mutex vsync_ work */
 112         struct mutex vsync_mutex;
 113         bool vsync_work_pending;
 114         struct completion dsp_hold_completion;
 115
 116         /* protected by dev->event_lock */
 117         struct drm_pending_vblank_event *event;
 118
 119         struct drm_flip_work fb_unref_work;
 120         unsigned long pending;
 121
 122         struct completion line_flag_completion;
 123
 124         const struct vop_data *data;
 125
 126         uint32_t *regsbak;
 127         void __iomem *regs;
 128
 129         /* physical map length of vop register */
 130         uint32_t len;
 131
 132         /* one time only one process allowed to config the register */
 133         spinlock_t reg_lock;
 134         /* lock vop irq reg */
 135         spinlock_t irq_lock;
 136
 137         unsigned int irq;
 138
 139         /* vop AHP clk */
 140         struct clk *hclk;
 141         /* vop dclk */
 142         struct clk *dclk;
 143         /* vop share memory frequency */
 144         struct clk *aclk;
 145
 146         /* vop dclk reset */
 147         struct reset_control *dclk_rst;
 148
 149         struct vop_win win[];
 150 };
 151
 152 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 153 {
 154         writel(v, vop->regs + offset);
 155         vop->regsbak[offset >> 2] = v;
 156 }
 157
 158 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 159 {
 160         return readl(vop->regs + offset);
 161 }
 162
 163 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 164                                     const struct vop_reg *reg)
 165 {
 166         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 167 }
 168
 169 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 170                                   uint32_t mask, uint32_t shift, uint32_t v,
 171                                   bool write_mask, bool relaxed)
 172 {
 173         if (!mask)
 174                 return;
 175
 176         if (write_mask) {
 177                 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
 178         } else {
 179                 uint32_t cached_val = vop->regsbak[offset >> 2];
 180
 181                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 182                 vop->regsbak[offset >> 2] = v;
 183         }
 184
 185         if (relaxed)
 186                 writel_relaxed(v, vop->regs + offset);
 187         else
 188                 writel(v, vop->regs + offset);
 189 }
 190
 191 static inline uint32_t vop_get_intr_type(struct vop *vop,
 192                                          const struct vop_reg *reg, int type)
 193 {
 194         uint32_t i, ret = 0;
 195         uint32_t regs = vop_read_reg(vop, 0, reg);
 196
 197         for (i = 0; i < vop->data->intr->nintrs; i++) {
 198                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 199                         ret |= vop->data->intr->intrs[i];
 200         }
 201
 202         return ret;
 203 }
 204
 205 static inline void vop_cfg_done(struct vop *vop)
 206 {
 207         VOP_CTRL_SET(vop, cfg_done, 1);
 208 }
 209
 210 static bool has_rb_swapped(uint32_t format)
 211 {
 212         switch (format) {
 213         case DRM_FORMAT_XBGR8888:
 214         case DRM_FORMAT_ABGR8888:
 215         case DRM_FORMAT_BGR888:
 216         case DRM_FORMAT_BGR565:
 217                 return true;
 218         default:
 219                 return false;
 220         }
 221 }
 222
 223 static enum vop_data_format vop_convert_format(uint32_t format)
 224 {
 225         switch (format) {
 226         case DRM_FORMAT_XRGB8888:
 227         case DRM_FORMAT_ARGB8888:
 228         case DRM_FORMAT_XBGR8888:
 229         case DRM_FORMAT_ABGR8888:
 230                 return VOP_FMT_ARGB8888;
 231         case DRM_FORMAT_RGB888:
 232         case DRM_FORMAT_BGR888:
 233                 return VOP_FMT_RGB888;
 234         case DRM_FORMAT_RGB565:
 235         case DRM_FORMAT_BGR565:
 236                 return VOP_FMT_RGB565;
 237         case DRM_FORMAT_NV12:
 238                 return VOP_FMT_YUV420SP;
 239         case DRM_FORMAT_NV16:
 240                 return VOP_FMT_YUV422SP;
 241         case DRM_FORMAT_NV24:
 242                 return VOP_FMT_YUV444SP;
 243         default:
 244                 DRM_ERROR("unsupported format[%08x]\n", format);
 245                 return -EINVAL;
 246         }
 247 }
 248
 249 static bool is_yuv_support(uint32_t format)
 250 {
 251         switch (format) {
 252         case DRM_FORMAT_NV12:
 253         case DRM_FORMAT_NV16:
 254         case DRM_FORMAT_NV24:
 255                 return true;
 256         default:
 257                 return false;
 258         }
 259 }
 260
 261 static bool is_alpha_support(uint32_t format)
 262 {
 263         switch (format) {
 264         case DRM_FORMAT_ARGB8888:
 265         case DRM_FORMAT_ABGR8888:
 266                 return true;
 267         default:
 268                 return false;
 269         }
 270 }
 271
 272 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 273                                   uint32_t dst, bool is_horizontal,
 274                                   int vsu_mode, int *vskiplines)
 275 {
 276         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 277
 278         if (is_horizontal) {
 279                 if (mode == SCALE_UP)
 280                         val = GET_SCL_FT_BIC(src, dst);
 281                 else if (mode == SCALE_DOWN)
 282                         val = GET_SCL_FT_BILI_DN(src, dst);
 283         } else {
 284                 if (mode == SCALE_UP) {
 285                         if (vsu_mode == SCALE_UP_BIL)
 286                                 val = GET_SCL_FT_BILI_UP(src, dst);
 287                         else
 288                                 val = GET_SCL_FT_BIC(src, dst);
 289                 } else if (mode == SCALE_DOWN) {
 290                         if (vskiplines) {
 291                                 *vskiplines = scl_get_vskiplines(src, dst);
 292                                 val = scl_get_bili_dn_vskip(src, dst,
 293                                                             *vskiplines);
 294                         } else {
 295                                 val = GET_SCL_FT_BILI_DN(src, dst);
 296                         }
 297                 }
 298         }
 299
 300         return val;
 301 }
 302
 303 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
 304                              uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 305                              uint32_t dst_h, uint32_t pixel_format)
 306 {
 307         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 308         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 309         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 310         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 311         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 312         bool is_yuv = is_yuv_support(pixel_format);
 313         uint16_t cbcr_src_w = src_w / hsub;
 314         uint16_t cbcr_src_h = src_h / vsub;
 315         uint16_t vsu_mode;
 316         uint16_t lb_mode;
 317         uint32_t val;
 318         int vskiplines = 0;
 319
 320         if (dst_w > 3840) {
 321                 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
 322                 return;
 323         }
 324
 325         if (!win->phy->scl->ext) {
 326                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 327                             scl_cal_scale2(src_w, dst_w));
 328                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 329                             scl_cal_scale2(src_h, dst_h));
 330                 if (is_yuv) {
 331                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 332                                     scl_cal_scale2(cbcr_src_w, dst_w));
 333                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 334                                     scl_cal_scale2(cbcr_src_h, dst_h));
 335                 }
 336                 return;
 337         }
 338
 339         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 340         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 341
 342         if (is_yuv) {
 343                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 344                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 345                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 346                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 347                 else
 348                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 349         } else {
 350                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 351                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 352                 else
 353                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 354         }
 355
 356         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 357         if (lb_mode == LB_RGB_3840X2) {
 358                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 359                         DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
 360                         return;
 361                 }
 362                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 363                         DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
 364                         return;
 365                 }
 366                 vsu_mode = SCALE_UP_BIL;
 367         } else if (lb_mode == LB_RGB_2560X4) {
 368                 vsu_mode = SCALE_UP_BIL;
 369         } else {
 370                 vsu_mode = SCALE_UP_BIC;
 371         }
 372
 373         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 374                                 true, 0, NULL);
 375         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 376         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 377                                 false, vsu_mode, &vskiplines);
 378         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 379
 380         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 381         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 382
 383         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 384         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 385         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 386         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 387         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 388         if (is_yuv) {
 389                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 390                                         dst_w, true, 0, NULL);
 391                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 392                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 393                                         dst_h, false, vsu_mode, &vskiplines);
 394                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 395
 396                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 397                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 398                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 399                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 400                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 401                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 402                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 403         }
 404 }
 405
 406 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 407 {
 408         unsigned long flags;
 409
 410         if (WARN_ON(!vop->is_enabled))
 411                 return;
 412
 413         spin_lock_irqsave(&vop->irq_lock, flags);
 414
 415         VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
 416         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 417
 418         spin_unlock_irqrestore(&vop->irq_lock, flags);
 419 }
 420
 421 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 422 {
 423         unsigned long flags;
 424
 425         if (WARN_ON(!vop->is_enabled))
 426                 return;
 427
 428         spin_lock_irqsave(&vop->irq_lock, flags);
 429
 430         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 431
 432         spin_unlock_irqrestore(&vop->irq_lock, flags);
 433 }
 434
 435 /*
 436  * (1) each frame starts at the start of the Vsync pulse which is signaled by
 437  *     the "FRAME_SYNC" interrupt.
 438  * (2) the active data region of each frame ends at dsp_vact_end
 439  * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
 440  *      to get "LINE_FLAG" interrupt at the end of the active on screen data.
 441  *
 442  * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
 443  * Interrupts
 444  * LINE_FLAG -------------------------------+
 445  * FRAME_SYNC ----+                         |
 446  *                |                         |
 447  *                v                         v
 448  *                | Vsync | Vbp |  Vactive  | Vfp |
 449  *                        ^     ^           ^     ^
 450  *                        |     |           |     |
 451  *                        |     |           |     |
 452  * dsp_vs_end ------------+     |           |     |   VOP_DSP_VTOTAL_VS_END
 453  * dsp_vact_start --------------+           |     |   VOP_DSP_VACT_ST_END
 454  * dsp_vact_end ----------------------------+     |   VOP_DSP_VACT_ST_END
 455  * dsp_total -------------------------------------+   VOP_DSP_VTOTAL_VS_END
 456  */
 457 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
 458 {
 459         uint32_t line_flag_irq;
 460         unsigned long flags;
 461
 462         spin_lock_irqsave(&vop->irq_lock, flags);
 463
 464         line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
 465
 466         spin_unlock_irqrestore(&vop->irq_lock, flags);
 467
 468         return !!line_flag_irq;
 469 }
 470
 471 static void vop_line_flag_irq_enable(struct vop *vop)
 472 {
 473         unsigned long flags;
 474
 475         if (WARN_ON(!vop->is_enabled))
 476                 return;
 477
 478         spin_lock_irqsave(&vop->irq_lock, flags);
 479
 480         VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
 481         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
 482
 483         spin_unlock_irqrestore(&vop->irq_lock, flags);
 484 }
 485
 486 static void vop_line_flag_irq_disable(struct vop *vop)
 487 {
 488         unsigned long flags;
 489
 490         if (WARN_ON(!vop->is_enabled))
 491                 return;
 492
 493         spin_lock_irqsave(&vop->irq_lock, flags);
 494
 495         VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
 496
 497         spin_unlock_irqrestore(&vop->irq_lock, flags);
 498 }
 499
 500 static int vop_enable(struct drm_crtc *crtc)
 501 {
 502         struct vop *vop = to_vop(crtc);
 503         int ret, i;
 504
 505         ret = pm_runtime_get_sync(vop->dev);
 506         if (ret < 0) {
 507                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 508                 return ret;
 509         }
 510
 511         ret = clk_enable(vop->hclk);
 512         if (WARN_ON(ret < 0))
 513                 goto err_put_pm_runtime;
 514
 515         ret = clk_enable(vop->dclk);
 516         if (WARN_ON(ret < 0))
 517                 goto err_disable_hclk;
 518
 519         ret = clk_enable(vop->aclk);
 520         if (WARN_ON(ret < 0))
 521                 goto err_disable_dclk;
 522
 523         /*
 524          * Slave iommu shares power, irq and clock with vop.  It was associated
 525          * automatically with this master device via common driver code.
 526          * Now that we have enabled the clock we attach it to the shared drm
 527          * mapping.
 528          */
 529         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 530         if (ret) {
 531                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 532                 goto err_disable_aclk;
 533         }
 534
 535         memcpy(vop->regs, vop->regsbak, vop->len);
 536         /*
 537          * We need to make sure that all windows are disabled before we
 538          * enable the crtc. Otherwise we might try to scan from a destroyed
 539          * buffer later.
 540          */
 541         for (i = 0; i < vop->data->win_size; i++) {
 542                 struct vop_win *vop_win = &vop->win[i];
 543                 const struct vop_win_data *win = vop_win->data;
 544
 545                 spin_lock(&vop->reg_lock);
 546                 VOP_WIN_SET(vop, win, enable, 0);
 547                 spin_unlock(&vop->reg_lock);
 548         }
 549
 550         vop_cfg_done(vop);
 551
 552         /*
 553          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 554          */
 555         vop->is_enabled = true;
 556
 557         spin_lock(&vop->reg_lock);
 558
 559         VOP_CTRL_SET(vop, standby, 0);
 560
 561         spin_unlock(&vop->reg_lock);
 562
 563         enable_irq(vop->irq);
 564
 565         drm_crtc_vblank_on(crtc);
 566
 567         return 0;
 568
 569 err_disable_aclk:
 570         clk_disable(vop->aclk);
 571 err_disable_dclk:
 572         clk_disable(vop->dclk);
 573 err_disable_hclk:
 574         clk_disable(vop->hclk);
 575 err_put_pm_runtime:
 576         pm_runtime_put_sync(vop->dev);
 577         return ret;
 578 }
 579
 580 static void vop_crtc_disable(struct drm_crtc *crtc)
 581 {
 582         struct vop *vop = to_vop(crtc);
 583
 584         WARN_ON(vop->event);
 585
 586         rockchip_drm_psr_deactivate(&vop->crtc);
 587
 588         drm_crtc_vblank_off(crtc);
 589
 590         /*
 591          * Vop standby will take effect at end of current frame,
 592          * if dsp hold valid irq happen, it means standby complete.
 593          *
 594          * we must wait standby complete when we want to disable aclk,
 595          * if not, memory bus maybe dead.
 596          */
 597         reinit_completion(&vop->dsp_hold_completion);
 598         vop_dsp_hold_valid_irq_enable(vop);
 599
 600         spin_lock(&vop->reg_lock);
 601
 602         VOP_CTRL_SET(vop, standby, 1);
 603
 604         spin_unlock(&vop->reg_lock);
 605
 606         wait_for_completion(&vop->dsp_hold_completion);
 607
 608         vop_dsp_hold_valid_irq_disable(vop);
 609
 610         disable_irq(vop->irq);
 611
 612         vop->is_enabled = false;
 613
 614         /*
 615          * vop standby complete, so iommu detach is safe.
 616          */
 617         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 618
 619         clk_disable(vop->dclk);
 620         clk_disable(vop->aclk);
 621         clk_disable(vop->hclk);
 622         pm_runtime_put(vop->dev);
 623
 624         if (crtc->state->event && !crtc->state->active) {
 625                 spin_lock_irq(&crtc->dev->event_lock);
 626                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 627                 spin_unlock_irq(&crtc->dev->event_lock);
 628
 629                 crtc->state->event = NULL;
 630         }
 631 }
 632
 633 static void vop_plane_destroy(struct drm_plane *plane)
 634 {
 635         drm_plane_cleanup(plane);
 636 }
 637
 638 static int vop_plane_atomic_check(struct drm_plane *plane,
 639                            struct drm_plane_state *state)
 640 {
 641         struct drm_crtc *crtc = state->crtc;
 642         struct drm_crtc_state *crtc_state;
 643         struct drm_framebuffer *fb = state->fb;
 644         struct vop_win *vop_win = to_vop_win(plane);
 645         const struct vop_win_data *win = vop_win->data;
 646         int ret;
 647         struct drm_rect clip;
 648         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 649                                         DRM_PLANE_HELPER_NO_SCALING;
 650         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 651                                         DRM_PLANE_HELPER_NO_SCALING;
 652
 653         if (!crtc || !fb)
 654                 return 0;
 655
 656         crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
 657         if (WARN_ON(!crtc_state))
 658                 return -EINVAL;
 659
 660         clip.x1 = 0;
 661         clip.y1 = 0;
 662         clip.x2 = crtc_state->adjusted_mode.hdisplay;
 663         clip.y2 = crtc_state->adjusted_mode.vdisplay;
 664
 665         ret = drm_plane_helper_check_state(state, &clip,
 666                                            min_scale, max_scale,
 667                                            true, true);
 668         if (ret)
 669                 return ret;
 670
 671         if (!state->visible)
 672                 return 0;
 673
 674         ret = vop_convert_format(fb->format->format);
 675         if (ret < 0)
 676                 return ret;
 677
 678         /*
 679          * Src.x1 can be odd when do clip, but yuv plane start point
 680          * need align with 2 pixel.
 681          */
 682         if (is_yuv_support(fb->format->format) && ((state->src.x1 >> 16) % 2))
 683                 return -EINVAL;
 684
 685         return 0;
 686 }
 687
 688 static void vop_plane_atomic_disable(struct drm_plane *plane,
 689                                      struct drm_plane_state *old_state)
 690 {
 691         struct vop_win *vop_win = to_vop_win(plane);
 692         const struct vop_win_data *win = vop_win->data;
 693         struct vop *vop = to_vop(old_state->crtc);
 694
 695         if (!old_state->crtc)
 696                 return;
 697
 698         spin_lock(&vop->reg_lock);
 699
 700         VOP_WIN_SET(vop, win, enable, 0);
 701
 702         spin_unlock(&vop->reg_lock);
 703 }
 704
 705 static void vop_plane_atomic_update(struct drm_plane *plane,
 706                 struct drm_plane_state *old_state)
 707 {
 708         struct drm_plane_state *state = plane->state;
 709         struct drm_crtc *crtc = state->crtc;
 710         struct vop_win *vop_win = to_vop_win(plane);
 711         const struct vop_win_data *win = vop_win->data;
 712         struct vop *vop = to_vop(state->crtc);
 713         struct drm_framebuffer *fb = state->fb;
 714         unsigned int actual_w, actual_h;
 715         unsigned int dsp_stx, dsp_sty;
 716         uint32_t act_info, dsp_info, dsp_st;
 717         struct drm_rect *src = &state->src;
 718         struct drm_rect *dest = &state->dst;
 719         struct drm_gem_object *obj, *uv_obj;
 720         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 721         unsigned long offset;
 722         dma_addr_t dma_addr;
 723         uint32_t val;
 724         bool rb_swap;
 725         int format;
 726
 727         /*
 728          * can't update plane when vop is disabled.
 729          */
 730         if (WARN_ON(!crtc))
 731                 return;
 732
 733         if (WARN_ON(!vop->is_enabled))
 734                 return;
 735
 736         if (!state->visible) {
 737                 vop_plane_atomic_disable(plane, old_state);
 738                 return;
 739         }
 740
 741         obj = rockchip_fb_get_gem_obj(fb, 0);
 742         rk_obj = to_rockchip_obj(obj);
 743
 744         actual_w = drm_rect_width(src) >> 16;
 745         actual_h = drm_rect_height(src) >> 16;
 746         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 747
 748         dsp_info = (drm_rect_height(dest) - 1) << 16;
 749         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 750
 751         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 752         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 753         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 754
 755         offset = (src->x1 >> 16) * fb->format->cpp[0];
 756         offset += (src->y1 >> 16) * fb->pitches[0];
 757         dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 758
 759         format = vop_convert_format(fb->format->format);
 760
 761         spin_lock(&vop->reg_lock);
 762
 763         VOP_WIN_SET(vop, win, format, format);
 764         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 765         VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
 766         if (is_yuv_support(fb->format->format)) {
 767                 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
 768                 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
 769                 int bpp = fb->format->cpp[1];
 770
 771                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 772                 rk_uv_obj = to_rockchip_obj(uv_obj);
 773
 774                 offset = (src->x1 >> 16) * bpp / hsub;
 775                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 776
 777                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 778                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 779                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 780         }
 781
 782         if (win->phy->scl)
 783                 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 784                                     drm_rect_width(dest), drm_rect_height(dest),
 785                                     fb->format->format);
 786
 787         VOP_WIN_SET(vop, win, act_info, act_info);
 788         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 789         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 790
 791         rb_swap = has_rb_swapped(fb->format->format);
 792         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 793
 794         if (is_alpha_support(fb->format->format)) {
 795                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 796                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 797                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 798                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 799                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 800                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 801                         SRC_FACTOR_M0(ALPHA_ONE);
 802                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 803         } else {
 804                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 805         }
 806
 807         VOP_WIN_SET(vop, win, enable, 1);
 808         spin_unlock(&vop->reg_lock);
 809 }
 810
 811 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 812         .atomic_check = vop_plane_atomic_check,
 813         .atomic_update = vop_plane_atomic_update,
 814         .atomic_disable = vop_plane_atomic_disable,
 815 };
 816
 817 static const struct drm_plane_funcs vop_plane_funcs = {
 818         .update_plane   = drm_atomic_helper_update_plane,
 819         .disable_plane  = drm_atomic_helper_disable_plane,
 820         .destroy = vop_plane_destroy,
 821         .reset = drm_atomic_helper_plane_reset,
 822         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 823         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 824 };
 825
 826 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 827 {
 828         struct vop *vop = to_vop(crtc);
 829         unsigned long flags;
 830
 831         if (WARN_ON(!vop->is_enabled))
 832                 return -EPERM;
 833
 834         spin_lock_irqsave(&vop->irq_lock, flags);
 835
 836         VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
 837         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 838
 839         spin_unlock_irqrestore(&vop->irq_lock, flags);
 840
 841         return 0;
 842 }
 843
 844 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 845 {
 846         struct vop *vop = to_vop(crtc);
 847         unsigned long flags;
 848
 849         if (WARN_ON(!vop->is_enabled))
 850                 return;
 851
 852         spin_lock_irqsave(&vop->irq_lock, flags);
 853
 854         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 855
 856         spin_unlock_irqrestore(&vop->irq_lock, flags);
 857 }
 858
 859 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 860                                 const struct drm_display_mode *mode,
 861                                 struct drm_display_mode *adjusted_mode)
 862 {
 863         struct vop *vop = to_vop(crtc);
 864
 865         adjusted_mode->clock =
 866                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
 867
 868         return true;
 869 }
 870
 871 static void vop_crtc_enable(struct drm_crtc *crtc)
 872 {
 873         struct vop *vop = to_vop(crtc);
 874         const struct vop_data *vop_data = vop->data;
 875         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 876         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
 877         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 878         u16 hdisplay = adjusted_mode->hdisplay;
 879         u16 htotal = adjusted_mode->htotal;
 880         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 881         u16 hact_end = hact_st + hdisplay;
 882         u16 vdisplay = adjusted_mode->vdisplay;
 883         u16 vtotal = adjusted_mode->vtotal;
 884         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 885         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 886         u16 vact_end = vact_st + vdisplay;
 887         uint32_t pin_pol, val;
 888         int ret;
 889
 890         WARN_ON(vop->event);
 891
 892         ret = vop_enable(crtc);
 893         if (ret) {
 894                 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
 895                 return;
 896         }
 897
 898         /*
 899          * If dclk rate is zero, mean that scanout is stop,
 900          * we don't need wait any more.
 901          */
 902         if (clk_get_rate(vop->dclk)) {
 903                 /*
 904                  * Rk3288 vop timing register is immediately, when configure
 905                  * display timing on display time, may cause tearing.
 906                  *
 907                  * Vop standby will take effect at end of current frame,
 908                  * if dsp hold valid irq happen, it means standby complete.
 909                  *
 910                  * mode set:
 911                  *    standby and wait complete --> |----
 912                  *                                  | display time
 913                  *                                  |----
 914                  *                                  |---> dsp hold irq
 915                  *     configure display timing --> |
 916                  *         standby exit             |
 917                  *                                  | new frame start.
 918                  */
 919
 920                 reinit_completion(&vop->dsp_hold_completion);
 921                 vop_dsp_hold_valid_irq_enable(vop);
 922
 923                 spin_lock(&vop->reg_lock);
 924
 925                 VOP_CTRL_SET(vop, standby, 1);
 926
 927                 spin_unlock(&vop->reg_lock);
 928
 929                 wait_for_completion(&vop->dsp_hold_completion);
 930
 931                 vop_dsp_hold_valid_irq_disable(vop);
 932         }
 933
 934         pin_pol = BIT(DCLK_INVERT);
 935         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
 936                    BIT(HSYNC_POSITIVE) : 0;
 937         pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
 938                    BIT(VSYNC_POSITIVE) : 0;
 939         VOP_CTRL_SET(vop, pin_pol, pin_pol);
 940
 941         switch (s->output_type) {
 942         case DRM_MODE_CONNECTOR_LVDS:
 943                 VOP_CTRL_SET(vop, rgb_en, 1);
 944                 VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol);
 945                 break;
 946         case DRM_MODE_CONNECTOR_eDP:
 947                 VOP_CTRL_SET(vop, edp_pin_pol, pin_pol);
 948                 VOP_CTRL_SET(vop, edp_en, 1);
 949                 break;
 950         case DRM_MODE_CONNECTOR_HDMIA:
 951                 VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol);
 952                 VOP_CTRL_SET(vop, hdmi_en, 1);
 953                 break;
 954         case DRM_MODE_CONNECTOR_DSI:
 955                 VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol);
 956                 VOP_CTRL_SET(vop, mipi_en, 1);
 957                 break;
 958         case DRM_MODE_CONNECTOR_DisplayPort:
 959                 pin_pol &= ~BIT(DCLK_INVERT);
 960                 VOP_CTRL_SET(vop, dp_pin_pol, pin_pol);
 961                 VOP_CTRL_SET(vop, dp_en, 1);
 962                 break;
 963         default:
 964                 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
 965                               s->output_type);
 966         }
 967
 968         /*
 969          * if vop is not support RGB10 output, need force RGB10 to RGB888.
 970          */
 971         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
 972             !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
 973                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
 974         VOP_CTRL_SET(vop, out_mode, s->output_mode);
 975
 976         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 977         val = hact_st << 16;
 978         val |= hact_end;
 979         VOP_CTRL_SET(vop, hact_st_end, val);
 980         VOP_CTRL_SET(vop, hpost_st_end, val);
 981
 982         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
 983         val = vact_st << 16;
 984         val |= vact_end;
 985         VOP_CTRL_SET(vop, vact_st_end, val);
 986         VOP_CTRL_SET(vop, vpost_st_end, val);
 987
 988         VOP_CTRL_SET(vop, line_flag_num[0], vact_end);
 989
 990         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 991
 992         VOP_CTRL_SET(vop, standby, 0);
 993
 994         rockchip_drm_psr_activate(&vop->crtc);
 995 }
 996
 997 static bool vop_fs_irq_is_pending(struct vop *vop)
 998 {
 999         return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1000 }
1001
1002 static void vop_wait_for_irq_handler(struct vop *vop)
1003 {
1004         bool pending;
1005         int ret;
1006
1007         /*
1008          * Spin until frame start interrupt status bit goes low, which means
1009          * that interrupt handler was invoked and cleared it. The timeout of
1010          * 10 msecs is really too long, but it is just a safety measure if
1011          * something goes really wrong. The wait will only happen in the very
1012          * unlikely case of a vblank happening exactly at the same time and
1013          * shouldn't exceed microseconds range.
1014          */
1015         ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1016                                         !pending, 0, 10 * 1000);
1017         if (ret)
1018                 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1019
1020         synchronize_irq(vop->irq);
1021 }
1022
1023 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1024                                   struct drm_crtc_state *old_crtc_state)
1025 {
1026         struct drm_atomic_state *old_state = old_crtc_state->state;
1027         struct drm_plane_state *old_plane_state;
1028         struct vop *vop = to_vop(crtc);
1029         struct drm_plane *plane;
1030         int i;
1031
1032         if (WARN_ON(!vop->is_enabled))
1033                 return;
1034
1035         spin_lock(&vop->reg_lock);
1036
1037         vop_cfg_done(vop);
1038
1039         spin_unlock(&vop->reg_lock);
1040
1041         /*
1042          * There is a (rather unlikely) possiblity that a vblank interrupt
1043          * fired before we set the cfg_done bit. To avoid spuriously
1044          * signalling flip completion we need to wait for it to finish.
1045          */
1046         vop_wait_for_irq_handler(vop);
1047
1048         spin_lock_irq(&crtc->dev->event_lock);
1049         if (crtc->state->event) {
1050                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1051                 WARN_ON(vop->event);
1052
1053                 vop->event = crtc->state->event;
1054                 crtc->state->event = NULL;
1055         }
1056         spin_unlock_irq(&crtc->dev->event_lock);
1057
1058         for_each_plane_in_state(old_state, plane, old_plane_state, i) {
1059                 if (!old_plane_state->fb)
1060                         continue;
1061
1062                 if (old_plane_state->fb == plane->state->fb)
1063                         continue;
1064
1065                 drm_framebuffer_reference(old_plane_state->fb);
1066                 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1067                 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1068                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1069         }
1070 }
1071
1072 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1073                                   struct drm_crtc_state *old_crtc_state)
1074 {
1075         rockchip_drm_psr_flush(crtc);
1076 }
1077
1078 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1079         .enable = vop_crtc_enable,
1080         .disable = vop_crtc_disable,
1081         .mode_fixup = vop_crtc_mode_fixup,
1082         .atomic_flush = vop_crtc_atomic_flush,
1083         .atomic_begin = vop_crtc_atomic_begin,
1084 };
1085
1086 static void vop_crtc_destroy(struct drm_crtc *crtc)
1087 {
1088         drm_crtc_cleanup(crtc);
1089 }
1090
1091 static void vop_crtc_reset(struct drm_crtc *crtc)
1092 {
1093         if (crtc->state)
1094                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1095         kfree(crtc->state);
1096
1097         crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1098         if (crtc->state)
1099                 crtc->state->crtc = crtc;
1100 }
1101
1102 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1103 {
1104         struct rockchip_crtc_state *rockchip_state;
1105
1106         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1107         if (!rockchip_state)
1108                 return NULL;
1109
1110         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1111         return &rockchip_state->base;
1112 }
1113
1114 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1115                                    struct drm_crtc_state *state)
1116 {
1117         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1118
1119         __drm_atomic_helper_crtc_destroy_state(&s->base);
1120         kfree(s);
1121 }
1122
1123 #ifdef CONFIG_DRM_ANALOGIX_DP
1124 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1125 {
1126         struct drm_connector *connector;
1127         struct drm_connector_list_iter conn_iter;
1128
1129         drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1130         drm_for_each_connector_iter(connector, &conn_iter) {
1131                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1132                         drm_connector_list_iter_end(&conn_iter);
1133                         return connector;
1134                 }
1135         }
1136         drm_connector_list_iter_end(&conn_iter);
1137
1138         return NULL;
1139 }
1140
1141 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1142                                    const char *source_name, size_t *values_cnt)
1143 {
1144         struct vop *vop = to_vop(crtc);
1145         struct drm_connector *connector;
1146         int ret;
1147
1148         connector = vop_get_edp_connector(vop);
1149         if (!connector)
1150                 return -EINVAL;
1151
1152         *values_cnt = 3;
1153
1154         if (source_name && strcmp(source_name, "auto") == 0)
1155                 ret = analogix_dp_start_crc(connector);
1156         else if (!source_name)
1157                 ret = analogix_dp_stop_crc(connector);
1158         else
1159                 ret = -EINVAL;
1160
1161         return ret;
1162 }
1163 #else
1164 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1165                                    const char *source_name, size_t *values_cnt)
1166 {
1167         return -ENODEV;
1168 }
1169 #endif
1170
1171 static const struct drm_crtc_funcs vop_crtc_funcs = {
1172         .set_config = drm_atomic_helper_set_config,
1173         .page_flip = drm_atomic_helper_page_flip,
1174         .destroy = vop_crtc_destroy,
1175         .reset = vop_crtc_reset,
1176         .atomic_duplicate_state = vop_crtc_duplicate_state,
1177         .atomic_destroy_state = vop_crtc_destroy_state,
1178         .enable_vblank = vop_crtc_enable_vblank,
1179         .disable_vblank = vop_crtc_disable_vblank,
1180         .set_crc_source = vop_crtc_set_crc_source,
1181 };
1182
1183 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1184 {
1185         struct vop *vop = container_of(work, struct vop, fb_unref_work);
1186         struct drm_framebuffer *fb = val;
1187
1188         drm_crtc_vblank_put(&vop->crtc);
1189         drm_framebuffer_unreference(fb);
1190 }
1191
1192 static void vop_handle_vblank(struct vop *vop)
1193 {
1194         struct drm_device *drm = vop->drm_dev;
1195         struct drm_crtc *crtc = &vop->crtc;
1196         unsigned long flags;
1197
1198         spin_lock_irqsave(&drm->event_lock, flags);
1199         if (vop->event) {
1200                 drm_crtc_send_vblank_event(crtc, vop->event);
1201                 drm_crtc_vblank_put(crtc);
1202                 vop->event = NULL;
1203         }
1204         spin_unlock_irqrestore(&drm->event_lock, flags);
1205
1206         if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1207                 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1208 }
1209
1210 static irqreturn_t vop_isr(int irq, void *data)
1211 {
1212         struct vop *vop = data;
1213         struct drm_crtc *crtc = &vop->crtc;
1214         uint32_t active_irqs;
1215         unsigned long flags;
1216         int ret = IRQ_NONE;
1217
1218         /*
1219          * interrupt register has interrupt status, enable and clear bits, we
1220          * must hold irq_lock to avoid a race with enable/disable_vblank().
1221         */
1222         spin_lock_irqsave(&vop->irq_lock, flags);
1223
1224         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1225         /* Clear all active interrupt sources */
1226         if (active_irqs)
1227                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1228
1229         spin_unlock_irqrestore(&vop->irq_lock, flags);
1230
1231         /* This is expected for vop iommu irqs, since the irq is shared */
1232         if (!active_irqs)
1233                 return IRQ_NONE;
1234
1235         if (active_irqs & DSP_HOLD_VALID_INTR) {
1236                 complete(&vop->dsp_hold_completion);
1237                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1238                 ret = IRQ_HANDLED;
1239         }
1240
1241         if (active_irqs & LINE_FLAG_INTR) {
1242                 complete(&vop->line_flag_completion);
1243                 active_irqs &= ~LINE_FLAG_INTR;
1244                 ret = IRQ_HANDLED;
1245         }
1246
1247         if (active_irqs & FS_INTR) {
1248                 drm_crtc_handle_vblank(crtc);
1249                 vop_handle_vblank(vop);
1250                 active_irqs &= ~FS_INTR;
1251                 ret = IRQ_HANDLED;
1252         }
1253
1254         /* Unhandled irqs are spurious. */
1255         if (active_irqs)
1256                 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1257                               active_irqs);
1258
1259         return ret;
1260 }
1261
1262 static int vop_create_crtc(struct vop *vop)
1263 {
1264         const struct vop_data *vop_data = vop->data;
1265         struct device *dev = vop->dev;
1266         struct drm_device *drm_dev = vop->drm_dev;
1267         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1268         struct drm_crtc *crtc = &vop->crtc;
1269         struct device_node *port;
1270         int ret;
1271         int i;
1272
1273         /*
1274          * Create drm_plane for primary and cursor planes first, since we need
1275          * to pass them to drm_crtc_init_with_planes, which sets the
1276          * "possible_crtcs" to the newly initialized crtc.
1277          */
1278         for (i = 0; i < vop_data->win_size; i++) {
1279                 struct vop_win *vop_win = &vop->win[i];
1280                 const struct vop_win_data *win_data = vop_win->data;
1281
1282                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1283                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1284                         continue;
1285
1286                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1287                                                0, &vop_plane_funcs,
1288                                                win_data->phy->data_formats,
1289                                                win_data->phy->nformats,
1290                                                win_data->type, NULL);
1291                 if (ret) {
1292                         DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1293                                       ret);
1294                         goto err_cleanup_planes;
1295                 }
1296
1297                 plane = &vop_win->base;
1298                 drm_plane_helper_add(plane, &plane_helper_funcs);
1299                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1300                         primary = plane;
1301                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1302                         cursor = plane;
1303         }
1304
1305         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1306                                         &vop_crtc_funcs, NULL);
1307         if (ret)
1308                 goto err_cleanup_planes;
1309
1310         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1311
1312         /*
1313          * Create drm_planes for overlay windows with possible_crtcs restricted
1314          * to the newly created crtc.
1315          */
1316         for (i = 0; i < vop_data->win_size; i++) {
1317                 struct vop_win *vop_win = &vop->win[i];
1318                 const struct vop_win_data *win_data = vop_win->data;
1319                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1320
1321                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1322                         continue;
1323
1324                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1325                                                possible_crtcs,
1326                                                &vop_plane_funcs,
1327                                                win_data->phy->data_formats,
1328                                                win_data->phy->nformats,
1329                                                win_data->type, NULL);
1330                 if (ret) {
1331                         DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1332                                       ret);
1333                         goto err_cleanup_crtc;
1334                 }
1335                 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1336         }
1337
1338         port = of_get_child_by_name(dev->of_node, "port");
1339         if (!port) {
1340                 DRM_DEV_ERROR(vop->dev, "no port node found in %s\n",
1341                               dev->of_node->full_name);
1342                 ret = -ENOENT;
1343                 goto err_cleanup_crtc;
1344         }
1345
1346         drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1347                            vop_fb_unref_worker);
1348
1349         init_completion(&vop->dsp_hold_completion);
1350         init_completion(&vop->line_flag_completion);
1351         crtc->port = port;
1352
1353         return 0;
1354
1355 err_cleanup_crtc:
1356         drm_crtc_cleanup(crtc);
1357 err_cleanup_planes:
1358         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1359                                  head)
1360                 drm_plane_cleanup(plane);
1361         return ret;
1362 }
1363
1364 static void vop_destroy_crtc(struct vop *vop)
1365 {
1366         struct drm_crtc *crtc = &vop->crtc;
1367         struct drm_device *drm_dev = vop->drm_dev;
1368         struct drm_plane *plane, *tmp;
1369
1370         of_node_put(crtc->port);
1371
1372         /*
1373          * We need to cleanup the planes now.  Why?
1374          *
1375          * The planes are "&vop->win[i].base".  That means the memory is
1376          * all part of the big "struct vop" chunk of memory.  That memory
1377          * was devm allocated and associated with this component.  We need to
1378          * free it ourselves before vop_unbind() finishes.
1379          */
1380         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1381                                  head)
1382                 vop_plane_destroy(plane);
1383
1384         /*
1385          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1386          * references the CRTC.
1387          */
1388         drm_crtc_cleanup(crtc);
1389         drm_flip_work_cleanup(&vop->fb_unref_work);
1390 }
1391
1392 static int vop_initial(struct vop *vop)
1393 {
1394         const struct vop_data *vop_data = vop->data;
1395         const struct vop_reg_data *init_table = vop_data->init_table;
1396         struct reset_control *ahb_rst;
1397         int i, ret;
1398
1399         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1400         if (IS_ERR(vop->hclk)) {
1401                 dev_err(vop->dev, "failed to get hclk source\n");
1402                 return PTR_ERR(vop->hclk);
1403         }
1404         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1405         if (IS_ERR(vop->aclk)) {
1406                 dev_err(vop->dev, "failed to get aclk source\n");
1407                 return PTR_ERR(vop->aclk);
1408         }
1409         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1410         if (IS_ERR(vop->dclk)) {
1411                 dev_err(vop->dev, "failed to get dclk source\n");
1412                 return PTR_ERR(vop->dclk);
1413         }
1414
1415         ret = pm_runtime_get_sync(vop->dev);
1416         if (ret < 0) {
1417                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
1418                 return ret;
1419         }
1420
1421         ret = clk_prepare(vop->dclk);
1422         if (ret < 0) {
1423                 dev_err(vop->dev, "failed to prepare dclk\n");
1424                 goto err_put_pm_runtime;
1425         }
1426
1427         /* Enable both the hclk and aclk to setup the vop */
1428         ret = clk_prepare_enable(vop->hclk);
1429         if (ret < 0) {
1430                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1431                 goto err_unprepare_dclk;
1432         }
1433
1434         ret = clk_prepare_enable(vop->aclk);
1435         if (ret < 0) {
1436                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1437                 goto err_disable_hclk;
1438         }
1439
1440         /*
1441          * do hclk_reset, reset all vop registers.
1442          */
1443         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1444         if (IS_ERR(ahb_rst)) {
1445                 dev_err(vop->dev, "failed to get ahb reset\n");
1446                 ret = PTR_ERR(ahb_rst);
1447                 goto err_disable_aclk;
1448         }
1449         reset_control_assert(ahb_rst);
1450         usleep_range(10, 20);
1451         reset_control_deassert(ahb_rst);
1452
1453         memcpy(vop->regsbak, vop->regs, vop->len);
1454
1455         for (i = 0; i < vop_data->table_size; i++)
1456                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1457
1458         for (i = 0; i < vop_data->win_size; i++) {
1459                 const struct vop_win_data *win = &vop_data->win[i];
1460
1461                 VOP_WIN_SET(vop, win, enable, 0);
1462         }
1463
1464         vop_cfg_done(vop);
1465
1466         /*
1467          * do dclk_reset, let all config take affect.
1468          */
1469         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1470         if (IS_ERR(vop->dclk_rst)) {
1471                 dev_err(vop->dev, "failed to get dclk reset\n");
1472                 ret = PTR_ERR(vop->dclk_rst);
1473                 goto err_disable_aclk;
1474         }
1475         reset_control_assert(vop->dclk_rst);
1476         usleep_range(10, 20);
1477         reset_control_deassert(vop->dclk_rst);
1478
1479         clk_disable(vop->hclk);
1480         clk_disable(vop->aclk);
1481
1482         vop->is_enabled = false;
1483
1484         pm_runtime_put_sync(vop->dev);
1485
1486         return 0;
1487
1488 err_disable_aclk:
1489         clk_disable_unprepare(vop->aclk);
1490 err_disable_hclk:
1491         clk_disable_unprepare(vop->hclk);
1492 err_unprepare_dclk:
1493         clk_unprepare(vop->dclk);
1494 err_put_pm_runtime:
1495         pm_runtime_put_sync(vop->dev);
1496         return ret;
1497 }
1498
1499 /*
1500  * Initialize the vop->win array elements.
1501  */
1502 static void vop_win_init(struct vop *vop)
1503 {
1504         const struct vop_data *vop_data = vop->data;
1505         unsigned int i;
1506
1507         for (i = 0; i < vop_data->win_size; i++) {
1508                 struct vop_win *vop_win = &vop->win[i];
1509                 const struct vop_win_data *win_data = &vop_data->win[i];
1510
1511                 vop_win->data = win_data;
1512                 vop_win->vop = vop;
1513         }
1514 }
1515
1516 /**
1517  * rockchip_drm_wait_vact_end
1518  * @crtc: CRTC to enable line flag
1519  * @mstimeout: millisecond for timeout
1520  *
1521  * Wait for vact_end line flag irq or timeout.
1522  *
1523  * Returns:
1524  * Zero on success, negative errno on failure.
1525  */
1526 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1527 {
1528         struct vop *vop = to_vop(crtc);
1529         unsigned long jiffies_left;
1530
1531         if (!crtc || !vop->is_enabled)
1532                 return -ENODEV;
1533
1534         if (mstimeout <= 0)
1535                 return -EINVAL;
1536
1537         if (vop_line_flag_irq_is_enabled(vop))
1538                 return -EBUSY;
1539
1540         reinit_completion(&vop->line_flag_completion);
1541         vop_line_flag_irq_enable(vop);
1542
1543         jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1544                                                    msecs_to_jiffies(mstimeout));
1545         vop_line_flag_irq_disable(vop);
1546
1547         if (jiffies_left == 0) {
1548                 dev_err(vop->dev, "Timeout waiting for IRQ\n");
1549                 return -ETIMEDOUT;
1550         }
1551
1552         return 0;
1553 }
1554 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1555
1556 static int vop_bind(struct device *dev, struct device *master, void *data)
1557 {
1558         struct platform_device *pdev = to_platform_device(dev);
1559         const struct vop_data *vop_data;
1560         struct drm_device *drm_dev = data;
1561         struct vop *vop;
1562         struct resource *res;
1563         size_t alloc_size;
1564         int ret, irq;
1565
1566         vop_data = of_device_get_match_data(dev);
1567         if (!vop_data)
1568                 return -ENODEV;
1569
1570         /* Allocate vop struct and its vop_win array */
1571         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1572         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1573         if (!vop)
1574                 return -ENOMEM;
1575
1576         vop->dev = dev;
1577         vop->data = vop_data;
1578         vop->drm_dev = drm_dev;
1579         dev_set_drvdata(dev, vop);
1580
1581         vop_win_init(vop);
1582
1583         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1584         vop->len = resource_size(res);
1585         vop->regs = devm_ioremap_resource(dev, res);
1586         if (IS_ERR(vop->regs))
1587                 return PTR_ERR(vop->regs);
1588
1589         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1590         if (!vop->regsbak)
1591                 return -ENOMEM;
1592
1593         irq = platform_get_irq(pdev, 0);
1594         if (irq < 0) {
1595                 dev_err(dev, "cannot find irq for vop\n");
1596                 return irq;
1597         }
1598         vop->irq = (unsigned int)irq;
1599
1600         spin_lock_init(&vop->reg_lock);
1601         spin_lock_init(&vop->irq_lock);
1602
1603         mutex_init(&vop->vsync_mutex);
1604
1605         ret = devm_request_irq(dev, vop->irq, vop_isr,
1606                                IRQF_SHARED, dev_name(dev), vop);
1607         if (ret)
1608                 return ret;
1609
1610         /* IRQ is initially disabled; it gets enabled in power_on */
1611         disable_irq(vop->irq);
1612
1613         ret = vop_create_crtc(vop);
1614         if (ret)
1615                 goto err_enable_irq;
1616
1617         pm_runtime_enable(&pdev->dev);
1618
1619         ret = vop_initial(vop);
1620         if (ret < 0) {
1621                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1622                 goto err_disable_pm_runtime;
1623         }
1624
1625         return 0;
1626
1627 err_disable_pm_runtime:
1628         pm_runtime_disable(&pdev->dev);
1629         vop_destroy_crtc(vop);
1630 err_enable_irq:
1631         enable_irq(vop->irq); /* To balance out the disable_irq above */
1632         return ret;
1633 }
1634
1635 static void vop_unbind(struct device *dev, struct device *master, void *data)
1636 {
1637         struct vop *vop = dev_get_drvdata(dev);
1638
1639         pm_runtime_disable(dev);
1640         vop_destroy_crtc(vop);
1641
1642         clk_unprepare(vop->aclk);
1643         clk_unprepare(vop->hclk);
1644         clk_unprepare(vop->dclk);
1645 }
1646
1647 const struct component_ops vop_component_ops = {
1648         .bind = vop_bind,
1649         .unbind = vop_unbind,
1650 };
1651 EXPORT_SYMBOL_GPL(vop_component_ops);