2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * encoder's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, the CRTC is also
19 * responsible for writing the display list for the HVS channel that
22 * The 2835 has 3 different pixel valves. pv0 in the audio power
23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
24 * image domain can feed either HDMI or the SDTV controller. The
25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26 * SDTV, etc.) according to which output type is chosen in the mux.
28 * For power management, the pixel valve's registers are all clocked
29 * by the AXI clock, while the timings and FIFOs make use of the
30 * output-specific clock. Since the encoders also directly consume
31 * the CPRMAN clocks, and know what timings they need, they are the
32 * ones that set the clock.
35 #include "drm_atomic.h"
36 #include "drm_atomic_helper.h"
37 #include "drm_crtc_helper.h"
38 #include "linux/clk.h"
39 #include "drm_fb_cma_helper.h"
40 #include "linux/component.h"
41 #include "linux/of_device.h"
47 const struct vc4_crtc_data *data;
50 /* Timestamp at start of vblank irq - unaffected by lock delays. */
53 /* Which HVS channel we're using for our CRTC. */
59 /* Size in pixels of the COB memory allocated to this CRTC. */
62 struct drm_pending_vblank_event *event;
65 struct vc4_crtc_state {
66 struct drm_crtc_state base;
67 /* Dlist area for this CRTC configuration. */
68 struct drm_mm_node mm;
71 static inline struct vc4_crtc *
72 to_vc4_crtc(struct drm_crtc *crtc)
74 return (struct vc4_crtc *)crtc;
77 static inline struct vc4_crtc_state *
78 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
80 return (struct vc4_crtc_state *)crtc_state;
83 struct vc4_crtc_data {
84 /* Which channel of the HVS this pixelvalve sources from. */
87 enum vc4_encoder_type encoder_types[4];
90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
93 #define CRTC_REG(reg) { reg, #reg }
99 CRTC_REG(PV_V_CONTROL),
100 CRTC_REG(PV_VSYNCD_EVEN),
105 CRTC_REG(PV_VERTA_EVEN),
106 CRTC_REG(PV_VERTB_EVEN),
108 CRTC_REG(PV_INTSTAT),
110 CRTC_REG(PV_HACT_ACT),
113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
117 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
118 DRM_INFO("0x%04x (%s): 0x%08x\n",
119 crtc_regs[i].reg, crtc_regs[i].name,
120 CRTC_READ(crtc_regs[i].reg));
124 #ifdef CONFIG_DEBUG_FS
125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
127 struct drm_info_node *node = (struct drm_info_node *)m->private;
128 struct drm_device *dev = node->minor->dev;
129 int crtc_index = (uintptr_t)node->info_ent->data;
130 struct drm_crtc *crtc;
131 struct vc4_crtc *vc4_crtc;
135 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
142 vc4_crtc = to_vc4_crtc(crtc);
144 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
145 seq_printf(m, "%s (0x%04x): 0x%08x\n",
146 crtc_regs[i].name, crtc_regs[i].reg,
147 CRTC_READ(crtc_regs[i].reg));
154 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
155 unsigned int flags, int *vpos, int *hpos,
156 ktime_t *stime, ktime_t *etime,
157 const struct drm_display_mode *mode)
159 struct vc4_dev *vc4 = to_vc4_dev(dev);
160 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
161 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
167 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
169 /* Get optional system timestamp before query. */
171 *stime = ktime_get();
174 * Read vertical scanline which is currently composed for our
175 * pixelvalve by the HVS, and also the scaler status.
177 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
179 /* Get optional system timestamp after query. */
181 *etime = ktime_get();
183 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
185 /* Vertical position of hvs composed scanline. */
186 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
189 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
192 /* Use hpos to correct for field offset in interlaced mode. */
193 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
194 *hpos += mode->crtc_htotal / 2;
197 /* This is the offset we need for translating hvs -> pv scanout pos. */
198 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
201 ret |= DRM_SCANOUTPOS_VALID;
203 /* HVS more than fifo_lines into frame for compositing? */
204 if (*vpos > fifo_lines) {
206 * We are in active scanout and can get some meaningful results
207 * from HVS. The actual PV scanout can not trail behind more
208 * than fifo_lines as that is the fifo's capacity. Assume that
209 * in active scanout the HVS and PV work in lockstep wrt. HVS
210 * refilling the fifo and PV consuming from the fifo, ie.
211 * whenever the PV consumes and frees up a scanline in the
212 * fifo, the HVS will immediately refill it, therefore
213 * incrementing vpos. Therefore we choose HVS read position -
214 * fifo size in scanlines as a estimate of the real scanout
215 * position of the PV.
217 *vpos -= fifo_lines + 1;
219 ret |= DRM_SCANOUTPOS_ACCURATE;
224 * Less: This happens when we are in vblank and the HVS, after getting
225 * the VSTART restart signal from the PV, just started refilling its
226 * fifo with new lines from the top-most lines of the new framebuffers.
227 * The PV does not scan out in vblank, so does not remove lines from
228 * the fifo, so the fifo will be full quickly and the HVS has to pause.
229 * We can't get meaningful readings wrt. scanline position of the PV
230 * and need to make things up in a approximative but consistent way.
232 ret |= DRM_SCANOUTPOS_IN_VBLANK;
233 vblank_lines = mode->vtotal - mode->vdisplay;
235 if (flags & DRM_CALLED_FROM_VBLIRQ) {
237 * Assume the irq handler got called close to first
238 * line of vblank, so PV has about a full vblank
239 * scanlines to go, and as a base timestamp use the
240 * one taken at entry into vblank irq handler, so it
241 * is not affected by random delays due to lock
242 * contention on event_lock or vblank_time lock in
245 *vpos = -vblank_lines;
248 *stime = vc4_crtc->t_vblank;
250 *etime = vc4_crtc->t_vblank;
253 * If the HVS fifo is not yet full then we know for certain
254 * we are at the very beginning of vblank, as the hvs just
255 * started refilling, and the stime and etime timestamps
256 * truly correspond to start of vblank.
258 if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
259 ret |= DRM_SCANOUTPOS_ACCURATE;
262 * No clue where we are inside vblank. Return a vpos of zero,
263 * which will cause calling code to just return the etime
264 * timestamp uncorrected. At least this is no worse than the
273 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
274 int *max_error, struct timeval *vblank_time,
277 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
278 struct drm_crtc_state *state = crtc->state;
280 /* Helper routine in DRM core does all the work: */
281 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
283 &state->adjusted_mode);
286 static void vc4_crtc_destroy(struct drm_crtc *crtc)
288 drm_crtc_cleanup(crtc);
292 vc4_crtc_lut_load(struct drm_crtc *crtc)
294 struct drm_device *dev = crtc->dev;
295 struct vc4_dev *vc4 = to_vc4_dev(dev);
296 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
299 /* The LUT memory is laid out with each HVS channel in order,
300 * each of which takes 256 writes for R, 256 for G, then 256
303 HVS_WRITE(SCALER_GAMADDR,
304 SCALER_GAMADDR_AUTOINC |
305 (vc4_crtc->channel * 3 * crtc->gamma_size));
307 for (i = 0; i < crtc->gamma_size; i++)
308 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
309 for (i = 0; i < crtc->gamma_size; i++)
310 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
311 for (i = 0; i < crtc->gamma_size; i++)
312 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
316 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
319 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
322 for (i = 0; i < size; i++) {
323 vc4_crtc->lut_r[i] = r[i] >> 8;
324 vc4_crtc->lut_g[i] = g[i] >> 8;
325 vc4_crtc->lut_b[i] = b[i] >> 8;
328 vc4_crtc_lut_load(crtc);
333 static u32 vc4_get_fifo_full_level(u32 format)
335 static const u32 fifo_len_bytes = 64;
336 static const u32 hvs_latency_pix = 6;
339 case PV_CONTROL_FORMAT_DSIV_16:
340 case PV_CONTROL_FORMAT_DSIC_16:
341 return fifo_len_bytes - 2 * hvs_latency_pix;
342 case PV_CONTROL_FORMAT_DSIV_18:
343 return fifo_len_bytes - 14;
344 case PV_CONTROL_FORMAT_24:
345 case PV_CONTROL_FORMAT_DSIV_24:
347 return fifo_len_bytes - 3 * hvs_latency_pix;
352 * Returns the encoder attached to the CRTC.
354 * VC4 can only scan out to one encoder at a time, while the DRM core
355 * allows drivers to push pixels to more than one encoder from the
358 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
360 struct drm_connector *connector;
362 drm_for_each_connector(connector, crtc->dev) {
363 if (connector->state->crtc == crtc) {
364 return connector->encoder;
371 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
373 struct drm_device *dev = crtc->dev;
374 struct vc4_dev *vc4 = to_vc4_dev(dev);
375 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
376 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
377 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
378 struct drm_crtc_state *state = crtc->state;
379 struct drm_display_mode *mode = &state->adjusted_mode;
380 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
381 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
382 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
383 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
384 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
385 bool debug_dump_regs = false;
387 if (debug_dump_regs) {
388 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
389 vc4_crtc_dump_regs(vc4_crtc);
392 /* Reset the PV fifo. */
393 CRTC_WRITE(PV_CONTROL, 0);
394 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
395 CRTC_WRITE(PV_CONTROL, 0);
398 VC4_SET_FIELD((mode->htotal -
399 mode->hsync_end) * pixel_rep,
401 VC4_SET_FIELD((mode->hsync_end -
402 mode->hsync_start) * pixel_rep,
405 VC4_SET_FIELD((mode->hsync_start -
406 mode->hdisplay) * pixel_rep,
408 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
411 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
413 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
416 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
418 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
421 CRTC_WRITE(PV_VERTA_EVEN,
422 VC4_SET_FIELD(mode->crtc_vtotal -
423 mode->crtc_vsync_end - 1,
425 VC4_SET_FIELD(mode->crtc_vsync_end -
426 mode->crtc_vsync_start,
428 CRTC_WRITE(PV_VERTB_EVEN,
429 VC4_SET_FIELD(mode->crtc_vsync_start -
432 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
434 /* We set up first field even mode for HDMI. VEC's
435 * NTSC mode would want first field odd instead, once
436 * we support it (to do so, set ODD_FIRST and put the
437 * delay in VSYNCD_EVEN instead).
439 CRTC_WRITE(PV_V_CONTROL,
440 PV_VCONTROL_CONTINUOUS |
441 (is_dsi ? PV_VCONTROL_DSI : 0) |
442 PV_VCONTROL_INTERLACE |
443 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
444 PV_VCONTROL_ODD_DELAY));
445 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
447 CRTC_WRITE(PV_V_CONTROL,
448 PV_VCONTROL_CONTINUOUS |
449 (is_dsi ? PV_VCONTROL_DSI : 0));
452 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
454 CRTC_WRITE(PV_CONTROL,
455 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
456 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
457 PV_CONTROL_FIFO_LEVEL) |
458 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
459 PV_CONTROL_CLR_AT_START |
460 PV_CONTROL_TRIGGER_UNDERFLOW |
461 PV_CONTROL_WAIT_HSTART |
462 VC4_SET_FIELD(vc4_encoder->clock_select,
463 PV_CONTROL_CLK_SELECT) |
464 PV_CONTROL_FIFO_CLR |
467 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
468 SCALER_DISPBKGND_AUTOHS |
469 SCALER_DISPBKGND_GAMMA |
470 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
472 /* Reload the LUT, since the SRAMs would have been disabled if
473 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
475 vc4_crtc_lut_load(crtc);
477 if (debug_dump_regs) {
478 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
479 vc4_crtc_dump_regs(vc4_crtc);
483 static void require_hvs_enabled(struct drm_device *dev)
485 struct vc4_dev *vc4 = to_vc4_dev(dev);
487 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
488 SCALER_DISPCTRL_ENABLE);
491 static void vc4_crtc_disable(struct drm_crtc *crtc)
493 struct drm_device *dev = crtc->dev;
494 struct vc4_dev *vc4 = to_vc4_dev(dev);
495 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
496 u32 chan = vc4_crtc->channel;
498 require_hvs_enabled(dev);
500 /* Disable vblank irq handling before crtc is disabled. */
501 drm_crtc_vblank_off(crtc);
503 CRTC_WRITE(PV_V_CONTROL,
504 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
505 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
506 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
508 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
509 SCALER_DISPCTRLX_ENABLE) {
510 HVS_WRITE(SCALER_DISPCTRLX(chan),
511 SCALER_DISPCTRLX_RESET);
513 /* While the docs say that reset is self-clearing, it
514 * seems it doesn't actually.
516 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
519 /* Once we leave, the scaler should be disabled and its fifo empty. */
521 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
523 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
524 SCALER_DISPSTATX_MODE) !=
525 SCALER_DISPSTATX_MODE_DISABLED);
527 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
528 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
529 SCALER_DISPSTATX_EMPTY);
532 static void vc4_crtc_enable(struct drm_crtc *crtc)
534 struct drm_device *dev = crtc->dev;
535 struct vc4_dev *vc4 = to_vc4_dev(dev);
536 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
537 struct drm_crtc_state *state = crtc->state;
538 struct drm_display_mode *mode = &state->adjusted_mode;
540 require_hvs_enabled(dev);
542 /* Turn on the scaler, which will wait for vstart to start
545 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
546 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
547 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
548 SCALER_DISPCTRLX_ENABLE);
550 /* Turn on the pixel valve, which will emit the vstart signal. */
551 CRTC_WRITE(PV_V_CONTROL,
552 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
554 /* Enable vblank irq handling after crtc is started. */
555 drm_crtc_vblank_on(crtc);
558 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
559 const struct drm_display_mode *mode,
560 struct drm_display_mode *adjusted_mode)
562 /* Do not allow doublescan modes from user space */
563 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
564 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
572 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
573 struct drm_crtc_state *state)
575 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
576 struct drm_device *dev = crtc->dev;
577 struct vc4_dev *vc4 = to_vc4_dev(dev);
578 struct drm_plane *plane;
580 const struct drm_plane_state *plane_state;
584 /* The pixelvalve can only feed one encoder (and encoders are
585 * 1:1 with connectors.)
587 if (hweight32(state->connector_mask) > 1)
590 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
591 dlist_count += vc4_plane_dlist_size(plane_state);
593 dlist_count++; /* Account for SCALER_CTL0_END. */
595 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
596 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
598 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
605 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
606 struct drm_crtc_state *old_state)
608 struct drm_device *dev = crtc->dev;
609 struct vc4_dev *vc4 = to_vc4_dev(dev);
610 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
611 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
612 struct drm_plane *plane;
613 bool debug_dump_regs = false;
614 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
615 u32 __iomem *dlist_next = dlist_start;
617 if (debug_dump_regs) {
618 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
619 vc4_hvs_dump_state(dev);
622 /* Copy all the active planes' dlist contents to the hardware dlist. */
623 drm_atomic_crtc_for_each_plane(plane, crtc) {
624 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
627 writel(SCALER_CTL0_END, dlist_next);
630 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
632 if (crtc->state->event) {
635 crtc->state->event->pipe = drm_crtc_index(crtc);
637 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
639 spin_lock_irqsave(&dev->event_lock, flags);
640 vc4_crtc->event = crtc->state->event;
641 crtc->state->event = NULL;
643 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
644 vc4_state->mm.start);
646 spin_unlock_irqrestore(&dev->event_lock, flags);
648 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
649 vc4_state->mm.start);
652 if (debug_dump_regs) {
653 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
654 vc4_hvs_dump_state(dev);
658 static int vc4_enable_vblank(struct drm_crtc *crtc)
660 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
662 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
667 static void vc4_disable_vblank(struct drm_crtc *crtc)
669 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
671 CRTC_WRITE(PV_INTEN, 0);
674 /* Must be called with the event lock held */
675 bool vc4_event_pending(struct drm_crtc *crtc)
677 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
679 return !!vc4_crtc->event;
682 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
684 struct drm_crtc *crtc = &vc4_crtc->base;
685 struct drm_device *dev = crtc->dev;
686 struct vc4_dev *vc4 = to_vc4_dev(dev);
687 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
688 u32 chan = vc4_crtc->channel;
691 spin_lock_irqsave(&dev->event_lock, flags);
692 if (vc4_crtc->event &&
693 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
694 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
695 vc4_crtc->event = NULL;
696 drm_crtc_vblank_put(crtc);
698 spin_unlock_irqrestore(&dev->event_lock, flags);
701 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
703 struct vc4_crtc *vc4_crtc = data;
704 u32 stat = CRTC_READ(PV_INTSTAT);
705 irqreturn_t ret = IRQ_NONE;
707 if (stat & PV_INT_VFP_START) {
708 vc4_crtc->t_vblank = ktime_get();
709 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
710 drm_crtc_handle_vblank(&vc4_crtc->base);
711 vc4_crtc_handle_page_flip(vc4_crtc);
718 struct vc4_async_flip_state {
719 struct drm_crtc *crtc;
720 struct drm_framebuffer *fb;
721 struct drm_pending_vblank_event *event;
723 struct vc4_seqno_cb cb;
726 /* Called when the V3D execution for the BO being flipped to is done, so that
727 * we can actually update the plane's address to point to it.
730 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
732 struct vc4_async_flip_state *flip_state =
733 container_of(cb, struct vc4_async_flip_state, cb);
734 struct drm_crtc *crtc = flip_state->crtc;
735 struct drm_device *dev = crtc->dev;
736 struct vc4_dev *vc4 = to_vc4_dev(dev);
737 struct drm_plane *plane = crtc->primary;
739 vc4_plane_async_set_fb(plane, flip_state->fb);
740 if (flip_state->event) {
743 spin_lock_irqsave(&dev->event_lock, flags);
744 drm_crtc_send_vblank_event(crtc, flip_state->event);
745 spin_unlock_irqrestore(&dev->event_lock, flags);
748 drm_crtc_vblank_put(crtc);
749 drm_framebuffer_unreference(flip_state->fb);
752 up(&vc4->async_modeset);
755 /* Implements async (non-vblank-synced) page flips.
757 * The page flip ioctl needs to return immediately, so we grab the
758 * modeset semaphore on the pipe, and queue the address update for
759 * when V3D is done with the BO being flipped to.
761 static int vc4_async_page_flip(struct drm_crtc *crtc,
762 struct drm_framebuffer *fb,
763 struct drm_pending_vblank_event *event,
766 struct drm_device *dev = crtc->dev;
767 struct vc4_dev *vc4 = to_vc4_dev(dev);
768 struct drm_plane *plane = crtc->primary;
770 struct vc4_async_flip_state *flip_state;
771 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
772 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
774 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
778 drm_framebuffer_reference(fb);
780 flip_state->crtc = crtc;
781 flip_state->event = event;
783 /* Make sure all other async modesetes have landed. */
784 ret = down_interruptible(&vc4->async_modeset);
786 drm_framebuffer_unreference(fb);
791 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
793 /* Immediately update the plane's legacy fb pointer, so that later
794 * modeset prep sees the state that will be present when the semaphore
797 drm_atomic_set_fb_for_plane(plane->state, fb);
800 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
801 vc4_async_page_flip_complete);
803 /* Driver takes ownership of state on successful async commit. */
807 static int vc4_page_flip(struct drm_crtc *crtc,
808 struct drm_framebuffer *fb,
809 struct drm_pending_vblank_event *event,
812 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
813 return vc4_async_page_flip(crtc, fb, event, flags);
815 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
818 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
820 struct vc4_crtc_state *vc4_state;
822 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
826 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
827 return &vc4_state->base;
830 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
831 struct drm_crtc_state *state)
833 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
834 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
836 if (vc4_state->mm.allocated) {
839 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
840 drm_mm_remove_node(&vc4_state->mm);
841 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
845 drm_atomic_helper_crtc_destroy_state(crtc, state);
848 static const struct drm_crtc_funcs vc4_crtc_funcs = {
849 .set_config = drm_atomic_helper_set_config,
850 .destroy = vc4_crtc_destroy,
851 .page_flip = vc4_page_flip,
852 .set_property = NULL,
853 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
854 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
855 .reset = drm_atomic_helper_crtc_reset,
856 .atomic_duplicate_state = vc4_crtc_duplicate_state,
857 .atomic_destroy_state = vc4_crtc_destroy_state,
858 .gamma_set = vc4_crtc_gamma_set,
859 .enable_vblank = vc4_enable_vblank,
860 .disable_vblank = vc4_disable_vblank,
863 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
864 .mode_set_nofb = vc4_crtc_mode_set_nofb,
865 .disable = vc4_crtc_disable,
866 .enable = vc4_crtc_enable,
867 .mode_fixup = vc4_crtc_mode_fixup,
868 .atomic_check = vc4_crtc_atomic_check,
869 .atomic_flush = vc4_crtc_atomic_flush,
872 static const struct vc4_crtc_data pv0_data = {
875 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
876 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
880 static const struct vc4_crtc_data pv1_data = {
883 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
884 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
888 static const struct vc4_crtc_data pv2_data = {
891 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
892 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
896 static const struct of_device_id vc4_crtc_dt_match[] = {
897 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
898 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
899 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
903 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
904 struct drm_crtc *crtc)
906 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
907 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
908 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
909 struct drm_encoder *encoder;
911 drm_for_each_encoder(encoder, drm) {
912 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
915 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
916 if (vc4_encoder->type == encoder_types[i]) {
917 vc4_encoder->clock_select = i;
918 encoder->possible_crtcs |= drm_crtc_mask(crtc);
926 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
928 struct drm_device *drm = vc4_crtc->base.dev;
929 struct vc4_dev *vc4 = to_vc4_dev(drm);
930 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
931 /* Top/base are supposed to be 4-pixel aligned, but the
932 * Raspberry Pi firmware fills the low bits (which are
933 * presumably ignored).
935 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
936 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
938 vc4_crtc->cob_size = top - base + 4;
941 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
943 struct platform_device *pdev = to_platform_device(dev);
944 struct drm_device *drm = dev_get_drvdata(master);
945 struct vc4_crtc *vc4_crtc;
946 struct drm_crtc *crtc;
947 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
948 const struct of_device_id *match;
951 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
954 crtc = &vc4_crtc->base;
956 match = of_match_device(vc4_crtc_dt_match, dev);
959 vc4_crtc->data = match->data;
961 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
962 if (IS_ERR(vc4_crtc->regs))
963 return PTR_ERR(vc4_crtc->regs);
965 /* For now, we create just the primary and the legacy cursor
966 * planes. We should be able to stack more planes on easily,
967 * but to do that we would need to compute the bandwidth
968 * requirement of the plane configuration, and reject ones
969 * that will take too much.
971 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
972 if (IS_ERR(primary_plane)) {
973 dev_err(dev, "failed to construct primary plane\n");
974 ret = PTR_ERR(primary_plane);
978 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
979 &vc4_crtc_funcs, NULL);
980 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
981 primary_plane->crtc = crtc;
982 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
983 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
985 /* Set up some arbitrary number of planes. We're not limited
986 * by a set number of physical registers, just the space in
987 * the HVS (16k) and how small an plane can be (28 bytes).
988 * However, each plane we set up takes up some memory, and
989 * increases the cost of looping over planes, which atomic
990 * modesetting does quite a bit. As a result, we pick a
991 * modest number of planes to expose, that should hopefully
992 * still cover any sane usecase.
994 for (i = 0; i < 8; i++) {
995 struct drm_plane *plane =
996 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1001 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1004 /* Set up the legacy cursor after overlay initialization,
1005 * since we overlay planes on the CRTC in the order they were
1008 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1009 if (!IS_ERR(cursor_plane)) {
1010 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1011 cursor_plane->crtc = crtc;
1012 crtc->cursor = cursor_plane;
1015 vc4_crtc_get_cob_allocation(vc4_crtc);
1017 CRTC_WRITE(PV_INTEN, 0);
1018 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1019 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1020 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1022 goto err_destroy_planes;
1024 vc4_set_crtc_possible_masks(drm, crtc);
1026 for (i = 0; i < crtc->gamma_size; i++) {
1027 vc4_crtc->lut_r[i] = i;
1028 vc4_crtc->lut_g[i] = i;
1029 vc4_crtc->lut_b[i] = i;
1032 platform_set_drvdata(pdev, vc4_crtc);
1037 list_for_each_entry_safe(destroy_plane, temp,
1038 &drm->mode_config.plane_list, head) {
1039 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1040 destroy_plane->funcs->destroy(destroy_plane);
1046 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1049 struct platform_device *pdev = to_platform_device(dev);
1050 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1052 vc4_crtc_destroy(&vc4_crtc->base);
1054 CRTC_WRITE(PV_INTEN, 0);
1056 platform_set_drvdata(pdev, NULL);
1059 static const struct component_ops vc4_crtc_ops = {
1060 .bind = vc4_crtc_bind,
1061 .unbind = vc4_crtc_unbind,
1064 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1066 return component_add(&pdev->dev, &vc4_crtc_ops);
1069 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1071 component_del(&pdev->dev, &vc4_crtc_ops);
1075 struct platform_driver vc4_crtc_driver = {
1076 .probe = vc4_crtc_dev_probe,
1077 .remove = vc4_crtc_dev_remove,
1080 .of_match_table = vc4_crtc_dt_match,