drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * output's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, this file also manages
  19  * setup of the VC4 HVS's display elements on the CRTC.
  20  *
  21  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  22  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  23  * image domain can feed either HDMI or the SDTV controller.  The
  24  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  25  * SDTV, etc.) according to which output type is chosen in the mux.
  26  *
  27  * For power management, the pixel valve's registers are all clocked
  28  * by the AXI clock, while the timings and FIFOs make use of the
  29  * output-specific clock.  Since the encoders also directly consume
  30  * the CPRMAN clocks, and know what timings they need, they are the
  31  * ones that set the clock.
  32  */
  33
  34 #include "drm_atomic.h"
  35 #include "drm_atomic_helper.h"
  36 #include "drm_crtc_helper.h"
  37 #include "linux/clk.h"
  38 #include "drm_fb_cma_helper.h"
  39 #include "linux/component.h"
  40 #include "linux/of_device.h"
  41 #include "vc4_drv.h"
  42 #include "vc4_regs.h"
  43
  44 struct vc4_crtc {
  45         struct drm_crtc base;
  46         const struct vc4_crtc_data *data;
  47         void __iomem *regs;
  48
  49         /* Timestamp at start of vblank irq - unaffected by lock delays. */
  50         ktime_t t_vblank;
  51
  52         /* Which HVS channel we're using for our CRTC. */
  53         int channel;
  54
  55         u8 lut_r[256];
  56         u8 lut_g[256];
  57         u8 lut_b[256];
  58         /* Size in pixels of the COB memory allocated to this CRTC. */
  59         u32 cob_size;
  60
  61         struct drm_pending_vblank_event *event;
  62 };
  63
  64 struct vc4_crtc_state {
  65         struct drm_crtc_state base;
  66         /* Dlist area for this CRTC configuration. */
  67         struct drm_mm_node mm;
  68 };
  69
  70 static inline struct vc4_crtc *
  71 to_vc4_crtc(struct drm_crtc *crtc)
  72 {
  73         return (struct vc4_crtc *)crtc;
  74 }
  75
  76 static inline struct vc4_crtc_state *
  77 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  78 {
  79         return (struct vc4_crtc_state *)crtc_state;
  80 }
  81
  82 struct vc4_crtc_data {
  83         /* Which channel of the HVS this pixelvalve sources from. */
  84         int hvs_channel;
  85
  86         enum vc4_encoder_type encoder0_type;
  87         enum vc4_encoder_type encoder1_type;
  88 };
  89
  90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  92
  93 #define CRTC_REG(reg) { reg, #reg }
  94 static const struct {
  95         u32 reg;
  96         const char *name;
  97 } crtc_regs[] = {
  98         CRTC_REG(PV_CONTROL),
  99         CRTC_REG(PV_V_CONTROL),
 100         CRTC_REG(PV_VSYNCD_EVEN),
 101         CRTC_REG(PV_HORZA),
 102         CRTC_REG(PV_HORZB),
 103         CRTC_REG(PV_VERTA),
 104         CRTC_REG(PV_VERTB),
 105         CRTC_REG(PV_VERTA_EVEN),
 106         CRTC_REG(PV_VERTB_EVEN),
 107         CRTC_REG(PV_INTEN),
 108         CRTC_REG(PV_INTSTAT),
 109         CRTC_REG(PV_STAT),
 110         CRTC_REG(PV_HACT_ACT),
 111 };
 112
 113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
 114 {
 115         int i;
 116
 117         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 118                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 119                          crtc_regs[i].reg, crtc_regs[i].name,
 120                          CRTC_READ(crtc_regs[i].reg));
 121         }
 122 }
 123
 124 #ifdef CONFIG_DEBUG_FS
 125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
 126 {
 127         struct drm_info_node *node = (struct drm_info_node *)m->private;
 128         struct drm_device *dev = node->minor->dev;
 129         int crtc_index = (uintptr_t)node->info_ent->data;
 130         struct drm_crtc *crtc;
 131         struct vc4_crtc *vc4_crtc;
 132         int i;
 133
 134         i = 0;
 135         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 136                 if (i == crtc_index)
 137                         break;
 138                 i++;
 139         }
 140         if (!crtc)
 141                 return 0;
 142         vc4_crtc = to_vc4_crtc(crtc);
 143
 144         for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
 145                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 146                            crtc_regs[i].name, crtc_regs[i].reg,
 147                            CRTC_READ(crtc_regs[i].reg));
 148         }
 149
 150         return 0;
 151 }
 152 #endif
 153
 154 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
 155                             unsigned int flags, int *vpos, int *hpos,
 156                             ktime_t *stime, ktime_t *etime,
 157                             const struct drm_display_mode *mode)
 158 {
 159         struct vc4_dev *vc4 = to_vc4_dev(dev);
 160         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 161         u32 val;
 162         int fifo_lines;
 163         int vblank_lines;
 164         int ret = 0;
 165
 166         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 167
 168         /* Get optional system timestamp before query. */
 169         if (stime)
 170                 *stime = ktime_get();
 171
 172         /*
 173          * Read vertical scanline which is currently composed for our
 174          * pixelvalve by the HVS, and also the scaler status.
 175          */
 176         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 177
 178         /* Get optional system timestamp after query. */
 179         if (etime)
 180                 *etime = ktime_get();
 181
 182         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 183
 184         /* Vertical position of hvs composed scanline. */
 185         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 186         *hpos = 0;
 187
 188         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 189                 *vpos /= 2;
 190
 191                 /* Use hpos to correct for field offset in interlaced mode. */
 192                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 193                         *hpos += mode->crtc_htotal / 2;
 194         }
 195
 196         /* This is the offset we need for translating hvs -> pv scanout pos. */
 197         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 198
 199         if (fifo_lines > 0)
 200                 ret |= DRM_SCANOUTPOS_VALID;
 201
 202         /* HVS more than fifo_lines into frame for compositing? */
 203         if (*vpos > fifo_lines) {
 204                 /*
 205                  * We are in active scanout and can get some meaningful results
 206                  * from HVS. The actual PV scanout can not trail behind more
 207                  * than fifo_lines as that is the fifo's capacity. Assume that
 208                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 209                  * refilling the fifo and PV consuming from the fifo, ie.
 210                  * whenever the PV consumes and frees up a scanline in the
 211                  * fifo, the HVS will immediately refill it, therefore
 212                  * incrementing vpos. Therefore we choose HVS read position -
 213                  * fifo size in scanlines as a estimate of the real scanout
 214                  * position of the PV.
 215                  */
 216                 *vpos -= fifo_lines + 1;
 217
 218                 ret |= DRM_SCANOUTPOS_ACCURATE;
 219                 return ret;
 220         }
 221
 222         /*
 223          * Less: This happens when we are in vblank and the HVS, after getting
 224          * the VSTART restart signal from the PV, just started refilling its
 225          * fifo with new lines from the top-most lines of the new framebuffers.
 226          * The PV does not scan out in vblank, so does not remove lines from
 227          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 228          * We can't get meaningful readings wrt. scanline position of the PV
 229          * and need to make things up in a approximative but consistent way.
 230          */
 231         ret |= DRM_SCANOUTPOS_IN_VBLANK;
 232         vblank_lines = mode->crtc_vtotal - mode->crtc_vdisplay;
 233
 234         if (flags & DRM_CALLED_FROM_VBLIRQ) {
 235                 /*
 236                  * Assume the irq handler got called close to first
 237                  * line of vblank, so PV has about a full vblank
 238                  * scanlines to go, and as a base timestamp use the
 239                  * one taken at entry into vblank irq handler, so it
 240                  * is not affected by random delays due to lock
 241                  * contention on event_lock or vblank_time lock in
 242                  * the core.
 243                  */
 244                 *vpos = -vblank_lines;
 245
 246                 if (stime)
 247                         *stime = vc4_crtc->t_vblank;
 248                 if (etime)
 249                         *etime = vc4_crtc->t_vblank;
 250
 251                 /*
 252                  * If the HVS fifo is not yet full then we know for certain
 253                  * we are at the very beginning of vblank, as the hvs just
 254                  * started refilling, and the stime and etime timestamps
 255                  * truly correspond to start of vblank.
 256                  */
 257                 if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
 258                         ret |= DRM_SCANOUTPOS_ACCURATE;
 259         } else {
 260                 /*
 261                  * No clue where we are inside vblank. Return a vpos of zero,
 262                  * which will cause calling code to just return the etime
 263                  * timestamp uncorrected. At least this is no worse than the
 264                  * standard fallback.
 265                  */
 266                 *vpos = 0;
 267         }
 268
 269         return ret;
 270 }
 271
 272 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
 273                                   int *max_error, struct timeval *vblank_time,
 274                                   unsigned flags)
 275 {
 276         struct vc4_dev *vc4 = to_vc4_dev(dev);
 277         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 278         struct drm_crtc *crtc = &vc4_crtc->base;
 279         struct drm_crtc_state *state = crtc->state;
 280
 281         /* Helper routine in DRM core does all the work: */
 282         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
 283                                                      vblank_time, flags,
 284                                                      &state->adjusted_mode);
 285 }
 286
 287 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 288 {
 289         drm_crtc_cleanup(crtc);
 290 }
 291
 292 static void
 293 vc4_crtc_lut_load(struct drm_crtc *crtc)
 294 {
 295         struct drm_device *dev = crtc->dev;
 296         struct vc4_dev *vc4 = to_vc4_dev(dev);
 297         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 298         u32 i;
 299
 300         /* The LUT memory is laid out with each HVS channel in order,
 301          * each of which takes 256 writes for R, 256 for G, then 256
 302          * for B.
 303          */
 304         HVS_WRITE(SCALER_GAMADDR,
 305                   SCALER_GAMADDR_AUTOINC |
 306                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 307
 308         for (i = 0; i < crtc->gamma_size; i++)
 309                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 310         for (i = 0; i < crtc->gamma_size; i++)
 311                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 312         for (i = 0; i < crtc->gamma_size; i++)
 313                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 314 }
 315
 316 static int
 317 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 318                    uint32_t size)
 319 {
 320         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 321         u32 i;
 322
 323         for (i = 0; i < size; i++) {
 324                 vc4_crtc->lut_r[i] = r[i] >> 8;
 325                 vc4_crtc->lut_g[i] = g[i] >> 8;
 326                 vc4_crtc->lut_b[i] = b[i] >> 8;
 327         }
 328
 329         vc4_crtc_lut_load(crtc);
 330
 331         return 0;
 332 }
 333
 334 static u32 vc4_get_fifo_full_level(u32 format)
 335 {
 336         static const u32 fifo_len_bytes = 64;
 337         static const u32 hvs_latency_pix = 6;
 338
 339         switch (format) {
 340         case PV_CONTROL_FORMAT_DSIV_16:
 341         case PV_CONTROL_FORMAT_DSIC_16:
 342                 return fifo_len_bytes - 2 * hvs_latency_pix;
 343         case PV_CONTROL_FORMAT_DSIV_18:
 344                 return fifo_len_bytes - 14;
 345         case PV_CONTROL_FORMAT_24:
 346         case PV_CONTROL_FORMAT_DSIV_24:
 347         default:
 348                 return fifo_len_bytes - 3 * hvs_latency_pix;
 349         }
 350 }
 351
 352 /*
 353  * Returns the clock select bit for the connector attached to the
 354  * CRTC.
 355  */
 356 static int vc4_get_clock_select(struct drm_crtc *crtc)
 357 {
 358         struct drm_connector *connector;
 359
 360         drm_for_each_connector(connector, crtc->dev) {
 361                 if (connector->state->crtc == crtc) {
 362                         struct drm_encoder *encoder = connector->encoder;
 363                         struct vc4_encoder *vc4_encoder =
 364                                 to_vc4_encoder(encoder);
 365
 366                         return vc4_encoder->clock_select;
 367                 }
 368         }
 369
 370         return -1;
 371 }
 372
 373 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 374 {
 375         struct drm_device *dev = crtc->dev;
 376         struct vc4_dev *vc4 = to_vc4_dev(dev);
 377         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 378         struct drm_crtc_state *state = crtc->state;
 379         struct drm_display_mode *mode = &state->adjusted_mode;
 380         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 381         u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
 382         u32 format = PV_CONTROL_FORMAT_24;
 383         bool debug_dump_regs = false;
 384         int clock_select = vc4_get_clock_select(crtc);
 385
 386         if (debug_dump_regs) {
 387                 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
 388                 vc4_crtc_dump_regs(vc4_crtc);
 389         }
 390
 391         /* Reset the PV fifo. */
 392         CRTC_WRITE(PV_CONTROL, 0);
 393         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 394         CRTC_WRITE(PV_CONTROL, 0);
 395
 396         CRTC_WRITE(PV_HORZA,
 397                    VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 398                                  PV_HORZA_HBP) |
 399                    VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 400                                  PV_HORZA_HSYNC));
 401         CRTC_WRITE(PV_HORZB,
 402                    VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 403                                  PV_HORZB_HFP) |
 404                    VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
 405
 406         CRTC_WRITE(PV_VERTA,
 407                    VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
 408                                  PV_VERTA_VBP) |
 409                    VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 410                                  PV_VERTA_VSYNC));
 411         CRTC_WRITE(PV_VERTB,
 412                    VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 413                                  PV_VERTB_VFP) |
 414                    VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
 415
 416         if (interlace) {
 417                 CRTC_WRITE(PV_VERTA_EVEN,
 418                            VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
 419                                          PV_VERTA_VBP) |
 420                            VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 421                                          PV_VERTA_VSYNC));
 422                 CRTC_WRITE(PV_VERTB_EVEN,
 423                            VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 424                                          PV_VERTB_VFP) |
 425                            VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
 426         }
 427
 428         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
 429
 430         CRTC_WRITE(PV_V_CONTROL,
 431                    PV_VCONTROL_CONTINUOUS |
 432                    (interlace ? PV_VCONTROL_INTERLACE : 0));
 433
 434         CRTC_WRITE(PV_CONTROL,
 435                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 436                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 437                                  PV_CONTROL_FIFO_LEVEL) |
 438                    PV_CONTROL_CLR_AT_START |
 439                    PV_CONTROL_TRIGGER_UNDERFLOW |
 440                    PV_CONTROL_WAIT_HSTART |
 441                    VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
 442                    PV_CONTROL_FIFO_CLR |
 443                    PV_CONTROL_EN);
 444
 445         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 446                   SCALER_DISPBKGND_AUTOHS |
 447                   SCALER_DISPBKGND_GAMMA |
 448                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 449
 450         /* Reload the LUT, since the SRAMs would have been disabled if
 451          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 452          */
 453         vc4_crtc_lut_load(crtc);
 454
 455         if (debug_dump_regs) {
 456                 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
 457                 vc4_crtc_dump_regs(vc4_crtc);
 458         }
 459 }
 460
 461 static void require_hvs_enabled(struct drm_device *dev)
 462 {
 463         struct vc4_dev *vc4 = to_vc4_dev(dev);
 464
 465         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 466                      SCALER_DISPCTRL_ENABLE);
 467 }
 468
 469 static void vc4_crtc_disable(struct drm_crtc *crtc)
 470 {
 471         struct drm_device *dev = crtc->dev;
 472         struct vc4_dev *vc4 = to_vc4_dev(dev);
 473         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 474         u32 chan = vc4_crtc->channel;
 475         int ret;
 476         require_hvs_enabled(dev);
 477
 478         /* Disable vblank irq handling before crtc is disabled. */
 479         drm_crtc_vblank_off(crtc);
 480
 481         CRTC_WRITE(PV_V_CONTROL,
 482                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 483         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 484         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 485
 486         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 487             SCALER_DISPCTRLX_ENABLE) {
 488                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 489                           SCALER_DISPCTRLX_RESET);
 490
 491                 /* While the docs say that reset is self-clearing, it
 492                  * seems it doesn't actually.
 493                  */
 494                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 495         }
 496
 497         /* Once we leave, the scaler should be disabled and its fifo empty. */
 498
 499         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 500
 501         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 502                                    SCALER_DISPSTATX_MODE) !=
 503                      SCALER_DISPSTATX_MODE_DISABLED);
 504
 505         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 506                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 507                      SCALER_DISPSTATX_EMPTY);
 508 }
 509
 510 static void vc4_crtc_enable(struct drm_crtc *crtc)
 511 {
 512         struct drm_device *dev = crtc->dev;
 513         struct vc4_dev *vc4 = to_vc4_dev(dev);
 514         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 515         struct drm_crtc_state *state = crtc->state;
 516         struct drm_display_mode *mode = &state->adjusted_mode;
 517
 518         require_hvs_enabled(dev);
 519
 520         /* Turn on the scaler, which will wait for vstart to start
 521          * compositing.
 522          */
 523         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 524                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 525                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 526                   SCALER_DISPCTRLX_ENABLE);
 527
 528         /* Turn on the pixel valve, which will emit the vstart signal. */
 529         CRTC_WRITE(PV_V_CONTROL,
 530                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 531
 532         /* Enable vblank irq handling after crtc is started. */
 533         drm_crtc_vblank_on(crtc);
 534 }
 535
 536 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
 537                                 const struct drm_display_mode *mode,
 538                                 struct drm_display_mode *adjusted_mode)
 539 {
 540         /* Do not allow doublescan modes from user space */
 541         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 542                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 543                               crtc->base.id);
 544                 return false;
 545         }
 546
 547         /*
 548          * Interlaced video modes got CRTC_INTERLACE_HALVE_V applied when
 549          * coming from user space. We don't want this, as it screws up
 550          * vblank timestamping, so fix it up.
 551          */
 552         drm_mode_set_crtcinfo(adjusted_mode, 0);
 553
 554         DRM_DEBUG_KMS("[CRTC:%d] adjusted_mode :\n", crtc->base.id);
 555         drm_mode_debug_printmodeline(adjusted_mode);
 556
 557         return true;
 558 }
 559
 560 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 561                                  struct drm_crtc_state *state)
 562 {
 563         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 564         struct drm_device *dev = crtc->dev;
 565         struct vc4_dev *vc4 = to_vc4_dev(dev);
 566         struct drm_plane *plane;
 567         unsigned long flags;
 568         const struct drm_plane_state *plane_state;
 569         u32 dlist_count = 0;
 570         int ret;
 571
 572         /* The pixelvalve can only feed one encoder (and encoders are
 573          * 1:1 with connectors.)
 574          */
 575         if (hweight32(state->connector_mask) > 1)
 576                 return -EINVAL;
 577
 578         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 579                 dlist_count += vc4_plane_dlist_size(plane_state);
 580
 581         dlist_count++; /* Account for SCALER_CTL0_END. */
 582
 583         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 584         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 585                                  dlist_count, 1, 0);
 586         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 587         if (ret)
 588                 return ret;
 589
 590         return 0;
 591 }
 592
 593 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 594                                   struct drm_crtc_state *old_state)
 595 {
 596         struct drm_device *dev = crtc->dev;
 597         struct vc4_dev *vc4 = to_vc4_dev(dev);
 598         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 599         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 600         struct drm_plane *plane;
 601         bool debug_dump_regs = false;
 602         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 603         u32 __iomem *dlist_next = dlist_start;
 604
 605         if (debug_dump_regs) {
 606                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 607                 vc4_hvs_dump_state(dev);
 608         }
 609
 610         /* Copy all the active planes' dlist contents to the hardware dlist. */
 611         drm_atomic_crtc_for_each_plane(plane, crtc) {
 612                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 613         }
 614
 615         writel(SCALER_CTL0_END, dlist_next);
 616         dlist_next++;
 617
 618         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 619
 620         if (crtc->state->event) {
 621                 unsigned long flags;
 622
 623                 crtc->state->event->pipe = drm_crtc_index(crtc);
 624
 625                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 626
 627                 spin_lock_irqsave(&dev->event_lock, flags);
 628                 vc4_crtc->event = crtc->state->event;
 629                 crtc->state->event = NULL;
 630
 631                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 632                           vc4_state->mm.start);
 633
 634                 spin_unlock_irqrestore(&dev->event_lock, flags);
 635         } else {
 636                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 637                           vc4_state->mm.start);
 638         }
 639
 640         if (debug_dump_regs) {
 641                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 642                 vc4_hvs_dump_state(dev);
 643         }
 644 }
 645
 646 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
 647 {
 648         struct vc4_dev *vc4 = to_vc4_dev(dev);
 649         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 650
 651         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 652
 653         return 0;
 654 }
 655
 656 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
 657 {
 658         struct vc4_dev *vc4 = to_vc4_dev(dev);
 659         struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
 660
 661         CRTC_WRITE(PV_INTEN, 0);
 662 }
 663
 664 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 665 {
 666         struct drm_crtc *crtc = &vc4_crtc->base;
 667         struct drm_device *dev = crtc->dev;
 668         struct vc4_dev *vc4 = to_vc4_dev(dev);
 669         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 670         u32 chan = vc4_crtc->channel;
 671         unsigned long flags;
 672
 673         spin_lock_irqsave(&dev->event_lock, flags);
 674         if (vc4_crtc->event &&
 675             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 676                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 677                 vc4_crtc->event = NULL;
 678                 drm_crtc_vblank_put(crtc);
 679         }
 680         spin_unlock_irqrestore(&dev->event_lock, flags);
 681 }
 682
 683 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 684 {
 685         struct vc4_crtc *vc4_crtc = data;
 686         u32 stat = CRTC_READ(PV_INTSTAT);
 687         irqreturn_t ret = IRQ_NONE;
 688
 689         if (stat & PV_INT_VFP_START) {
 690                 vc4_crtc->t_vblank = ktime_get();
 691                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 692                 drm_crtc_handle_vblank(&vc4_crtc->base);
 693                 vc4_crtc_handle_page_flip(vc4_crtc);
 694                 ret = IRQ_HANDLED;
 695         }
 696
 697         return ret;
 698 }
 699
 700 struct vc4_async_flip_state {
 701         struct drm_crtc *crtc;
 702         struct drm_framebuffer *fb;
 703         struct drm_pending_vblank_event *event;
 704
 705         struct vc4_seqno_cb cb;
 706 };
 707
 708 /* Called when the V3D execution for the BO being flipped to is done, so that
 709  * we can actually update the plane's address to point to it.
 710  */
 711 static void
 712 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 713 {
 714         struct vc4_async_flip_state *flip_state =
 715                 container_of(cb, struct vc4_async_flip_state, cb);
 716         struct drm_crtc *crtc = flip_state->crtc;
 717         struct drm_device *dev = crtc->dev;
 718         struct vc4_dev *vc4 = to_vc4_dev(dev);
 719         struct drm_plane *plane = crtc->primary;
 720
 721         vc4_plane_async_set_fb(plane, flip_state->fb);
 722         if (flip_state->event) {
 723                 unsigned long flags;
 724
 725                 spin_lock_irqsave(&dev->event_lock, flags);
 726                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 727                 spin_unlock_irqrestore(&dev->event_lock, flags);
 728         }
 729
 730         drm_crtc_vblank_put(crtc);
 731         drm_framebuffer_unreference(flip_state->fb);
 732         kfree(flip_state);
 733
 734         up(&vc4->async_modeset);
 735 }
 736
 737 /* Implements async (non-vblank-synced) page flips.
 738  *
 739  * The page flip ioctl needs to return immediately, so we grab the
 740  * modeset semaphore on the pipe, and queue the address update for
 741  * when V3D is done with the BO being flipped to.
 742  */
 743 static int vc4_async_page_flip(struct drm_crtc *crtc,
 744                                struct drm_framebuffer *fb,
 745                                struct drm_pending_vblank_event *event,
 746                                uint32_t flags)
 747 {
 748         struct drm_device *dev = crtc->dev;
 749         struct vc4_dev *vc4 = to_vc4_dev(dev);
 750         struct drm_plane *plane = crtc->primary;
 751         int ret = 0;
 752         struct vc4_async_flip_state *flip_state;
 753         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 754         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 755
 756         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 757         if (!flip_state)
 758                 return -ENOMEM;
 759
 760         drm_framebuffer_reference(fb);
 761         flip_state->fb = fb;
 762         flip_state->crtc = crtc;
 763         flip_state->event = event;
 764
 765         /* Make sure all other async modesetes have landed. */
 766         ret = down_interruptible(&vc4->async_modeset);
 767         if (ret) {
 768                 drm_framebuffer_unreference(fb);
 769                 kfree(flip_state);
 770                 return ret;
 771         }
 772
 773         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 774
 775         /* Immediately update the plane's legacy fb pointer, so that later
 776          * modeset prep sees the state that will be present when the semaphore
 777          * is released.
 778          */
 779         drm_atomic_set_fb_for_plane(plane->state, fb);
 780         plane->fb = fb;
 781
 782         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 783                            vc4_async_page_flip_complete);
 784
 785         /* Driver takes ownership of state on successful async commit. */
 786         return 0;
 787 }
 788
 789 static int vc4_page_flip(struct drm_crtc *crtc,
 790                          struct drm_framebuffer *fb,
 791                          struct drm_pending_vblank_event *event,
 792                          uint32_t flags)
 793 {
 794         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 795                 return vc4_async_page_flip(crtc, fb, event, flags);
 796         else
 797                 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
 798 }
 799
 800 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 801 {
 802         struct vc4_crtc_state *vc4_state;
 803
 804         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 805         if (!vc4_state)
 806                 return NULL;
 807
 808         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 809         return &vc4_state->base;
 810 }
 811
 812 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 813                                    struct drm_crtc_state *state)
 814 {
 815         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 816         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 817
 818         if (vc4_state->mm.allocated) {
 819                 unsigned long flags;
 820
 821                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 822                 drm_mm_remove_node(&vc4_state->mm);
 823                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 824
 825         }
 826
 827         __drm_atomic_helper_crtc_destroy_state(state);
 828 }
 829
 830 static const struct drm_crtc_funcs vc4_crtc_funcs = {
 831         .set_config = drm_atomic_helper_set_config,
 832         .destroy = vc4_crtc_destroy,
 833         .page_flip = vc4_page_flip,
 834         .set_property = NULL,
 835         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
 836         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
 837         .reset = drm_atomic_helper_crtc_reset,
 838         .atomic_duplicate_state = vc4_crtc_duplicate_state,
 839         .atomic_destroy_state = vc4_crtc_destroy_state,
 840         .gamma_set = vc4_crtc_gamma_set,
 841 };
 842
 843 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
 844         .mode_set_nofb = vc4_crtc_mode_set_nofb,
 845         .disable = vc4_crtc_disable,
 846         .enable = vc4_crtc_enable,
 847         .mode_fixup = vc4_crtc_mode_fixup,
 848         .atomic_check = vc4_crtc_atomic_check,
 849         .atomic_flush = vc4_crtc_atomic_flush,
 850 };
 851
 852 static const struct vc4_crtc_data pv0_data = {
 853         .hvs_channel = 0,
 854         .encoder0_type = VC4_ENCODER_TYPE_DSI0,
 855         .encoder1_type = VC4_ENCODER_TYPE_DPI,
 856 };
 857
 858 static const struct vc4_crtc_data pv1_data = {
 859         .hvs_channel = 2,
 860         .encoder0_type = VC4_ENCODER_TYPE_DSI1,
 861         .encoder1_type = VC4_ENCODER_TYPE_SMI,
 862 };
 863
 864 static const struct vc4_crtc_data pv2_data = {
 865         .hvs_channel = 1,
 866         .encoder0_type = VC4_ENCODER_TYPE_VEC,
 867         .encoder1_type = VC4_ENCODER_TYPE_HDMI,
 868 };
 869
 870 static const struct of_device_id vc4_crtc_dt_match[] = {
 871         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
 872         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
 873         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
 874         {}
 875 };
 876
 877 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
 878                                         struct drm_crtc *crtc)
 879 {
 880         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 881         struct drm_encoder *encoder;
 882
 883         drm_for_each_encoder(encoder, drm) {
 884                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 885
 886                 if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
 887                         vc4_encoder->clock_select = 0;
 888                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 889                 } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
 890                         vc4_encoder->clock_select = 1;
 891                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
 892                 }
 893         }
 894 }
 895
 896 static void
 897 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
 898 {
 899         struct drm_device *drm = vc4_crtc->base.dev;
 900         struct vc4_dev *vc4 = to_vc4_dev(drm);
 901         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
 902         /* Top/base are supposed to be 4-pixel aligned, but the
 903          * Raspberry Pi firmware fills the low bits (which are
 904          * presumably ignored).
 905          */
 906         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
 907         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
 908
 909         vc4_crtc->cob_size = top - base + 4;
 910 }
 911
 912 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
 913 {
 914         struct platform_device *pdev = to_platform_device(dev);
 915         struct drm_device *drm = dev_get_drvdata(master);
 916         struct vc4_dev *vc4 = to_vc4_dev(drm);
 917         struct vc4_crtc *vc4_crtc;
 918         struct drm_crtc *crtc;
 919         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
 920         const struct of_device_id *match;
 921         int ret, i;
 922
 923         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
 924         if (!vc4_crtc)
 925                 return -ENOMEM;
 926         crtc = &vc4_crtc->base;
 927
 928         match = of_match_device(vc4_crtc_dt_match, dev);
 929         if (!match)
 930                 return -ENODEV;
 931         vc4_crtc->data = match->data;
 932
 933         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
 934         if (IS_ERR(vc4_crtc->regs))
 935                 return PTR_ERR(vc4_crtc->regs);
 936
 937         /* For now, we create just the primary and the legacy cursor
 938          * planes.  We should be able to stack more planes on easily,
 939          * but to do that we would need to compute the bandwidth
 940          * requirement of the plane configuration, and reject ones
 941          * that will take too much.
 942          */
 943         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
 944         if (IS_ERR(primary_plane)) {
 945                 dev_err(dev, "failed to construct primary plane\n");
 946                 ret = PTR_ERR(primary_plane);
 947                 goto err;
 948         }
 949
 950         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
 951                                   &vc4_crtc_funcs, NULL);
 952         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
 953         primary_plane->crtc = crtc;
 954         vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
 955         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
 956         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
 957
 958         /* Set up some arbitrary number of planes.  We're not limited
 959          * by a set number of physical registers, just the space in
 960          * the HVS (16k) and how small an plane can be (28 bytes).
 961          * However, each plane we set up takes up some memory, and
 962          * increases the cost of looping over planes, which atomic
 963          * modesetting does quite a bit.  As a result, we pick a
 964          * modest number of planes to expose, that should hopefully
 965          * still cover any sane usecase.
 966          */
 967         for (i = 0; i < 8; i++) {
 968                 struct drm_plane *plane =
 969                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
 970
 971                 if (IS_ERR(plane))
 972                         continue;
 973
 974                 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
 975         }
 976
 977         /* Set up the legacy cursor after overlay initialization,
 978          * since we overlay planes on the CRTC in the order they were
 979          * initialized.
 980          */
 981         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
 982         if (!IS_ERR(cursor_plane)) {
 983                 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
 984                 cursor_plane->crtc = crtc;
 985                 crtc->cursor = cursor_plane;
 986         }
 987
 988         vc4_crtc_get_cob_allocation(vc4_crtc);
 989
 990         CRTC_WRITE(PV_INTEN, 0);
 991         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 992         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 993                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
 994         if (ret)
 995                 goto err_destroy_planes;
 996
 997         vc4_set_crtc_possible_masks(drm, crtc);
 998
 999         for (i = 0; i < crtc->gamma_size; i++) {
1000                 vc4_crtc->lut_r[i] = i;
1001                 vc4_crtc->lut_g[i] = i;
1002                 vc4_crtc->lut_b[i] = i;
1003         }
1004
1005         platform_set_drvdata(pdev, vc4_crtc);
1006
1007         return 0;
1008
1009 err_destroy_planes:
1010         list_for_each_entry_safe(destroy_plane, temp,
1011                                  &drm->mode_config.plane_list, head) {
1012                 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1013                     destroy_plane->funcs->destroy(destroy_plane);
1014         }
1015 err:
1016         return ret;
1017 }
1018
1019 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1020                             void *data)
1021 {
1022         struct platform_device *pdev = to_platform_device(dev);
1023         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1024
1025         vc4_crtc_destroy(&vc4_crtc->base);
1026
1027         CRTC_WRITE(PV_INTEN, 0);
1028
1029         platform_set_drvdata(pdev, NULL);
1030 }
1031
1032 static const struct component_ops vc4_crtc_ops = {
1033         .bind   = vc4_crtc_bind,
1034         .unbind = vc4_crtc_unbind,
1035 };
1036
1037 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1038 {
1039         return component_add(&pdev->dev, &vc4_crtc_ops);
1040 }
1041
1042 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1043 {
1044         component_del(&pdev->dev, &vc4_crtc_ops);
1045         return 0;
1046 }
1047
1048 struct platform_driver vc4_crtc_driver = {
1049         .probe = vc4_crtc_dev_probe,
1050         .remove = vc4_crtc_dev_remove,
1051         .driver = {
1052                 .name = "vc4_crtc",
1053                 .of_match_table = vc4_crtc_dt_match,
1054         },
1055 };