2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/reservation.h>
11 #include <drm/drm_encoder.h>
12 #include <drm/drm_gem_cma_helper.h>
15 struct drm_device *dev;
17 struct vc4_hdmi *hdmi;
24 struct drm_fbdev_cma *fbdev;
26 struct vc4_hang_state *hang_state;
28 /* The kernel-space BO cache. Tracks buffers that have been
29 * unreferenced by all other users (refcounts of 0!) but not
30 * yet freed, so we can do cheap allocations.
33 /* Array of list heads for entries in the BO cache,
34 * based on number of pages, so we can do O(1) lookups
35 * in the cache when allocating.
37 struct list_head *size_list;
38 uint32_t size_list_size;
40 /* List of all BOs in the cache, ordered by age, so we
41 * can do O(1) lookups when trying to free old
44 struct list_head time_list;
45 struct work_struct time_work;
46 struct timer_list time_timer;
56 /* Protects bo_cache and the BO stats. */
59 uint64_t dma_fence_context;
61 /* Sequence number for the last job queued in bin_job_list.
62 * Starts at 0 (no jobs emitted).
66 /* Sequence number for the last completed job on the GPU.
67 * Starts at 0 (no jobs completed).
69 uint64_t finished_seqno;
71 /* List of all struct vc4_exec_info for jobs to be executed in
72 * the binner. The first job in the list is the one currently
73 * programmed into ct0ca for execution.
75 struct list_head bin_job_list;
77 /* List of all struct vc4_exec_info for jobs that have
78 * completed binning and are ready for rendering. The first
79 * job in the list is the one currently programmed into ct1ca
82 struct list_head render_job_list;
84 /* List of the finished vc4_exec_infos waiting to be freed by
87 struct list_head job_done_list;
88 /* Spinlock used to synchronize the job_list and seqno
89 * accesses between the IRQ handler and GEM ioctls.
92 wait_queue_head_t job_wait_queue;
93 struct work_struct job_done_work;
95 /* List of struct vc4_seqno_cb for callbacks to be made from a
96 * workqueue when the given seqno is passed.
98 struct list_head seqno_cb_list;
100 /* The memory used for storing binner tile alloc, tile state,
101 * and overflow memory allocations. This is freed when V3D
104 struct vc4_bo *bin_bo;
106 /* Size of blocks allocated within bin_bo. */
107 uint32_t bin_alloc_size;
109 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
112 uint32_t bin_alloc_used;
114 /* Bitmask of the current bin_alloc used for overflow memory. */
115 uint32_t bin_alloc_overflow;
117 struct work_struct overflow_mem_work;
121 /* Mutex controlling the power refcount. */
122 struct mutex power_lock;
125 struct timer_list timer;
126 struct work_struct reset_work;
129 struct semaphore async_modeset;
132 static inline struct vc4_dev *
133 to_vc4_dev(struct drm_device *dev)
135 return (struct vc4_dev *)dev->dev_private;
139 struct drm_gem_cma_object base;
141 /* seqno of the last job to render using this BO. */
144 /* seqno of the last job to use the RCL to write to this BO.
146 * Note that this doesn't include binner overflow memory
149 uint64_t write_seqno;
151 /* List entry for the BO's position in either
152 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
154 struct list_head unref_head;
156 /* Time in jiffies when the BO was put in vc4->bo_cache. */
157 unsigned long free_time;
159 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
160 struct list_head size_head;
162 /* Struct for shader validation state, if created by
163 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
165 struct vc4_validated_shader_info *validated_shader;
167 /* normally (resv == &_resv) except for imported bo's */
168 struct reservation_object *resv;
169 struct reservation_object _resv;
172 static inline struct vc4_bo *
173 to_vc4_bo(struct drm_gem_object *bo)
175 return (struct vc4_bo *)bo;
179 struct dma_fence base;
180 struct drm_device *dev;
181 /* vc4 seqno for signaled() test */
185 static inline struct vc4_fence *
186 to_vc4_fence(struct dma_fence *fence)
188 return (struct vc4_fence *)fence;
191 struct vc4_seqno_cb {
192 struct work_struct work;
194 void (*func)(struct vc4_seqno_cb *cb);
199 struct platform_device *pdev;
205 struct platform_device *pdev;
209 /* Memory manager for CRTCs to allocate space in the display
210 * list. Units are dwords.
212 struct drm_mm dlist_mm;
213 /* Memory manager for the LBM memory used by HVS scaling. */
214 struct drm_mm lbm_mm;
217 struct drm_mm_node mitchell_netravali_filter;
221 struct drm_plane base;
224 static inline struct vc4_plane *
225 to_vc4_plane(struct drm_plane *plane)
227 return (struct vc4_plane *)plane;
230 enum vc4_encoder_type {
231 VC4_ENCODER_TYPE_NONE,
232 VC4_ENCODER_TYPE_HDMI,
233 VC4_ENCODER_TYPE_VEC,
234 VC4_ENCODER_TYPE_DSI0,
235 VC4_ENCODER_TYPE_DSI1,
236 VC4_ENCODER_TYPE_SMI,
237 VC4_ENCODER_TYPE_DPI,
241 struct drm_encoder base;
242 enum vc4_encoder_type type;
246 static inline struct vc4_encoder *
247 to_vc4_encoder(struct drm_encoder *encoder)
249 return container_of(encoder, struct vc4_encoder, base);
252 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
253 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
254 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
255 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
257 struct vc4_exec_info {
258 /* Sequence number for this bin/render job. */
261 /* Latest write_seqno of any BO that binning depends on. */
262 uint64_t bin_dep_seqno;
264 struct dma_fence *fence;
266 /* Last current addresses the hardware was processing when the
267 * hangcheck timer checked on us.
269 uint32_t last_ct0ca, last_ct1ca;
271 /* Kernel-space copy of the ioctl arguments */
272 struct drm_vc4_submit_cl *args;
274 /* This is the array of BOs that were looked up at the start of exec.
275 * Command validation will use indices into this array.
277 struct drm_gem_cma_object **bo;
280 /* List of BOs that are being written by the RCL. Other than
281 * the binner temporary storage, this is all the BOs written
284 struct drm_gem_cma_object *rcl_write_bo[4];
285 uint32_t rcl_write_bo_count;
287 /* Pointers for our position in vc4->job_list */
288 struct list_head head;
290 /* List of other BOs used in the job that need to be released
291 * once the job is complete.
293 struct list_head unref_list;
295 /* Current unvalidated indices into @bo loaded by the non-hardware
296 * VC4_PACKET_GEM_HANDLES.
298 uint32_t bo_index[2];
300 /* This is the BO where we store the validated command lists, shader
301 * records, and uniforms.
303 struct drm_gem_cma_object *exec_bo;
306 * This tracks the per-shader-record state (packet 64) that
307 * determines the length of the shader record and the offset
308 * it's expected to be found at. It gets read in from the
311 struct vc4_shader_state {
313 /* Maximum vertex index referenced by any primitive using this
319 /** How many shader states the user declared they were using. */
320 uint32_t shader_state_size;
321 /** How many shader state records the validator has seen. */
322 uint32_t shader_state_count;
324 bool found_tile_binning_mode_config_packet;
325 bool found_start_tile_binning_packet;
326 bool found_increment_semaphore_packet;
328 uint8_t bin_tiles_x, bin_tiles_y;
329 /* Physical address of the start of the tile alloc array
330 * (where each tile's binned CL will start)
332 uint32_t tile_alloc_offset;
333 /* Bitmask of which binner slots are freed when this job completes. */
337 * Computed addresses pointing into exec_bo where we start the
338 * bin thread (ct0) and render thread (ct1).
340 uint32_t ct0ca, ct0ea;
341 uint32_t ct1ca, ct1ea;
343 /* Pointer to the unvalidated bin CL (if present). */
346 /* Pointers to the shader recs. These paddr gets incremented as CL
347 * packets are relocated in validate_gl_shader_state, and the vaddrs
348 * (u and v) get incremented and size decremented as the shader recs
349 * themselves are validated.
353 uint32_t shader_rec_p;
354 uint32_t shader_rec_size;
356 /* Pointers to the uniform data. These pointers are incremented, and
357 * size decremented, as each batch of uniforms is uploaded.
362 uint32_t uniforms_size;
365 static inline struct vc4_exec_info *
366 vc4_first_bin_job(struct vc4_dev *vc4)
368 return list_first_entry_or_null(&vc4->bin_job_list,
369 struct vc4_exec_info, head);
372 static inline struct vc4_exec_info *
373 vc4_first_render_job(struct vc4_dev *vc4)
375 return list_first_entry_or_null(&vc4->render_job_list,
376 struct vc4_exec_info, head);
379 static inline struct vc4_exec_info *
380 vc4_last_render_job(struct vc4_dev *vc4)
382 if (list_empty(&vc4->render_job_list))
384 return list_last_entry(&vc4->render_job_list,
385 struct vc4_exec_info, head);
389 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
392 * This will be used at draw time to relocate the reference to the texture
393 * contents in p0, and validate that the offset combined with
394 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
395 * Note that the hardware treats unprovided config parameters as 0, so not all
396 * of them need to be set up for every texure sample, and we'll store ~0 as
397 * the offset to mark the unused ones.
399 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
400 * Setup") for definitions of the texture parameters.
402 struct vc4_texture_sample_info {
404 uint32_t p_offset[4];
408 * struct vc4_validated_shader_info - information about validated shaders that
409 * needs to be used from command list validation.
411 * For a given shader, each time a shader state record references it, we need
412 * to verify that the shader doesn't read more uniforms than the shader state
413 * record's uniform BO pointer can provide, and we need to apply relocations
414 * and validate the shader state record's uniforms that define the texture
417 struct vc4_validated_shader_info {
418 uint32_t uniforms_size;
419 uint32_t uniforms_src_size;
420 uint32_t num_texture_samples;
421 struct vc4_texture_sample_info *texture_samples;
423 uint32_t num_uniform_addr_offsets;
424 uint32_t *uniform_addr_offsets;
430 * _wait_for - magic (register) wait macro
432 * Does the right thing for modeset paths when run under kdgb or similar atomic
433 * contexts. Note that it's important that we check the condition again after
434 * having timed out, since the timeout could be due to preemption or similar and
435 * we've never had a chance to check the condition before the timeout.
437 #define _wait_for(COND, MS, W) ({ \
438 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
441 if (time_after(jiffies, timeout__)) { \
443 ret__ = -ETIMEDOUT; \
446 if (W && drm_can_sleep()) { \
455 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
458 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
459 void vc4_free_object(struct drm_gem_object *gem_obj);
460 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
462 int vc4_dumb_create(struct drm_file *file_priv,
463 struct drm_device *dev,
464 struct drm_mode_create_dumb *args);
465 struct dma_buf *vc4_prime_export(struct drm_device *dev,
466 struct drm_gem_object *obj, int flags);
467 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
468 struct drm_file *file_priv);
469 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv);
471 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv);
473 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
474 struct drm_file *file_priv);
475 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
476 struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj);
477 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
478 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
479 struct dma_buf_attachment *attach,
480 struct sg_table *sgt);
481 void *vc4_prime_vmap(struct drm_gem_object *obj);
482 void vc4_bo_cache_init(struct drm_device *dev);
483 void vc4_bo_cache_destroy(struct drm_device *dev);
484 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
487 extern struct platform_driver vc4_crtc_driver;
488 bool vc4_event_pending(struct drm_crtc *crtc);
489 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
490 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
491 bool in_vblank_irq, int *vpos, int *hpos,
492 ktime_t *stime, ktime_t *etime,
493 const struct drm_display_mode *mode);
496 int vc4_debugfs_init(struct drm_minor *minor);
499 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
502 extern struct platform_driver vc4_dpi_driver;
503 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
506 extern struct platform_driver vc4_dsi_driver;
507 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
510 extern const struct dma_fence_ops vc4_fence_ops;
513 void vc4_gem_init(struct drm_device *dev);
514 void vc4_gem_destroy(struct drm_device *dev);
515 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
516 struct drm_file *file_priv);
517 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
518 struct drm_file *file_priv);
519 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
520 struct drm_file *file_priv);
521 void vc4_submit_next_bin_job(struct drm_device *dev);
522 void vc4_submit_next_render_job(struct drm_device *dev);
523 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
524 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
525 uint64_t timeout_ns, bool interruptible);
526 void vc4_job_handle_completed(struct vc4_dev *vc4);
527 int vc4_queue_seqno_cb(struct drm_device *dev,
528 struct vc4_seqno_cb *cb, uint64_t seqno,
529 void (*func)(struct vc4_seqno_cb *cb));
532 extern struct platform_driver vc4_hdmi_driver;
533 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
536 extern struct platform_driver vc4_vec_driver;
537 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
540 irqreturn_t vc4_irq(int irq, void *arg);
541 void vc4_irq_preinstall(struct drm_device *dev);
542 int vc4_irq_postinstall(struct drm_device *dev);
543 void vc4_irq_uninstall(struct drm_device *dev);
544 void vc4_irq_reset(struct drm_device *dev);
547 extern struct platform_driver vc4_hvs_driver;
548 void vc4_hvs_dump_state(struct drm_device *dev);
549 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
552 int vc4_kms_load(struct drm_device *dev);
555 struct drm_plane *vc4_plane_init(struct drm_device *dev,
556 enum drm_plane_type type);
557 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
558 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
559 void vc4_plane_async_set_fb(struct drm_plane *plane,
560 struct drm_framebuffer *fb);
563 extern struct platform_driver vc4_v3d_driver;
564 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
565 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
566 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
570 vc4_validate_bin_cl(struct drm_device *dev,
573 struct vc4_exec_info *exec);
576 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
578 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
581 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
583 bool vc4_check_tex_size(struct vc4_exec_info *exec,
584 struct drm_gem_cma_object *fbo,
585 uint32_t offset, uint8_t tiling_format,
586 uint32_t width, uint32_t height, uint8_t cpp);
588 /* vc4_validate_shader.c */
589 struct vc4_validated_shader_info *
590 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);