2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/device.h>
30 #include "uapi/drm/vc4_drm.h"
33 #include "vc4_trace.h"
36 vc4_queue_hangcheck(struct drm_device *dev)
38 struct vc4_dev *vc4 = to_vc4_dev(dev);
40 mod_timer(&vc4->hangcheck.timer,
41 round_jiffies_up(jiffies + msecs_to_jiffies(100)));
44 struct vc4_hang_state {
45 struct drm_vc4_get_hang_state user_state;
48 struct drm_gem_object **bo;
52 vc4_free_hang_state(struct drm_device *dev, struct vc4_hang_state *state)
56 for (i = 0; i < state->user_state.bo_count; i++)
57 drm_gem_object_unreference_unlocked(state->bo[i]);
63 vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
64 struct drm_file *file_priv)
66 struct drm_vc4_get_hang_state *get_state = data;
67 struct drm_vc4_get_hang_state_bo *bo_state;
68 struct vc4_hang_state *kernel_state;
69 struct drm_vc4_get_hang_state *state;
70 struct vc4_dev *vc4 = to_vc4_dev(dev);
71 unsigned long irqflags;
75 spin_lock_irqsave(&vc4->job_lock, irqflags);
76 kernel_state = vc4->hang_state;
78 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
81 state = &kernel_state->user_state;
83 /* If the user's array isn't big enough, just return the
84 * required array size.
86 if (get_state->bo_count < state->bo_count) {
87 get_state->bo_count = state->bo_count;
88 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
92 vc4->hang_state = NULL;
93 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
95 /* Save the user's BO pointer, so we don't stomp it with the memcpy. */
96 state->bo = get_state->bo;
97 memcpy(get_state, state, sizeof(*state));
99 bo_state = kcalloc(state->bo_count, sizeof(*bo_state), GFP_KERNEL);
105 for (i = 0; i < state->bo_count; i++) {
106 struct vc4_bo *vc4_bo = to_vc4_bo(kernel_state->bo[i]);
109 ret = drm_gem_handle_create(file_priv, kernel_state->bo[i],
113 state->bo_count = i - 1;
116 bo_state[i].handle = handle;
117 bo_state[i].paddr = vc4_bo->base.paddr;
118 bo_state[i].size = vc4_bo->base.base.size;
121 if (copy_to_user((void __user *)(uintptr_t)get_state->bo,
123 state->bo_count * sizeof(*bo_state)))
130 vc4_free_hang_state(dev, kernel_state);
137 vc4_save_hang_state(struct drm_device *dev)
139 struct vc4_dev *vc4 = to_vc4_dev(dev);
140 struct drm_vc4_get_hang_state *state;
141 struct vc4_hang_state *kernel_state;
142 struct vc4_exec_info *exec[2];
144 unsigned long irqflags;
145 unsigned int i, j, unref_list_count, prev_idx;
147 kernel_state = kcalloc(1, sizeof(*kernel_state), GFP_KERNEL);
151 state = &kernel_state->user_state;
153 spin_lock_irqsave(&vc4->job_lock, irqflags);
154 exec[0] = vc4_first_bin_job(vc4);
155 exec[1] = vc4_first_render_job(vc4);
156 if (!exec[0] && !exec[1]) {
157 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
161 /* Get the bos from both binner and renderer into hang state. */
163 for (i = 0; i < 2; i++) {
167 unref_list_count = 0;
168 list_for_each_entry(bo, &exec[i]->unref_list, unref_head)
170 state->bo_count += exec[i]->bo_count + unref_list_count;
173 kernel_state->bo = kcalloc(state->bo_count,
174 sizeof(*kernel_state->bo), GFP_ATOMIC);
176 if (!kernel_state->bo) {
177 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
182 for (i = 0; i < 2; i++) {
186 for (j = 0; j < exec[i]->bo_count; j++) {
187 drm_gem_object_reference(&exec[i]->bo[j]->base);
188 kernel_state->bo[j + prev_idx] = &exec[i]->bo[j]->base;
191 list_for_each_entry(bo, &exec[i]->unref_list, unref_head) {
192 drm_gem_object_reference(&bo->base.base);
193 kernel_state->bo[j + prev_idx] = &bo->base.base;
200 state->start_bin = exec[0]->ct0ca;
202 state->start_render = exec[1]->ct1ca;
204 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
206 state->ct0ca = V3D_READ(V3D_CTNCA(0));
207 state->ct0ea = V3D_READ(V3D_CTNEA(0));
209 state->ct1ca = V3D_READ(V3D_CTNCA(1));
210 state->ct1ea = V3D_READ(V3D_CTNEA(1));
212 state->ct0cs = V3D_READ(V3D_CTNCS(0));
213 state->ct1cs = V3D_READ(V3D_CTNCS(1));
215 state->ct0ra0 = V3D_READ(V3D_CT00RA0);
216 state->ct1ra0 = V3D_READ(V3D_CT01RA0);
218 state->bpca = V3D_READ(V3D_BPCA);
219 state->bpcs = V3D_READ(V3D_BPCS);
220 state->bpoa = V3D_READ(V3D_BPOA);
221 state->bpos = V3D_READ(V3D_BPOS);
223 state->vpmbase = V3D_READ(V3D_VPMBASE);
225 state->dbge = V3D_READ(V3D_DBGE);
226 state->fdbgo = V3D_READ(V3D_FDBGO);
227 state->fdbgb = V3D_READ(V3D_FDBGB);
228 state->fdbgr = V3D_READ(V3D_FDBGR);
229 state->fdbgs = V3D_READ(V3D_FDBGS);
230 state->errstat = V3D_READ(V3D_ERRSTAT);
232 spin_lock_irqsave(&vc4->job_lock, irqflags);
233 if (vc4->hang_state) {
234 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
235 vc4_free_hang_state(dev, kernel_state);
237 vc4->hang_state = kernel_state;
238 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
243 vc4_reset(struct drm_device *dev)
245 struct vc4_dev *vc4 = to_vc4_dev(dev);
247 DRM_INFO("Resetting GPU.\n");
249 mutex_lock(&vc4->power_lock);
250 if (vc4->power_refcount) {
251 /* Power the device off and back on the by dropping the
252 * reference on runtime PM.
254 pm_runtime_put_sync_suspend(&vc4->v3d->pdev->dev);
255 pm_runtime_get_sync(&vc4->v3d->pdev->dev);
257 mutex_unlock(&vc4->power_lock);
261 /* Rearm the hangcheck -- another job might have been waiting
262 * for our hung one to get kicked off, and vc4_irq_reset()
263 * would have started it.
265 vc4_queue_hangcheck(dev);
269 vc4_reset_work(struct work_struct *work)
271 struct vc4_dev *vc4 =
272 container_of(work, struct vc4_dev, hangcheck.reset_work);
274 vc4_save_hang_state(vc4->dev);
280 vc4_hangcheck_elapsed(unsigned long data)
282 struct drm_device *dev = (struct drm_device *)data;
283 struct vc4_dev *vc4 = to_vc4_dev(dev);
284 uint32_t ct0ca, ct1ca;
285 unsigned long irqflags;
286 struct vc4_exec_info *bin_exec, *render_exec;
288 spin_lock_irqsave(&vc4->job_lock, irqflags);
290 bin_exec = vc4_first_bin_job(vc4);
291 render_exec = vc4_first_render_job(vc4);
293 /* If idle, we can stop watching for hangs. */
294 if (!bin_exec && !render_exec) {
295 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
299 ct0ca = V3D_READ(V3D_CTNCA(0));
300 ct1ca = V3D_READ(V3D_CTNCA(1));
302 /* If we've made any progress in execution, rearm the timer
305 if ((bin_exec && ct0ca != bin_exec->last_ct0ca) ||
306 (render_exec && ct1ca != render_exec->last_ct1ca)) {
308 bin_exec->last_ct0ca = ct0ca;
310 render_exec->last_ct1ca = ct1ca;
311 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
312 vc4_queue_hangcheck(dev);
316 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
318 /* We've gone too long with no progress, reset. This has to
319 * be done from a work struct, since resetting can sleep and
320 * this timer hook isn't allowed to.
322 schedule_work(&vc4->hangcheck.reset_work);
326 submit_cl(struct drm_device *dev, uint32_t thread, uint32_t start, uint32_t end)
328 struct vc4_dev *vc4 = to_vc4_dev(dev);
330 /* Set the current and end address of the control list.
331 * Writing the end register is what starts the job.
333 V3D_WRITE(V3D_CTNCA(thread), start);
334 V3D_WRITE(V3D_CTNEA(thread), end);
338 vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, uint64_t timeout_ns,
341 struct vc4_dev *vc4 = to_vc4_dev(dev);
343 unsigned long timeout_expire;
346 if (vc4->finished_seqno >= seqno)
352 timeout_expire = jiffies + nsecs_to_jiffies(timeout_ns);
354 trace_vc4_wait_for_seqno_begin(dev, seqno, timeout_ns);
356 prepare_to_wait(&vc4->job_wait_queue, &wait,
357 interruptible ? TASK_INTERRUPTIBLE :
358 TASK_UNINTERRUPTIBLE);
360 if (interruptible && signal_pending(current)) {
365 if (vc4->finished_seqno >= seqno)
368 if (timeout_ns != ~0ull) {
369 if (time_after_eq(jiffies, timeout_expire)) {
373 schedule_timeout(timeout_expire - jiffies);
379 finish_wait(&vc4->job_wait_queue, &wait);
380 trace_vc4_wait_for_seqno_end(dev, seqno);
386 vc4_flush_caches(struct drm_device *dev)
388 struct vc4_dev *vc4 = to_vc4_dev(dev);
390 /* Flush the GPU L2 caches. These caches sit on top of system
391 * L3 (the 128kb or so shared with the CPU), and are
392 * non-allocating in the L3.
394 V3D_WRITE(V3D_L2CACTL,
397 V3D_WRITE(V3D_SLCACTL,
398 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
399 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) |
400 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) |
401 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
404 /* Sets the registers for the next job to be actually be executed in
407 * The job_lock should be held during this.
410 vc4_submit_next_bin_job(struct drm_device *dev)
412 struct vc4_dev *vc4 = to_vc4_dev(dev);
413 struct vc4_exec_info *exec;
416 exec = vc4_first_bin_job(vc4);
420 vc4_flush_caches(dev);
422 /* Either put the job in the binner if it uses the binner, or
423 * immediately move it to the to-be-rendered queue.
425 if (exec->ct0ca != exec->ct0ea) {
426 submit_cl(dev, 0, exec->ct0ca, exec->ct0ea);
428 vc4_move_job_to_render(dev, exec);
434 vc4_submit_next_render_job(struct drm_device *dev)
436 struct vc4_dev *vc4 = to_vc4_dev(dev);
437 struct vc4_exec_info *exec = vc4_first_render_job(vc4);
442 submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
446 vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec)
448 struct vc4_dev *vc4 = to_vc4_dev(dev);
449 bool was_empty = list_empty(&vc4->render_job_list);
451 list_move_tail(&exec->head, &vc4->render_job_list);
453 vc4_submit_next_render_job(dev);
457 vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t seqno)
462 for (i = 0; i < exec->bo_count; i++) {
463 bo = to_vc4_bo(&exec->bo[i]->base);
467 list_for_each_entry(bo, &exec->unref_list, unref_head) {
472 /* Queues a struct vc4_exec_info for execution. If no job is
473 * currently executing, then submits it.
475 * Unlike most GPUs, our hardware only handles one command list at a
476 * time. To queue multiple jobs at once, we'd need to edit the
477 * previous command list to have a jump to the new one at the end, and
478 * then bump the end address. That's a change for a later date,
482 vc4_queue_submit(struct drm_device *dev, struct vc4_exec_info *exec)
484 struct vc4_dev *vc4 = to_vc4_dev(dev);
486 unsigned long irqflags;
488 spin_lock_irqsave(&vc4->job_lock, irqflags);
490 seqno = ++vc4->emit_seqno;
492 vc4_update_bo_seqnos(exec, seqno);
494 list_add_tail(&exec->head, &vc4->bin_job_list);
496 /* If no job was executing, kick ours off. Otherwise, it'll
497 * get started when the previous job's flush done interrupt
500 if (vc4_first_bin_job(vc4) == exec) {
501 vc4_submit_next_bin_job(dev);
502 vc4_queue_hangcheck(dev);
505 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
509 * Looks up a bunch of GEM handles for BOs and stores the array for
510 * use in the command validator that actually writes relocated
511 * addresses pointing to them.
514 vc4_cl_lookup_bos(struct drm_device *dev,
515 struct drm_file *file_priv,
516 struct vc4_exec_info *exec)
518 struct drm_vc4_submit_cl *args = exec->args;
523 exec->bo_count = args->bo_handle_count;
525 if (!exec->bo_count) {
526 /* See comment on bo_index for why we have to check
529 DRM_ERROR("Rendering requires BOs to validate\n");
533 exec->bo = kcalloc(exec->bo_count, sizeof(struct drm_gem_cma_object *),
536 DRM_ERROR("Failed to allocate validated BO pointers\n");
540 handles = drm_malloc_ab(exec->bo_count, sizeof(uint32_t));
542 DRM_ERROR("Failed to allocate incoming GEM handles\n");
546 ret = copy_from_user(handles,
547 (void __user *)(uintptr_t)args->bo_handles,
548 exec->bo_count * sizeof(uint32_t));
550 DRM_ERROR("Failed to copy in GEM handles\n");
554 spin_lock(&file_priv->table_lock);
555 for (i = 0; i < exec->bo_count; i++) {
556 struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
559 DRM_ERROR("Failed to look up GEM BO %d: %d\n",
562 spin_unlock(&file_priv->table_lock);
565 drm_gem_object_reference(bo);
566 exec->bo[i] = (struct drm_gem_cma_object *)bo;
568 spin_unlock(&file_priv->table_lock);
576 vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
578 struct drm_vc4_submit_cl *args = exec->args;
582 uint32_t bin_offset = 0;
583 uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size,
585 uint32_t uniforms_offset = shader_rec_offset + args->shader_rec_size;
586 uint32_t exec_size = uniforms_offset + args->uniforms_size;
587 uint32_t temp_size = exec_size + (sizeof(struct vc4_shader_state) *
588 args->shader_rec_count);
591 if (uniforms_offset < shader_rec_offset ||
592 exec_size < uniforms_offset ||
593 args->shader_rec_count >= (UINT_MAX /
594 sizeof(struct vc4_shader_state)) ||
595 temp_size < exec_size) {
596 DRM_ERROR("overflow in exec arguments\n");
600 /* Allocate space where we'll store the copied in user command lists
601 * and shader records.
603 * We don't just copy directly into the BOs because we need to
604 * read the contents back for validation, and I think the
605 * bo->vaddr is uncached access.
607 temp = kmalloc(temp_size, GFP_KERNEL);
609 DRM_ERROR("Failed to allocate storage for copying "
610 "in bin/render CLs.\n");
614 bin = temp + bin_offset;
615 exec->shader_rec_u = temp + shader_rec_offset;
616 exec->uniforms_u = temp + uniforms_offset;
617 exec->shader_state = temp + exec_size;
618 exec->shader_state_size = args->shader_rec_count;
620 if (copy_from_user(bin,
621 (void __user *)(uintptr_t)args->bin_cl,
622 args->bin_cl_size)) {
627 if (copy_from_user(exec->shader_rec_u,
628 (void __user *)(uintptr_t)args->shader_rec,
629 args->shader_rec_size)) {
634 if (copy_from_user(exec->uniforms_u,
635 (void __user *)(uintptr_t)args->uniforms,
636 args->uniforms_size)) {
641 bo = vc4_bo_create(dev, exec_size, true);
643 DRM_ERROR("Couldn't allocate BO for binning\n");
647 exec->exec_bo = &bo->base;
649 list_add_tail(&to_vc4_bo(&exec->exec_bo->base)->unref_head,
652 exec->ct0ca = exec->exec_bo->paddr + bin_offset;
656 exec->shader_rec_v = exec->exec_bo->vaddr + shader_rec_offset;
657 exec->shader_rec_p = exec->exec_bo->paddr + shader_rec_offset;
658 exec->shader_rec_size = args->shader_rec_size;
660 exec->uniforms_v = exec->exec_bo->vaddr + uniforms_offset;
661 exec->uniforms_p = exec->exec_bo->paddr + uniforms_offset;
662 exec->uniforms_size = args->uniforms_size;
664 ret = vc4_validate_bin_cl(dev,
665 exec->exec_bo->vaddr + bin_offset,
671 ret = vc4_validate_shader_recs(dev, exec);
679 vc4_complete_exec(struct drm_device *dev, struct vc4_exec_info *exec)
681 struct vc4_dev *vc4 = to_vc4_dev(dev);
685 for (i = 0; i < exec->bo_count; i++)
686 drm_gem_object_unreference_unlocked(&exec->bo[i]->base);
690 while (!list_empty(&exec->unref_list)) {
691 struct vc4_bo *bo = list_first_entry(&exec->unref_list,
692 struct vc4_bo, unref_head);
693 list_del(&bo->unref_head);
694 drm_gem_object_unreference_unlocked(&bo->base.base);
697 mutex_lock(&vc4->power_lock);
698 if (--vc4->power_refcount == 0)
699 pm_runtime_put(&vc4->v3d->pdev->dev);
700 mutex_unlock(&vc4->power_lock);
706 vc4_job_handle_completed(struct vc4_dev *vc4)
708 unsigned long irqflags;
709 struct vc4_seqno_cb *cb, *cb_temp;
711 spin_lock_irqsave(&vc4->job_lock, irqflags);
712 while (!list_empty(&vc4->job_done_list)) {
713 struct vc4_exec_info *exec =
714 list_first_entry(&vc4->job_done_list,
715 struct vc4_exec_info, head);
716 list_del(&exec->head);
718 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
719 vc4_complete_exec(vc4->dev, exec);
720 spin_lock_irqsave(&vc4->job_lock, irqflags);
723 list_for_each_entry_safe(cb, cb_temp, &vc4->seqno_cb_list, work.entry) {
724 if (cb->seqno <= vc4->finished_seqno) {
725 list_del_init(&cb->work.entry);
726 schedule_work(&cb->work);
730 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
733 static void vc4_seqno_cb_work(struct work_struct *work)
735 struct vc4_seqno_cb *cb = container_of(work, struct vc4_seqno_cb, work);
740 int vc4_queue_seqno_cb(struct drm_device *dev,
741 struct vc4_seqno_cb *cb, uint64_t seqno,
742 void (*func)(struct vc4_seqno_cb *cb))
744 struct vc4_dev *vc4 = to_vc4_dev(dev);
746 unsigned long irqflags;
749 INIT_WORK(&cb->work, vc4_seqno_cb_work);
751 spin_lock_irqsave(&vc4->job_lock, irqflags);
752 if (seqno > vc4->finished_seqno) {
754 list_add_tail(&cb->work.entry, &vc4->seqno_cb_list);
756 schedule_work(&cb->work);
758 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
763 /* Scheduled when any job has been completed, this walks the list of
764 * jobs that had completed and unrefs their BOs and frees their exec
768 vc4_job_done_work(struct work_struct *work)
770 struct vc4_dev *vc4 =
771 container_of(work, struct vc4_dev, job_done_work);
773 vc4_job_handle_completed(vc4);
777 vc4_wait_for_seqno_ioctl_helper(struct drm_device *dev,
779 uint64_t *timeout_ns)
781 unsigned long start = jiffies;
782 int ret = vc4_wait_for_seqno(dev, seqno, *timeout_ns, true);
784 if ((ret == -EINTR || ret == -ERESTARTSYS) && *timeout_ns != ~0ull) {
785 uint64_t delta = jiffies_to_nsecs(jiffies - start);
787 if (*timeout_ns >= delta)
788 *timeout_ns -= delta;
795 vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
796 struct drm_file *file_priv)
798 struct drm_vc4_wait_seqno *args = data;
800 return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
805 vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
806 struct drm_file *file_priv)
809 struct drm_vc4_wait_bo *args = data;
810 struct drm_gem_object *gem_obj;
816 gem_obj = drm_gem_object_lookup(file_priv, args->handle);
818 DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
821 bo = to_vc4_bo(gem_obj);
823 ret = vc4_wait_for_seqno_ioctl_helper(dev, bo->seqno,
826 drm_gem_object_unreference_unlocked(gem_obj);
831 * Submits a command list to the VC4.
833 * This is what is called batchbuffer emitting on other hardware.
836 vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
837 struct drm_file *file_priv)
839 struct vc4_dev *vc4 = to_vc4_dev(dev);
840 struct drm_vc4_submit_cl *args = data;
841 struct vc4_exec_info *exec;
844 if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
845 DRM_ERROR("Unknown flags: 0x%02x\n", args->flags);
849 exec = kcalloc(1, sizeof(*exec), GFP_KERNEL);
851 DRM_ERROR("malloc failure on exec struct\n");
855 mutex_lock(&vc4->power_lock);
856 if (vc4->power_refcount++ == 0)
857 ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
858 mutex_unlock(&vc4->power_lock);
865 INIT_LIST_HEAD(&exec->unref_list);
867 ret = vc4_cl_lookup_bos(dev, file_priv, exec);
871 if (exec->args->bin_cl_size != 0) {
872 ret = vc4_get_bcl(dev, exec);
880 ret = vc4_get_rcl(dev, exec);
884 /* Clear this out of the struct we'll be putting in the queue,
885 * since it's part of our stack.
889 vc4_queue_submit(dev, exec);
891 /* Return the seqno for our job. */
892 args->seqno = vc4->emit_seqno;
897 vc4_complete_exec(vc4->dev, exec);
903 vc4_gem_init(struct drm_device *dev)
905 struct vc4_dev *vc4 = to_vc4_dev(dev);
907 INIT_LIST_HEAD(&vc4->bin_job_list);
908 INIT_LIST_HEAD(&vc4->render_job_list);
909 INIT_LIST_HEAD(&vc4->job_done_list);
910 INIT_LIST_HEAD(&vc4->seqno_cb_list);
911 spin_lock_init(&vc4->job_lock);
913 INIT_WORK(&vc4->hangcheck.reset_work, vc4_reset_work);
914 setup_timer(&vc4->hangcheck.timer,
915 vc4_hangcheck_elapsed,
918 INIT_WORK(&vc4->job_done_work, vc4_job_done_work);
920 mutex_init(&vc4->power_lock);
924 vc4_gem_destroy(struct drm_device *dev)
926 struct vc4_dev *vc4 = to_vc4_dev(dev);
928 /* Waiting for exec to finish would need to be done before
931 WARN_ON(vc4->emit_seqno != vc4->finished_seqno);
933 /* V3D should already have disabled its interrupt and cleared
934 * the overflow allocation registers. Now free the object.
936 if (vc4->overflow_mem) {
937 drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
938 vc4->overflow_mem = NULL;
941 vc4_bo_cache_destroy(dev);
944 vc4_free_hang_state(dev, vc4->hang_state);