drivers/gpu/drm/vc4/vc4_hdmi.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /**
  21  * DOC: VC4 Falcon HDMI module
  22  *
  23  * The HDMI core has a state machine and a PHY.  Most of the unit
  24  * operates off of the HSM clock from CPRMAN.  It also internally uses
  25  * the PLLH_PIX clock for the PHY.
  26  */
  27
  28 #include "drm_atomic_helper.h"
  29 #include "drm_crtc_helper.h"
  30 #include "drm_edid.h"
  31 #include "linux/clk.h"
  32 #include "linux/component.h"
  33 #include "linux/i2c.h"
  34 #include "linux/of_gpio.h"
  35 #include "linux/of_platform.h"
  36 #include "vc4_drv.h"
  37 #include "vc4_regs.h"
  38
  39 /* General HDMI hardware state. */
  40 struct vc4_hdmi {
  41         struct platform_device *pdev;
  42
  43         struct drm_encoder *encoder;
  44         struct drm_connector *connector;
  45
  46         struct i2c_adapter *ddc;
  47         void __iomem *hdmicore_regs;
  48         void __iomem *hd_regs;
  49         int hpd_gpio;
  50         bool hpd_active_low;
  51
  52         struct clk *pixel_clock;
  53         struct clk *hsm_clock;
  54 };
  55
  56 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
  57 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
  58 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
  59 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
  60
  61 /* VC4 HDMI encoder KMS struct */
  62 struct vc4_hdmi_encoder {
  63         struct vc4_encoder base;
  64         bool hdmi_monitor;
  65 };
  66
  67 static inline struct vc4_hdmi_encoder *
  68 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
  69 {
  70         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
  71 }
  72
  73 /* VC4 HDMI connector KMS struct */
  74 struct vc4_hdmi_connector {
  75         struct drm_connector base;
  76
  77         /* Since the connector is attached to just the one encoder,
  78          * this is the reference to it so we can do the best_encoder()
  79          * hook.
  80          */
  81         struct drm_encoder *encoder;
  82 };
  83
  84 static inline struct vc4_hdmi_connector *
  85 to_vc4_hdmi_connector(struct drm_connector *connector)
  86 {
  87         return container_of(connector, struct vc4_hdmi_connector, base);
  88 }
  89
  90 #define HDMI_REG(reg) { reg, #reg }
  91 static const struct {
  92         u32 reg;
  93         const char *name;
  94 } hdmi_regs[] = {
  95         HDMI_REG(VC4_HDMI_CORE_REV),
  96         HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
  97         HDMI_REG(VC4_HDMI_HOTPLUG_INT),
  98         HDMI_REG(VC4_HDMI_HOTPLUG),
  99         HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
 100         HDMI_REG(VC4_HDMI_HORZA),
 101         HDMI_REG(VC4_HDMI_HORZB),
 102         HDMI_REG(VC4_HDMI_FIFO_CTL),
 103         HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
 104         HDMI_REG(VC4_HDMI_VERTA0),
 105         HDMI_REG(VC4_HDMI_VERTA1),
 106         HDMI_REG(VC4_HDMI_VERTB0),
 107         HDMI_REG(VC4_HDMI_VERTB1),
 108         HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
 109 };
 110
 111 static const struct {
 112         u32 reg;
 113         const char *name;
 114 } hd_regs[] = {
 115         HDMI_REG(VC4_HD_M_CTL),
 116         HDMI_REG(VC4_HD_MAI_CTL),
 117         HDMI_REG(VC4_HD_VID_CTL),
 118         HDMI_REG(VC4_HD_CSC_CTL),
 119         HDMI_REG(VC4_HD_FRAME_COUNT),
 120 };
 121
 122 #ifdef CONFIG_DEBUG_FS
 123 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 124 {
 125         struct drm_info_node *node = (struct drm_info_node *)m->private;
 126         struct drm_device *dev = node->minor->dev;
 127         struct vc4_dev *vc4 = to_vc4_dev(dev);
 128         int i;
 129
 130         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 131                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 132                            hdmi_regs[i].name, hdmi_regs[i].reg,
 133                            HDMI_READ(hdmi_regs[i].reg));
 134         }
 135
 136         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 137                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 138                            hd_regs[i].name, hd_regs[i].reg,
 139                            HD_READ(hd_regs[i].reg));
 140         }
 141
 142         return 0;
 143 }
 144 #endif /* CONFIG_DEBUG_FS */
 145
 146 static void vc4_hdmi_dump_regs(struct drm_device *dev)
 147 {
 148         struct vc4_dev *vc4 = to_vc4_dev(dev);
 149         int i;
 150
 151         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 152                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 153                          hdmi_regs[i].reg, hdmi_regs[i].name,
 154                          HDMI_READ(hdmi_regs[i].reg));
 155         }
 156         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 157                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 158                          hd_regs[i].reg, hd_regs[i].name,
 159                          HD_READ(hd_regs[i].reg));
 160         }
 161 }
 162
 163 static enum drm_connector_status
 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 165 {
 166         struct drm_device *dev = connector->dev;
 167         struct vc4_dev *vc4 = to_vc4_dev(dev);
 168
 169         if (vc4->hdmi->hpd_gpio) {
 170                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 171                     vc4->hdmi->hpd_active_low)
 172                         return connector_status_connected;
 173                 else
 174                         return connector_status_disconnected;
 175         }
 176
 177         if (drm_probe_ddc(vc4->hdmi->ddc))
 178                 return connector_status_connected;
 179
 180         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 181                 return connector_status_connected;
 182         else
 183                 return connector_status_disconnected;
 184 }
 185
 186 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 187 {
 188         drm_connector_unregister(connector);
 189         drm_connector_cleanup(connector);
 190 }
 191
 192 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 193 {
 194         struct vc4_hdmi_connector *vc4_connector =
 195                 to_vc4_hdmi_connector(connector);
 196         struct drm_encoder *encoder = vc4_connector->encoder;
 197         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 198         struct drm_device *dev = connector->dev;
 199         struct vc4_dev *vc4 = to_vc4_dev(dev);
 200         int ret = 0;
 201         struct edid *edid;
 202
 203         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 204         if (!edid)
 205                 return -ENODEV;
 206
 207         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 208         drm_mode_connector_update_edid_property(connector, edid);
 209         ret = drm_add_edid_modes(connector, edid);
 210
 211         return ret;
 212 }
 213
 214 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 215         .dpms = drm_atomic_helper_connector_dpms,
 216         .detect = vc4_hdmi_connector_detect,
 217         .fill_modes = drm_helper_probe_single_connector_modes,
 218         .destroy = vc4_hdmi_connector_destroy,
 219         .reset = drm_atomic_helper_connector_reset,
 220         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 221         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 222 };
 223
 224 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 225         .get_modes = vc4_hdmi_connector_get_modes,
 226 };
 227
 228 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 229                                                      struct drm_encoder *encoder)
 230 {
 231         struct drm_connector *connector = NULL;
 232         struct vc4_hdmi_connector *hdmi_connector;
 233         int ret = 0;
 234
 235         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 236                                       GFP_KERNEL);
 237         if (!hdmi_connector) {
 238                 ret = -ENOMEM;
 239                 goto fail;
 240         }
 241         connector = &hdmi_connector->base;
 242
 243         hdmi_connector->encoder = encoder;
 244
 245         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 246                            DRM_MODE_CONNECTOR_HDMIA);
 247         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 248
 249         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 250                              DRM_CONNECTOR_POLL_DISCONNECT);
 251
 252         connector->interlace_allowed = 1;
 253         connector->doublescan_allowed = 0;
 254
 255         drm_mode_connector_attach_encoder(connector, encoder);
 256
 257         return connector;
 258
 259  fail:
 260         if (connector)
 261                 vc4_hdmi_connector_destroy(connector);
 262
 263         return ERR_PTR(ret);
 264 }
 265
 266 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 267 {
 268         drm_encoder_cleanup(encoder);
 269 }
 270
 271 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 272         .destroy = vc4_hdmi_encoder_destroy,
 273 };
 274
 275 static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
 276                                       struct drm_display_mode *unadjusted_mode,
 277                                       struct drm_display_mode *mode)
 278 {
 279         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 280         struct drm_device *dev = encoder->dev;
 281         struct vc4_dev *vc4 = to_vc4_dev(dev);
 282         bool debug_dump_regs = false;
 283         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 284         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 285         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 286         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 287                                    VC4_HDMI_VERTA_VSP) |
 288                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 289                                    VC4_HDMI_VERTA_VFP) |
 290                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 291         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 292                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 293                                    VC4_HDMI_VERTB_VBP));
 294         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 295                           VC4_SET_FIELD(mode->crtc_vtotal -
 296                                         mode->crtc_vsync_end -
 297                                         interlaced,
 298                                         VC4_HDMI_VERTB_VBP));
 299         u32 csc_ctl;
 300
 301         if (debug_dump_regs) {
 302                 DRM_INFO("HDMI regs before:\n");
 303                 vc4_hdmi_dump_regs(dev);
 304         }
 305
 306         HD_WRITE(VC4_HD_VID_CTL, 0);
 307
 308         clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);
 309
 310         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 311                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 312                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 313                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 314
 315         HDMI_WRITE(VC4_HDMI_HORZA,
 316                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 317                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 318                    VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));
 319
 320         HDMI_WRITE(VC4_HDMI_HORZB,
 321                    VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 322                                  VC4_HDMI_HORZB_HBP) |
 323                    VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 324                                  VC4_HDMI_HORZB_HSP) |
 325                    VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 326                                  VC4_HDMI_HORZB_HFP));
 327
 328         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 329         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 330
 331         HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
 332         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 333
 334         HD_WRITE(VC4_HD_VID_CTL,
 335                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 336                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 337
 338         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 339                                 VC4_HD_CSC_CTL_ORDER);
 340
 341         if (vc4_encoder->hdmi_monitor && drm_match_cea_mode(mode) > 1) {
 342                 /* CEA VICs other than #1 requre limited range RGB
 343                  * output.  Apply a colorspace conversion to squash
 344                  * 0-255 down to 16-235.  The matrix here is:
 345                  *
 346                  * [ 0      0      0.8594 16]
 347                  * [ 0      0.8594 0      16]
 348                  * [ 0.8594 0      0      16]
 349                  * [ 0      0      0       1]
 350                  */
 351                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 352                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 353                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 354                                          VC4_HD_CSC_CTL_MODE);
 355
 356                 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
 357                 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
 358                 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
 359                 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
 360                 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
 361                 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
 362         }
 363
 364         /* The RGB order applies even when CSC is disabled. */
 365         HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
 366
 367         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 368
 369         if (debug_dump_regs) {
 370                 DRM_INFO("HDMI regs after:\n");
 371                 vc4_hdmi_dump_regs(dev);
 372         }
 373 }
 374
 375 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 376 {
 377         struct drm_device *dev = encoder->dev;
 378         struct vc4_dev *vc4 = to_vc4_dev(dev);
 379
 380         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 381         HD_WRITE(VC4_HD_VID_CTL,
 382                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 383 }
 384
 385 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 386 {
 387         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 388         struct drm_device *dev = encoder->dev;
 389         struct vc4_dev *vc4 = to_vc4_dev(dev);
 390         int ret;
 391
 392         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 393
 394         HD_WRITE(VC4_HD_VID_CTL,
 395                  HD_READ(VC4_HD_VID_CTL) |
 396                  VC4_HD_VID_CTL_ENABLE |
 397                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 398                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 399
 400         if (vc4_encoder->hdmi_monitor) {
 401                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 402                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 403                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 404
 405                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 406                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 407                 WARN_ONCE(ret, "Timeout waiting for "
 408                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 409         } else {
 410                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 411                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 412                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 413                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 414                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 415                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 416
 417                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 418                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 419                 WARN_ONCE(ret, "Timeout waiting for "
 420                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 421         }
 422
 423         if (vc4_encoder->hdmi_monitor) {
 424                 u32 drift;
 425
 426                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 427                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 428                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 429                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 430                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 431
 432                 /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
 433                  * up the infoframe.
 434                  */
 435
 436                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 437                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 438
 439                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 440                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 441                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 442                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 443                 udelay(1000);
 444                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 445                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 446                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 447                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 448
 449                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 450                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 451                 WARN_ONCE(ret, "Timeout waiting for "
 452                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 453         }
 454 }
 455
 456 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 457         .mode_set = vc4_hdmi_encoder_mode_set,
 458         .disable = vc4_hdmi_encoder_disable,
 459         .enable = vc4_hdmi_encoder_enable,
 460 };
 461
 462 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
 463 {
 464         struct platform_device *pdev = to_platform_device(dev);
 465         struct drm_device *drm = dev_get_drvdata(master);
 466         struct vc4_dev *vc4 = drm->dev_private;
 467         struct vc4_hdmi *hdmi;
 468         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
 469         struct device_node *ddc_node;
 470         u32 value;
 471         int ret;
 472
 473         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 474         if (!hdmi)
 475                 return -ENOMEM;
 476
 477         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
 478                                         GFP_KERNEL);
 479         if (!vc4_hdmi_encoder)
 480                 return -ENOMEM;
 481         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
 482         hdmi->encoder = &vc4_hdmi_encoder->base.base;
 483
 484         hdmi->pdev = pdev;
 485         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
 486         if (IS_ERR(hdmi->hdmicore_regs))
 487                 return PTR_ERR(hdmi->hdmicore_regs);
 488
 489         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
 490         if (IS_ERR(hdmi->hd_regs))
 491                 return PTR_ERR(hdmi->hd_regs);
 492
 493         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
 494         if (IS_ERR(hdmi->pixel_clock)) {
 495                 DRM_ERROR("Failed to get pixel clock\n");
 496                 return PTR_ERR(hdmi->pixel_clock);
 497         }
 498         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
 499         if (IS_ERR(hdmi->hsm_clock)) {
 500                 DRM_ERROR("Failed to get HDMI state machine clock\n");
 501                 return PTR_ERR(hdmi->hsm_clock);
 502         }
 503
 504         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
 505         if (!ddc_node) {
 506                 DRM_ERROR("Failed to find ddc node in device tree\n");
 507                 return -ENODEV;
 508         }
 509
 510         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
 511         of_node_put(ddc_node);
 512         if (!hdmi->ddc) {
 513                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
 514                 return -EPROBE_DEFER;
 515         }
 516
 517         /* Enable the clocks at startup.  We can't quite recover from
 518          * turning off the pixel clock during disable/enables yet, so
 519          * it's always running.
 520          */
 521         ret = clk_prepare_enable(hdmi->pixel_clock);
 522         if (ret) {
 523                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 524                 goto err_put_i2c;
 525         }
 526
 527         /* This is the rate that is set by the firmware.  The number
 528          * needs to be a bit higher than the pixel clock rate
 529          * (generally 148.5Mhz).
 530          */
 531         ret = clk_set_rate(hdmi->hsm_clock, 163682864);
 532         if (ret) {
 533                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 534                 goto err_unprepare_pix;
 535         }
 536
 537         ret = clk_prepare_enable(hdmi->hsm_clock);
 538         if (ret) {
 539                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
 540                           ret);
 541                 goto err_unprepare_pix;
 542         }
 543
 544         /* Only use the GPIO HPD pin if present in the DT, otherwise
 545          * we'll use the HDMI core's register.
 546          */
 547         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
 548                 enum of_gpio_flags hpd_gpio_flags;
 549
 550                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
 551                                                          "hpd-gpios", 0,
 552                                                          &hpd_gpio_flags);
 553                 if (hdmi->hpd_gpio < 0) {
 554                         ret = hdmi->hpd_gpio;
 555                         goto err_unprepare_hsm;
 556                 }
 557
 558                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
 559         }
 560
 561         vc4->hdmi = hdmi;
 562
 563         /* HDMI core must be enabled. */
 564         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
 565                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
 566                 udelay(1);
 567                 HD_WRITE(VC4_HD_M_CTL, 0);
 568
 569                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
 570
 571                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 572                            VC4_HDMI_SW_RESET_HDMI |
 573                            VC4_HDMI_SW_RESET_FORMAT_DETECT);
 574
 575                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 576
 577                 /* PHY should be in reset, like
 578                  * vc4_hdmi_encoder_disable() does.
 579                  */
 580                 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 581         }
 582
 583         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
 584                          DRM_MODE_ENCODER_TMDS, NULL);
 585         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
 586
 587         hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
 588         if (IS_ERR(hdmi->connector)) {
 589                 ret = PTR_ERR(hdmi->connector);
 590                 goto err_destroy_encoder;
 591         }
 592
 593         return 0;
 594
 595 err_destroy_encoder:
 596         vc4_hdmi_encoder_destroy(hdmi->encoder);
 597 err_unprepare_hsm:
 598         clk_disable_unprepare(hdmi->hsm_clock);
 599 err_unprepare_pix:
 600         clk_disable_unprepare(hdmi->pixel_clock);
 601 err_put_i2c:
 602         put_device(&hdmi->ddc->dev);
 603
 604         return ret;
 605 }
 606
 607 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
 608                             void *data)
 609 {
 610         struct drm_device *drm = dev_get_drvdata(master);
 611         struct vc4_dev *vc4 = drm->dev_private;
 612         struct vc4_hdmi *hdmi = vc4->hdmi;
 613
 614         vc4_hdmi_connector_destroy(hdmi->connector);
 615         vc4_hdmi_encoder_destroy(hdmi->encoder);
 616
 617         clk_disable_unprepare(hdmi->pixel_clock);
 618         clk_disable_unprepare(hdmi->hsm_clock);
 619         put_device(&hdmi->ddc->dev);
 620
 621         vc4->hdmi = NULL;
 622 }
 623
 624 static const struct component_ops vc4_hdmi_ops = {
 625         .bind   = vc4_hdmi_bind,
 626         .unbind = vc4_hdmi_unbind,
 627 };
 628
 629 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
 630 {
 631         return component_add(&pdev->dev, &vc4_hdmi_ops);
 632 }
 633
 634 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
 635 {
 636         component_del(&pdev->dev, &vc4_hdmi_ops);
 637         return 0;
 638 }
 639
 640 static const struct of_device_id vc4_hdmi_dt_match[] = {
 641         { .compatible = "brcm,bcm2835-hdmi" },
 642         {}
 643 };
 644
 645 struct platform_driver vc4_hdmi_driver = {
 646         .probe = vc4_hdmi_dev_probe,
 647         .remove = vc4_hdmi_dev_remove,
 648         .driver = {
 649                 .name = "vc4_hdmi",
 650                 .of_match_table = vc4_hdmi_dt_match,
 651         },
 652 };