drivers/gpu/drm/vc4/vc4_hdmi.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /**
  21  * DOC: VC4 Falcon HDMI module
  22  *
  23  * The HDMI core has a state machine and a PHY.  Most of the unit
  24  * operates off of the HSM clock from CPRMAN.  It also internally uses
  25  * the PLLH_PIX clock for the PHY.
  26  */
  27
  28 #include "drm_atomic_helper.h"
  29 #include "drm_crtc_helper.h"
  30 #include "drm_edid.h"
  31 #include "linux/clk.h"
  32 #include "linux/component.h"
  33 #include "linux/i2c.h"
  34 #include "linux/of_gpio.h"
  35 #include "linux/of_platform.h"
  36 #include "vc4_drv.h"
  37 #include "vc4_regs.h"
  38
  39 /* General HDMI hardware state. */
  40 struct vc4_hdmi {
  41         struct platform_device *pdev;
  42
  43         struct drm_encoder *encoder;
  44         struct drm_connector *connector;
  45
  46         struct i2c_adapter *ddc;
  47         void __iomem *hdmicore_regs;
  48         void __iomem *hd_regs;
  49         int hpd_gpio;
  50         bool hpd_active_low;
  51
  52         struct clk *pixel_clock;
  53         struct clk *hsm_clock;
  54 };
  55
  56 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
  57 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
  58 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
  59 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
  60
  61 /* VC4 HDMI encoder KMS struct */
  62 struct vc4_hdmi_encoder {
  63         struct vc4_encoder base;
  64         bool hdmi_monitor;
  65 };
  66
  67 static inline struct vc4_hdmi_encoder *
  68 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
  69 {
  70         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
  71 }
  72
  73 /* VC4 HDMI connector KMS struct */
  74 struct vc4_hdmi_connector {
  75         struct drm_connector base;
  76
  77         /* Since the connector is attached to just the one encoder,
  78          * this is the reference to it so we can do the best_encoder()
  79          * hook.
  80          */
  81         struct drm_encoder *encoder;
  82 };
  83
  84 static inline struct vc4_hdmi_connector *
  85 to_vc4_hdmi_connector(struct drm_connector *connector)
  86 {
  87         return container_of(connector, struct vc4_hdmi_connector, base);
  88 }
  89
  90 #define HDMI_REG(reg) { reg, #reg }
  91 static const struct {
  92         u32 reg;
  93         const char *name;
  94 } hdmi_regs[] = {
  95         HDMI_REG(VC4_HDMI_CORE_REV),
  96         HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
  97         HDMI_REG(VC4_HDMI_HOTPLUG_INT),
  98         HDMI_REG(VC4_HDMI_HOTPLUG),
  99         HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
 100         HDMI_REG(VC4_HDMI_HORZA),
 101         HDMI_REG(VC4_HDMI_HORZB),
 102         HDMI_REG(VC4_HDMI_FIFO_CTL),
 103         HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
 104         HDMI_REG(VC4_HDMI_VERTA0),
 105         HDMI_REG(VC4_HDMI_VERTA1),
 106         HDMI_REG(VC4_HDMI_VERTB0),
 107         HDMI_REG(VC4_HDMI_VERTB1),
 108         HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
 109 };
 110
 111 static const struct {
 112         u32 reg;
 113         const char *name;
 114 } hd_regs[] = {
 115         HDMI_REG(VC4_HD_M_CTL),
 116         HDMI_REG(VC4_HD_MAI_CTL),
 117         HDMI_REG(VC4_HD_VID_CTL),
 118         HDMI_REG(VC4_HD_CSC_CTL),
 119         HDMI_REG(VC4_HD_FRAME_COUNT),
 120 };
 121
 122 #ifdef CONFIG_DEBUG_FS
 123 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 124 {
 125         struct drm_info_node *node = (struct drm_info_node *)m->private;
 126         struct drm_device *dev = node->minor->dev;
 127         struct vc4_dev *vc4 = to_vc4_dev(dev);
 128         int i;
 129
 130         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 131                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 132                            hdmi_regs[i].name, hdmi_regs[i].reg,
 133                            HDMI_READ(hdmi_regs[i].reg));
 134         }
 135
 136         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 137                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 138                            hd_regs[i].name, hd_regs[i].reg,
 139                            HD_READ(hd_regs[i].reg));
 140         }
 141
 142         return 0;
 143 }
 144 #endif /* CONFIG_DEBUG_FS */
 145
 146 static void vc4_hdmi_dump_regs(struct drm_device *dev)
 147 {
 148         struct vc4_dev *vc4 = to_vc4_dev(dev);
 149         int i;
 150
 151         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 152                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 153                          hdmi_regs[i].reg, hdmi_regs[i].name,
 154                          HDMI_READ(hdmi_regs[i].reg));
 155         }
 156         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 157                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 158                          hd_regs[i].reg, hd_regs[i].name,
 159                          HD_READ(hd_regs[i].reg));
 160         }
 161 }
 162
 163 static enum drm_connector_status
 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 165 {
 166         struct drm_device *dev = connector->dev;
 167         struct vc4_dev *vc4 = to_vc4_dev(dev);
 168
 169         if (vc4->hdmi->hpd_gpio) {
 170                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 171                     vc4->hdmi->hpd_active_low)
 172                         return connector_status_connected;
 173                 else
 174                         return connector_status_disconnected;
 175         }
 176
 177         if (drm_probe_ddc(vc4->hdmi->ddc))
 178                 return connector_status_connected;
 179
 180         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 181                 return connector_status_connected;
 182         else
 183                 return connector_status_disconnected;
 184 }
 185
 186 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 187 {
 188         drm_connector_unregister(connector);
 189         drm_connector_cleanup(connector);
 190 }
 191
 192 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 193 {
 194         struct vc4_hdmi_connector *vc4_connector =
 195                 to_vc4_hdmi_connector(connector);
 196         struct drm_encoder *encoder = vc4_connector->encoder;
 197         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 198         struct drm_device *dev = connector->dev;
 199         struct vc4_dev *vc4 = to_vc4_dev(dev);
 200         int ret = 0;
 201         struct edid *edid;
 202
 203         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 204         if (!edid)
 205                 return -ENODEV;
 206
 207         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 208         drm_mode_connector_update_edid_property(connector, edid);
 209         ret = drm_add_edid_modes(connector, edid);
 210
 211         return ret;
 212 }
 213
 214 /*
 215  * drm_helper_probe_single_connector_modes() applies drm_mode_set_crtcinfo to
 216  * all modes with flag CRTC_INTERLACE_HALVE_V. We don't want this, as it
 217  * screws up vblank timestamping for interlaced modes, so fix it up.
 218  */
 219 static int vc4_hdmi_connector_probe_modes(struct drm_connector *connector,
 220                                           uint32_t maxX, uint32_t maxY)
 221 {
 222         struct drm_display_mode *mode;
 223         int count;
 224
 225         count = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
 226         if (count == 0)
 227                 return 0;
 228
 229         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed adapted modes :\n",
 230                       connector->base.id, connector->name);
 231         list_for_each_entry(mode, &connector->modes, head) {
 232                 drm_mode_set_crtcinfo(mode, 0);
 233                 drm_mode_debug_printmodeline(mode);
 234         }
 235
 236         return count;
 237 }
 238
 239 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 240         .dpms = drm_atomic_helper_connector_dpms,
 241         .detect = vc4_hdmi_connector_detect,
 242         .fill_modes = vc4_hdmi_connector_probe_modes,
 243         .destroy = vc4_hdmi_connector_destroy,
 244         .reset = drm_atomic_helper_connector_reset,
 245         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 246         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 247 };
 248
 249 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 250         .get_modes = vc4_hdmi_connector_get_modes,
 251 };
 252
 253 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 254                                                      struct drm_encoder *encoder)
 255 {
 256         struct drm_connector *connector = NULL;
 257         struct vc4_hdmi_connector *hdmi_connector;
 258         int ret = 0;
 259
 260         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 261                                       GFP_KERNEL);
 262         if (!hdmi_connector) {
 263                 ret = -ENOMEM;
 264                 goto fail;
 265         }
 266         connector = &hdmi_connector->base;
 267
 268         hdmi_connector->encoder = encoder;
 269
 270         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 271                            DRM_MODE_CONNECTOR_HDMIA);
 272         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 273
 274         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 275                              DRM_CONNECTOR_POLL_DISCONNECT);
 276
 277         connector->interlace_allowed = 1;
 278         connector->doublescan_allowed = 0;
 279
 280         drm_mode_connector_attach_encoder(connector, encoder);
 281
 282         return connector;
 283
 284  fail:
 285         if (connector)
 286                 vc4_hdmi_connector_destroy(connector);
 287
 288         return ERR_PTR(ret);
 289 }
 290
 291 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 292 {
 293         drm_encoder_cleanup(encoder);
 294 }
 295
 296 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 297         .destroy = vc4_hdmi_encoder_destroy,
 298 };
 299
 300 static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
 301                                       struct drm_display_mode *unadjusted_mode,
 302                                       struct drm_display_mode *mode)
 303 {
 304         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 305         struct drm_device *dev = encoder->dev;
 306         struct vc4_dev *vc4 = to_vc4_dev(dev);
 307         bool debug_dump_regs = false;
 308         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 309         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 310         u32 vactive = (mode->vdisplay >>
 311                        ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
 312         u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 313                                    VC4_HDMI_VERTA_VSP) |
 314                      VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 315                                    VC4_HDMI_VERTA_VFP) |
 316                      VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL));
 317         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 318                      VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
 319                                    VC4_HDMI_VERTB_VBP));
 320         u32 csc_ctl;
 321
 322         if (debug_dump_regs) {
 323                 DRM_INFO("HDMI regs before:\n");
 324                 vc4_hdmi_dump_regs(dev);
 325         }
 326
 327         HD_WRITE(VC4_HD_VID_CTL, 0);
 328
 329         clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);
 330
 331         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 332                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 333                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 334                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 335
 336         HDMI_WRITE(VC4_HDMI_HORZA,
 337                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 338                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 339                    VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));
 340
 341         HDMI_WRITE(VC4_HDMI_HORZB,
 342                    VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 343                                  VC4_HDMI_HORZB_HBP) |
 344                    VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 345                                  VC4_HDMI_HORZB_HSP) |
 346                    VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 347                                  VC4_HDMI_HORZB_HFP));
 348
 349         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 350         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 351
 352         HDMI_WRITE(VC4_HDMI_VERTB0, vertb);
 353         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 354
 355         HD_WRITE(VC4_HD_VID_CTL,
 356                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 357                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 358
 359         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 360                                 VC4_HD_CSC_CTL_ORDER);
 361
 362         if (vc4_encoder->hdmi_monitor && drm_match_cea_mode(mode) > 1) {
 363                 /* CEA VICs other than #1 requre limited range RGB
 364                  * output.  Apply a colorspace conversion to squash
 365                  * 0-255 down to 16-235.  The matrix here is:
 366                  *
 367                  * [ 0      0      0.8594 16]
 368                  * [ 0      0.8594 0      16]
 369                  * [ 0.8594 0      0      16]
 370                  * [ 0      0      0       1]
 371                  */
 372                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 373                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 374                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 375                                          VC4_HD_CSC_CTL_MODE);
 376
 377                 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
 378                 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
 379                 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
 380                 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
 381                 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
 382                 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
 383         }
 384
 385         /* The RGB order applies even when CSC is disabled. */
 386         HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
 387
 388         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 389
 390         if (debug_dump_regs) {
 391                 DRM_INFO("HDMI regs after:\n");
 392                 vc4_hdmi_dump_regs(dev);
 393         }
 394 }
 395
 396 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 397 {
 398         struct drm_device *dev = encoder->dev;
 399         struct vc4_dev *vc4 = to_vc4_dev(dev);
 400
 401         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 402         HD_WRITE(VC4_HD_VID_CTL,
 403                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 404 }
 405
 406 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 407 {
 408         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 409         struct drm_device *dev = encoder->dev;
 410         struct vc4_dev *vc4 = to_vc4_dev(dev);
 411         int ret;
 412
 413         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 414
 415         HD_WRITE(VC4_HD_VID_CTL,
 416                  HD_READ(VC4_HD_VID_CTL) |
 417                  VC4_HD_VID_CTL_ENABLE |
 418                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 419                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 420
 421         if (vc4_encoder->hdmi_monitor) {
 422                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 423                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 424                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 425
 426                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 427                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 428                 WARN_ONCE(ret, "Timeout waiting for "
 429                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 430         } else {
 431                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 432                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 433                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 434                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 435                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 436                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 437
 438                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 439                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 440                 WARN_ONCE(ret, "Timeout waiting for "
 441                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 442         }
 443
 444         if (vc4_encoder->hdmi_monitor) {
 445                 u32 drift;
 446
 447                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 448                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 449                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 450                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 451                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 452
 453                 /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
 454                  * up the infoframe.
 455                  */
 456
 457                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 458                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 459
 460                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 461                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 462                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 463                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 464                 udelay(1000);
 465                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 466                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 467                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 468                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 469
 470                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 471                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 472                 WARN_ONCE(ret, "Timeout waiting for "
 473                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 474         }
 475 }
 476
 477 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 478         .mode_set = vc4_hdmi_encoder_mode_set,
 479         .disable = vc4_hdmi_encoder_disable,
 480         .enable = vc4_hdmi_encoder_enable,
 481 };
 482
 483 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
 484 {
 485         struct platform_device *pdev = to_platform_device(dev);
 486         struct drm_device *drm = dev_get_drvdata(master);
 487         struct vc4_dev *vc4 = drm->dev_private;
 488         struct vc4_hdmi *hdmi;
 489         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
 490         struct device_node *ddc_node;
 491         u32 value;
 492         int ret;
 493
 494         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 495         if (!hdmi)
 496                 return -ENOMEM;
 497
 498         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
 499                                         GFP_KERNEL);
 500         if (!vc4_hdmi_encoder)
 501                 return -ENOMEM;
 502         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
 503         hdmi->encoder = &vc4_hdmi_encoder->base.base;
 504
 505         hdmi->pdev = pdev;
 506         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
 507         if (IS_ERR(hdmi->hdmicore_regs))
 508                 return PTR_ERR(hdmi->hdmicore_regs);
 509
 510         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
 511         if (IS_ERR(hdmi->hd_regs))
 512                 return PTR_ERR(hdmi->hd_regs);
 513
 514         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
 515         if (IS_ERR(hdmi->pixel_clock)) {
 516                 DRM_ERROR("Failed to get pixel clock\n");
 517                 return PTR_ERR(hdmi->pixel_clock);
 518         }
 519         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
 520         if (IS_ERR(hdmi->hsm_clock)) {
 521                 DRM_ERROR("Failed to get HDMI state machine clock\n");
 522                 return PTR_ERR(hdmi->hsm_clock);
 523         }
 524
 525         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
 526         if (!ddc_node) {
 527                 DRM_ERROR("Failed to find ddc node in device tree\n");
 528                 return -ENODEV;
 529         }
 530
 531         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
 532         of_node_put(ddc_node);
 533         if (!hdmi->ddc) {
 534                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
 535                 return -EPROBE_DEFER;
 536         }
 537
 538         /* Enable the clocks at startup.  We can't quite recover from
 539          * turning off the pixel clock during disable/enables yet, so
 540          * it's always running.
 541          */
 542         ret = clk_prepare_enable(hdmi->pixel_clock);
 543         if (ret) {
 544                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 545                 goto err_put_i2c;
 546         }
 547
 548         /* This is the rate that is set by the firmware.  The number
 549          * needs to be a bit higher than the pixel clock rate
 550          * (generally 148.5Mhz).
 551          */
 552         ret = clk_set_rate(hdmi->hsm_clock, 163682864);
 553         if (ret) {
 554                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 555                 goto err_unprepare_pix;
 556         }
 557
 558         ret = clk_prepare_enable(hdmi->hsm_clock);
 559         if (ret) {
 560                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
 561                           ret);
 562                 goto err_unprepare_pix;
 563         }
 564
 565         /* Only use the GPIO HPD pin if present in the DT, otherwise
 566          * we'll use the HDMI core's register.
 567          */
 568         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
 569                 enum of_gpio_flags hpd_gpio_flags;
 570
 571                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
 572                                                          "hpd-gpios", 0,
 573                                                          &hpd_gpio_flags);
 574                 if (hdmi->hpd_gpio < 0) {
 575                         ret = hdmi->hpd_gpio;
 576                         goto err_unprepare_hsm;
 577                 }
 578
 579                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
 580         }
 581
 582         vc4->hdmi = hdmi;
 583
 584         /* HDMI core must be enabled. */
 585         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
 586                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
 587                 udelay(1);
 588                 HD_WRITE(VC4_HD_M_CTL, 0);
 589
 590                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
 591
 592                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 593                            VC4_HDMI_SW_RESET_HDMI |
 594                            VC4_HDMI_SW_RESET_FORMAT_DETECT);
 595
 596                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 597
 598                 /* PHY should be in reset, like
 599                  * vc4_hdmi_encoder_disable() does.
 600                  */
 601                 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 602         }
 603
 604         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
 605                          DRM_MODE_ENCODER_TMDS, NULL);
 606         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
 607
 608         hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
 609         if (IS_ERR(hdmi->connector)) {
 610                 ret = PTR_ERR(hdmi->connector);
 611                 goto err_destroy_encoder;
 612         }
 613
 614         return 0;
 615
 616 err_destroy_encoder:
 617         vc4_hdmi_encoder_destroy(hdmi->encoder);
 618 err_unprepare_hsm:
 619         clk_disable_unprepare(hdmi->hsm_clock);
 620 err_unprepare_pix:
 621         clk_disable_unprepare(hdmi->pixel_clock);
 622 err_put_i2c:
 623         put_device(&hdmi->ddc->dev);
 624
 625         return ret;
 626 }
 627
 628 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
 629                             void *data)
 630 {
 631         struct drm_device *drm = dev_get_drvdata(master);
 632         struct vc4_dev *vc4 = drm->dev_private;
 633         struct vc4_hdmi *hdmi = vc4->hdmi;
 634
 635         vc4_hdmi_connector_destroy(hdmi->connector);
 636         vc4_hdmi_encoder_destroy(hdmi->encoder);
 637
 638         clk_disable_unprepare(hdmi->pixel_clock);
 639         clk_disable_unprepare(hdmi->hsm_clock);
 640         put_device(&hdmi->ddc->dev);
 641
 642         vc4->hdmi = NULL;
 643 }
 644
 645 static const struct component_ops vc4_hdmi_ops = {
 646         .bind   = vc4_hdmi_bind,
 647         .unbind = vc4_hdmi_unbind,
 648 };
 649
 650 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
 651 {
 652         return component_add(&pdev->dev, &vc4_hdmi_ops);
 653 }
 654
 655 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
 656 {
 657         component_del(&pdev->dev, &vc4_hdmi_ops);
 658         return 0;
 659 }
 660
 661 static const struct of_device_id vc4_hdmi_dt_match[] = {
 662         { .compatible = "brcm,bcm2835-hdmi" },
 663         {}
 664 };
 665
 666 struct platform_driver vc4_hdmi_driver = {
 667         .probe = vc4_hdmi_dev_probe,
 668         .remove = vc4_hdmi_dev_remove,
 669         .driver = {
 670                 .name = "vc4_hdmi",
 671                 .of_match_table = vc4_hdmi_dt_match,
 672         },
 673 };