drivers/hwtracing/coresight/coresight-etm3x.c

   1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/cpu.h>
  28 #include <linux/of.h>
  29 #include <linux/coresight.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/uaccess.h>
  33 #include <asm/sections.h>
  34
  35 #include "coresight-etm.h"
  36
  37 static int boot_enable;
  38 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  39
  40 /* The number of ETM/PTM currently registered */
  41 static int etm_count;
  42 static struct etm_drvdata *etmdrvdata[NR_CPUS];
  43
  44 static inline void etm_writel(struct etm_drvdata *drvdata,
  45                               u32 val, u32 off)
  46 {
  47         if (drvdata->use_cp14) {
  48                 if (etm_writel_cp14(off, val)) {
  49                         dev_err(drvdata->dev,
  50                                 "invalid CP14 access to ETM reg: %#x", off);
  51                 }
  52         } else {
  53                 writel_relaxed(val, drvdata->base + off);
  54         }
  55 }
  56
  57 static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
  58 {
  59         u32 val;
  60
  61         if (drvdata->use_cp14) {
  62                 if (etm_readl_cp14(off, &val)) {
  63                         dev_err(drvdata->dev,
  64                                 "invalid CP14 access to ETM reg: %#x", off);
  65                 }
  66         } else {
  67                 val = readl_relaxed(drvdata->base + off);
  68         }
  69
  70         return val;
  71 }
  72
  73 /*
  74  * Memory mapped writes to clear os lock are not supported on some processors
  75  * and OS lock must be unlocked before any memory mapped access on such
  76  * processors, otherwise memory mapped reads/writes will be invalid.
  77  */
  78 static void etm_os_unlock(void *info)
  79 {
  80         struct etm_drvdata *drvdata = (struct etm_drvdata *)info;
  81         /* Writing any value to ETMOSLAR unlocks the trace registers */
  82         etm_writel(drvdata, 0x0, ETMOSLAR);
  83         isb();
  84 }
  85
  86 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
  87 {
  88         u32 etmcr;
  89
  90         /* Ensure pending cp14 accesses complete before setting pwrdwn */
  91         mb();
  92         isb();
  93         etmcr = etm_readl(drvdata, ETMCR);
  94         etmcr |= ETMCR_PWD_DWN;
  95         etm_writel(drvdata, etmcr, ETMCR);
  96 }
  97
  98 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
  99 {
 100         u32 etmcr;
 101
 102         etmcr = etm_readl(drvdata, ETMCR);
 103         etmcr &= ~ETMCR_PWD_DWN;
 104         etm_writel(drvdata, etmcr, ETMCR);
 105         /* Ensure pwrup completes before subsequent cp14 accesses */
 106         mb();
 107         isb();
 108 }
 109
 110 static void etm_set_pwrup(struct etm_drvdata *drvdata)
 111 {
 112         u32 etmpdcr;
 113
 114         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 115         etmpdcr |= ETMPDCR_PWD_UP;
 116         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 117         /* Ensure pwrup completes before subsequent cp14 accesses */
 118         mb();
 119         isb();
 120 }
 121
 122 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
 123 {
 124         u32 etmpdcr;
 125
 126         /* Ensure pending cp14 accesses complete before clearing pwrup */
 127         mb();
 128         isb();
 129         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 130         etmpdcr &= ~ETMPDCR_PWD_UP;
 131         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 132 }
 133
 134 /**
 135  * coresight_timeout_etm - loop until a bit has changed to a specific state.
 136  * @drvdata: etm's private data structure.
 137  * @offset: address of a register, starting from @addr.
 138  * @position: the position of the bit of interest.
 139  * @value: the value the bit should have.
 140  *
 141  * Basically the same as @coresight_timeout except for the register access
 142  * method where we have to account for CP14 configurations.
 143
 144  * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
 145  * TIMEOUT_US has elapsed, which ever happens first.
 146  */
 147
 148 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
 149                                   int position, int value)
 150 {
 151         int i;
 152         u32 val;
 153
 154         for (i = TIMEOUT_US; i > 0; i--) {
 155                 val = etm_readl(drvdata, offset);
 156                 /* Waiting on the bit to go from 0 to 1 */
 157                 if (value) {
 158                         if (val & BIT(position))
 159                                 return 0;
 160                 /* Waiting on the bit to go from 1 to 0 */
 161                 } else {
 162                         if (!(val & BIT(position)))
 163                                 return 0;
 164                 }
 165
 166                 /*
 167                  * Delay is arbitrary - the specification doesn't say how long
 168                  * we are expected to wait.  Extra check required to make sure
 169                  * we don't wait needlessly on the last iteration.
 170                  */
 171                 if (i - 1)
 172                         udelay(1);
 173         }
 174
 175         return -EAGAIN;
 176 }
 177
 178
 179 static void etm_set_prog(struct etm_drvdata *drvdata)
 180 {
 181         u32 etmcr;
 182
 183         etmcr = etm_readl(drvdata, ETMCR);
 184         etmcr |= ETMCR_ETM_PRG;
 185         etm_writel(drvdata, etmcr, ETMCR);
 186         /*
 187          * Recommended by spec for cp14 accesses to ensure etmcr write is
 188          * complete before polling etmsr
 189          */
 190         isb();
 191         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
 192                 dev_err(drvdata->dev,
 193                         "timeout observed when probing at offset %#x\n", ETMSR);
 194         }
 195 }
 196
 197 static void etm_clr_prog(struct etm_drvdata *drvdata)
 198 {
 199         u32 etmcr;
 200
 201         etmcr = etm_readl(drvdata, ETMCR);
 202         etmcr &= ~ETMCR_ETM_PRG;
 203         etm_writel(drvdata, etmcr, ETMCR);
 204         /*
 205          * Recommended by spec for cp14 accesses to ensure etmcr write is
 206          * complete before polling etmsr
 207          */
 208         isb();
 209         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
 210                 dev_err(drvdata->dev,
 211                         "timeout observed when probing at offset %#x\n", ETMSR);
 212         }
 213 }
 214
 215 static void etm_set_default(struct etm_drvdata *drvdata)
 216 {
 217         int i;
 218
 219         drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 220         drvdata->enable_event = ETM_HARD_WIRE_RES_A;
 221
 222         drvdata->seq_12_event = ETM_DEFAULT_EVENT_VAL;
 223         drvdata->seq_21_event = ETM_DEFAULT_EVENT_VAL;
 224         drvdata->seq_23_event = ETM_DEFAULT_EVENT_VAL;
 225         drvdata->seq_31_event = ETM_DEFAULT_EVENT_VAL;
 226         drvdata->seq_32_event = ETM_DEFAULT_EVENT_VAL;
 227         drvdata->seq_13_event = ETM_DEFAULT_EVENT_VAL;
 228         drvdata->timestamp_event = ETM_DEFAULT_EVENT_VAL;
 229
 230         for (i = 0; i < drvdata->nr_cntr; i++) {
 231                 drvdata->cntr_rld_val[i] = 0x0;
 232                 drvdata->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
 233                 drvdata->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
 234                 drvdata->cntr_val[i] = 0x0;
 235         }
 236
 237         drvdata->seq_curr_state = 0x0;
 238         drvdata->ctxid_idx = 0x0;
 239         for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
 240                 drvdata->ctxid_val[i] = 0x0;
 241         drvdata->ctxid_mask = 0x0;
 242 }
 243
 244 static void etm_enable_hw(void *info)
 245 {
 246         int i;
 247         u32 etmcr;
 248         struct etm_drvdata *drvdata = info;
 249
 250         CS_UNLOCK(drvdata->base);
 251
 252         /* Turn engine on */
 253         etm_clr_pwrdwn(drvdata);
 254         /* Apply power to trace registers */
 255         etm_set_pwrup(drvdata);
 256         /* Make sure all registers are accessible */
 257         etm_os_unlock(drvdata);
 258
 259         etm_set_prog(drvdata);
 260
 261         etmcr = etm_readl(drvdata, ETMCR);
 262         etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG);
 263         etmcr |= drvdata->port_size;
 264         etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR);
 265         etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER);
 266         etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR);
 267         etm_writel(drvdata, drvdata->enable_event, ETMTEEVR);
 268         etm_writel(drvdata, drvdata->enable_ctrl1, ETMTECR1);
 269         etm_writel(drvdata, drvdata->fifofull_level, ETMFFLR);
 270         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 271                 etm_writel(drvdata, drvdata->addr_val[i], ETMACVRn(i));
 272                 etm_writel(drvdata, drvdata->addr_acctype[i], ETMACTRn(i));
 273         }
 274         for (i = 0; i < drvdata->nr_cntr; i++) {
 275                 etm_writel(drvdata, drvdata->cntr_rld_val[i], ETMCNTRLDVRn(i));
 276                 etm_writel(drvdata, drvdata->cntr_event[i], ETMCNTENRn(i));
 277                 etm_writel(drvdata, drvdata->cntr_rld_event[i],
 278                            ETMCNTRLDEVRn(i));
 279                 etm_writel(drvdata, drvdata->cntr_val[i], ETMCNTVRn(i));
 280         }
 281         etm_writel(drvdata, drvdata->seq_12_event, ETMSQ12EVR);
 282         etm_writel(drvdata, drvdata->seq_21_event, ETMSQ21EVR);
 283         etm_writel(drvdata, drvdata->seq_23_event, ETMSQ23EVR);
 284         etm_writel(drvdata, drvdata->seq_31_event, ETMSQ31EVR);
 285         etm_writel(drvdata, drvdata->seq_32_event, ETMSQ32EVR);
 286         etm_writel(drvdata, drvdata->seq_13_event, ETMSQ13EVR);
 287         etm_writel(drvdata, drvdata->seq_curr_state, ETMSQR);
 288         for (i = 0; i < drvdata->nr_ext_out; i++)
 289                 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
 290         for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
 291                 etm_writel(drvdata, drvdata->ctxid_val[i], ETMCIDCVRn(i));
 292         etm_writel(drvdata, drvdata->ctxid_mask, ETMCIDCMR);
 293         etm_writel(drvdata, drvdata->sync_freq, ETMSYNCFR);
 294         /* No external input selected */
 295         etm_writel(drvdata, 0x0, ETMEXTINSELR);
 296         etm_writel(drvdata, drvdata->timestamp_event, ETMTSEVR);
 297         /* No auxiliary control selected */
 298         etm_writel(drvdata, 0x0, ETMAUXCR);
 299         etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
 300         /* No VMID comparator value selected */
 301         etm_writel(drvdata, 0x0, ETMVMIDCVR);
 302
 303         /* Ensures trace output is enabled from this ETM */
 304         etm_writel(drvdata, drvdata->ctrl | ETMCR_ETM_EN | etmcr, ETMCR);
 305
 306         etm_clr_prog(drvdata);
 307         CS_LOCK(drvdata->base);
 308
 309         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 310 }
 311
 312 static int etm_trace_id_simple(struct etm_drvdata *drvdata)
 313 {
 314         if (!drvdata->enable)
 315                 return drvdata->traceid;
 316
 317         return (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
 318 }
 319
 320 static int etm_trace_id(struct coresight_device *csdev)
 321 {
 322         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 323         unsigned long flags;
 324         int trace_id = -1;
 325
 326         if (!drvdata->enable)
 327                 return drvdata->traceid;
 328         pm_runtime_get_sync(csdev->dev.parent);
 329
 330         spin_lock_irqsave(&drvdata->spinlock, flags);
 331
 332         CS_UNLOCK(drvdata->base);
 333         trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
 334         CS_LOCK(drvdata->base);
 335
 336         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 337         pm_runtime_put(csdev->dev.parent);
 338
 339         return trace_id;
 340 }
 341
 342 static int etm_enable(struct coresight_device *csdev)
 343 {
 344         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 345         int ret;
 346
 347         pm_runtime_get_sync(csdev->dev.parent);
 348         spin_lock(&drvdata->spinlock);
 349
 350         /*
 351          * Configure the ETM only if the CPU is online.  If it isn't online
 352          * hw configuration will take place when 'CPU_STARTING' is received
 353          * in @etm_cpu_callback.
 354          */
 355         if (cpu_online(drvdata->cpu)) {
 356                 ret = smp_call_function_single(drvdata->cpu,
 357                                                etm_enable_hw, drvdata, 1);
 358                 if (ret)
 359                         goto err;
 360         }
 361
 362         drvdata->enable = true;
 363         drvdata->sticky_enable = true;
 364
 365         spin_unlock(&drvdata->spinlock);
 366
 367         dev_info(drvdata->dev, "ETM tracing enabled\n");
 368         return 0;
 369 err:
 370         spin_unlock(&drvdata->spinlock);
 371         pm_runtime_put(csdev->dev.parent);
 372         return ret;
 373 }
 374
 375 static void etm_disable_hw(void *info)
 376 {
 377         int i;
 378         struct etm_drvdata *drvdata = info;
 379
 380         CS_UNLOCK(drvdata->base);
 381         etm_set_prog(drvdata);
 382
 383         /* Program trace enable to low by using always false event */
 384         etm_writel(drvdata, ETM_HARD_WIRE_RES_A | ETM_EVENT_NOT_A, ETMTEEVR);
 385
 386         /* Read back sequencer and counters for post trace analysis */
 387         drvdata->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
 388
 389         for (i = 0; i < drvdata->nr_cntr; i++)
 390                 drvdata->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
 391
 392         etm_set_pwrdwn(drvdata);
 393         CS_LOCK(drvdata->base);
 394
 395         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 396 }
 397
 398 static void etm_disable(struct coresight_device *csdev)
 399 {
 400         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 401
 402         /*
 403          * Taking hotplug lock here protects from clocks getting disabled
 404          * with tracing being left on (crash scenario) if user disable occurs
 405          * after cpu online mask indicates the cpu is offline but before the
 406          * DYING hotplug callback is serviced by the ETM driver.
 407          */
 408         get_online_cpus();
 409         spin_lock(&drvdata->spinlock);
 410
 411         /*
 412          * Executing etm_disable_hw on the cpu whose ETM is being disabled
 413          * ensures that register writes occur when cpu is powered.
 414          */
 415         smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
 416         drvdata->enable = false;
 417
 418         spin_unlock(&drvdata->spinlock);
 419         put_online_cpus();
 420         pm_runtime_put(csdev->dev.parent);
 421
 422         dev_info(drvdata->dev, "ETM tracing disabled\n");
 423 }
 424
 425 static const struct coresight_ops_source etm_source_ops = {
 426         .trace_id       = etm_trace_id,
 427         .enable         = etm_enable,
 428         .disable        = etm_disable,
 429 };
 430
 431 static const struct coresight_ops etm_cs_ops = {
 432         .source_ops     = &etm_source_ops,
 433 };
 434
 435 static ssize_t nr_addr_cmp_show(struct device *dev,
 436                                 struct device_attribute *attr, char *buf)
 437 {
 438         unsigned long val;
 439         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 440
 441         val = drvdata->nr_addr_cmp;
 442         return sprintf(buf, "%#lx\n", val);
 443 }
 444 static DEVICE_ATTR_RO(nr_addr_cmp);
 445
 446 static ssize_t nr_cntr_show(struct device *dev,
 447                             struct device_attribute *attr, char *buf)
 448 {       unsigned long val;
 449         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 450
 451         val = drvdata->nr_cntr;
 452         return sprintf(buf, "%#lx\n", val);
 453 }
 454 static DEVICE_ATTR_RO(nr_cntr);
 455
 456 static ssize_t nr_ctxid_cmp_show(struct device *dev,
 457                                  struct device_attribute *attr, char *buf)
 458 {
 459         unsigned long val;
 460         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 461
 462         val = drvdata->nr_ctxid_cmp;
 463         return sprintf(buf, "%#lx\n", val);
 464 }
 465 static DEVICE_ATTR_RO(nr_ctxid_cmp);
 466
 467 static ssize_t etmsr_show(struct device *dev,
 468                           struct device_attribute *attr, char *buf)
 469 {
 470         unsigned long flags, val;
 471         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 472
 473         pm_runtime_get_sync(drvdata->dev);
 474         spin_lock_irqsave(&drvdata->spinlock, flags);
 475         CS_UNLOCK(drvdata->base);
 476
 477         val = etm_readl(drvdata, ETMSR);
 478
 479         CS_LOCK(drvdata->base);
 480         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 481         pm_runtime_put(drvdata->dev);
 482
 483         return sprintf(buf, "%#lx\n", val);
 484 }
 485 static DEVICE_ATTR_RO(etmsr);
 486
 487 static ssize_t reset_store(struct device *dev,
 488                            struct device_attribute *attr,
 489                            const char *buf, size_t size)
 490 {
 491         int i, ret;
 492         unsigned long val;
 493         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 494
 495         ret = kstrtoul(buf, 16, &val);
 496         if (ret)
 497                 return ret;
 498
 499         if (val) {
 500                 spin_lock(&drvdata->spinlock);
 501                 drvdata->mode = ETM_MODE_EXCLUDE;
 502                 drvdata->ctrl = 0x0;
 503                 drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 504                 drvdata->startstop_ctrl = 0x0;
 505                 drvdata->addr_idx = 0x0;
 506                 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 507                         drvdata->addr_val[i] = 0x0;
 508                         drvdata->addr_acctype[i] = 0x0;
 509                         drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;
 510                 }
 511                 drvdata->cntr_idx = 0x0;
 512
 513                 etm_set_default(drvdata);
 514                 spin_unlock(&drvdata->spinlock);
 515         }
 516
 517         return size;
 518 }
 519 static DEVICE_ATTR_WO(reset);
 520
 521 static ssize_t mode_show(struct device *dev,
 522                          struct device_attribute *attr, char *buf)
 523 {
 524         unsigned long val;
 525         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 526
 527         val = drvdata->mode;
 528         return sprintf(buf, "%#lx\n", val);
 529 }
 530
 531 static ssize_t mode_store(struct device *dev,
 532                           struct device_attribute *attr,
 533                           const char *buf, size_t size)
 534 {
 535         int ret;
 536         unsigned long val;
 537         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 538
 539         ret = kstrtoul(buf, 16, &val);
 540         if (ret)
 541                 return ret;
 542
 543         spin_lock(&drvdata->spinlock);
 544         drvdata->mode = val & ETM_MODE_ALL;
 545
 546         if (drvdata->mode & ETM_MODE_EXCLUDE)
 547                 drvdata->enable_ctrl1 |= ETMTECR1_INC_EXC;
 548         else
 549                 drvdata->enable_ctrl1 &= ~ETMTECR1_INC_EXC;
 550
 551         if (drvdata->mode & ETM_MODE_CYCACC)
 552                 drvdata->ctrl |= ETMCR_CYC_ACC;
 553         else
 554                 drvdata->ctrl &= ~ETMCR_CYC_ACC;
 555
 556         if (drvdata->mode & ETM_MODE_STALL) {
 557                 if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
 558                         dev_warn(drvdata->dev, "stall mode not supported\n");
 559                         ret = -EINVAL;
 560                         goto err_unlock;
 561                 }
 562                 drvdata->ctrl |= ETMCR_STALL_MODE;
 563          } else
 564                 drvdata->ctrl &= ~ETMCR_STALL_MODE;
 565
 566         if (drvdata->mode & ETM_MODE_TIMESTAMP) {
 567                 if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
 568                         dev_warn(drvdata->dev, "timestamp not supported\n");
 569                         ret = -EINVAL;
 570                         goto err_unlock;
 571                 }
 572                 drvdata->ctrl |= ETMCR_TIMESTAMP_EN;
 573         } else
 574                 drvdata->ctrl &= ~ETMCR_TIMESTAMP_EN;
 575
 576         if (drvdata->mode & ETM_MODE_CTXID)
 577                 drvdata->ctrl |= ETMCR_CTXID_SIZE;
 578         else
 579                 drvdata->ctrl &= ~ETMCR_CTXID_SIZE;
 580         spin_unlock(&drvdata->spinlock);
 581
 582         return size;
 583
 584 err_unlock:
 585         spin_unlock(&drvdata->spinlock);
 586         return ret;
 587 }
 588 static DEVICE_ATTR_RW(mode);
 589
 590 static ssize_t trigger_event_show(struct device *dev,
 591                                   struct device_attribute *attr, char *buf)
 592 {
 593         unsigned long val;
 594         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 595
 596         val = drvdata->trigger_event;
 597         return sprintf(buf, "%#lx\n", val);
 598 }
 599
 600 static ssize_t trigger_event_store(struct device *dev,
 601                                    struct device_attribute *attr,
 602                                    const char *buf, size_t size)
 603 {
 604         int ret;
 605         unsigned long val;
 606         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 607
 608         ret = kstrtoul(buf, 16, &val);
 609         if (ret)
 610                 return ret;
 611
 612         drvdata->trigger_event = val & ETM_EVENT_MASK;
 613
 614         return size;
 615 }
 616 static DEVICE_ATTR_RW(trigger_event);
 617
 618 static ssize_t enable_event_show(struct device *dev,
 619                                  struct device_attribute *attr, char *buf)
 620 {
 621         unsigned long val;
 622         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 623
 624         val = drvdata->enable_event;
 625         return sprintf(buf, "%#lx\n", val);
 626 }
 627
 628 static ssize_t enable_event_store(struct device *dev,
 629                                   struct device_attribute *attr,
 630                                   const char *buf, size_t size)
 631 {
 632         int ret;
 633         unsigned long val;
 634         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 635
 636         ret = kstrtoul(buf, 16, &val);
 637         if (ret)
 638                 return ret;
 639
 640         drvdata->enable_event = val & ETM_EVENT_MASK;
 641
 642         return size;
 643 }
 644 static DEVICE_ATTR_RW(enable_event);
 645
 646 static ssize_t fifofull_level_show(struct device *dev,
 647                                    struct device_attribute *attr, char *buf)
 648 {
 649         unsigned long val;
 650         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 651
 652         val = drvdata->fifofull_level;
 653         return sprintf(buf, "%#lx\n", val);
 654 }
 655
 656 static ssize_t fifofull_level_store(struct device *dev,
 657                                     struct device_attribute *attr,
 658                                     const char *buf, size_t size)
 659 {
 660         int ret;
 661         unsigned long val;
 662         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 663
 664         ret = kstrtoul(buf, 16, &val);
 665         if (ret)
 666                 return ret;
 667
 668         drvdata->fifofull_level = val;
 669
 670         return size;
 671 }
 672 static DEVICE_ATTR_RW(fifofull_level);
 673
 674 static ssize_t addr_idx_show(struct device *dev,
 675                              struct device_attribute *attr, char *buf)
 676 {
 677         unsigned long val;
 678         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 679
 680         val = drvdata->addr_idx;
 681         return sprintf(buf, "%#lx\n", val);
 682 }
 683
 684 static ssize_t addr_idx_store(struct device *dev,
 685                               struct device_attribute *attr,
 686                               const char *buf, size_t size)
 687 {
 688         int ret;
 689         unsigned long val;
 690         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 691
 692         ret = kstrtoul(buf, 16, &val);
 693         if (ret)
 694                 return ret;
 695
 696         if (val >= drvdata->nr_addr_cmp)
 697                 return -EINVAL;
 698
 699         /*
 700          * Use spinlock to ensure index doesn't change while it gets
 701          * dereferenced multiple times within a spinlock block elsewhere.
 702          */
 703         spin_lock(&drvdata->spinlock);
 704         drvdata->addr_idx = val;
 705         spin_unlock(&drvdata->spinlock);
 706
 707         return size;
 708 }
 709 static DEVICE_ATTR_RW(addr_idx);
 710
 711 static ssize_t addr_single_show(struct device *dev,
 712                                 struct device_attribute *attr, char *buf)
 713 {
 714         u8 idx;
 715         unsigned long val;
 716         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 717
 718         spin_lock(&drvdata->spinlock);
 719         idx = drvdata->addr_idx;
 720         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 721               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 722                 spin_unlock(&drvdata->spinlock);
 723                 return -EINVAL;
 724         }
 725
 726         val = drvdata->addr_val[idx];
 727         spin_unlock(&drvdata->spinlock);
 728
 729         return sprintf(buf, "%#lx\n", val);
 730 }
 731
 732 static ssize_t addr_single_store(struct device *dev,
 733                                  struct device_attribute *attr,
 734                                  const char *buf, size_t size)
 735 {
 736         u8 idx;
 737         int ret;
 738         unsigned long val;
 739         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 740
 741         ret = kstrtoul(buf, 16, &val);
 742         if (ret)
 743                 return ret;
 744
 745         spin_lock(&drvdata->spinlock);
 746         idx = drvdata->addr_idx;
 747         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 748               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 749                 spin_unlock(&drvdata->spinlock);
 750                 return -EINVAL;
 751         }
 752
 753         drvdata->addr_val[idx] = val;
 754         drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
 755         spin_unlock(&drvdata->spinlock);
 756
 757         return size;
 758 }
 759 static DEVICE_ATTR_RW(addr_single);
 760
 761 static ssize_t addr_range_show(struct device *dev,
 762                                struct device_attribute *attr, char *buf)
 763 {
 764         u8 idx;
 765         unsigned long val1, val2;
 766         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 767
 768         spin_lock(&drvdata->spinlock);
 769         idx = drvdata->addr_idx;
 770         if (idx % 2 != 0) {
 771                 spin_unlock(&drvdata->spinlock);
 772                 return -EPERM;
 773         }
 774         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 775                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 776               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 777                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 778                 spin_unlock(&drvdata->spinlock);
 779                 return -EPERM;
 780         }
 781
 782         val1 = drvdata->addr_val[idx];
 783         val2 = drvdata->addr_val[idx + 1];
 784         spin_unlock(&drvdata->spinlock);
 785
 786         return sprintf(buf, "%#lx %#lx\n", val1, val2);
 787 }
 788
 789 static ssize_t addr_range_store(struct device *dev,
 790                               struct device_attribute *attr,
 791                               const char *buf, size_t size)
 792 {
 793         u8 idx;
 794         unsigned long val1, val2;
 795         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 796
 797         if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
 798                 return -EINVAL;
 799         /* Lower address comparator cannot have a higher address value */
 800         if (val1 > val2)
 801                 return -EINVAL;
 802
 803         spin_lock(&drvdata->spinlock);
 804         idx = drvdata->addr_idx;
 805         if (idx % 2 != 0) {
 806                 spin_unlock(&drvdata->spinlock);
 807                 return -EPERM;
 808         }
 809         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 810                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 811               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 812                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 813                 spin_unlock(&drvdata->spinlock);
 814                 return -EPERM;
 815         }
 816
 817         drvdata->addr_val[idx] = val1;
 818         drvdata->addr_type[idx] = ETM_ADDR_TYPE_RANGE;
 819         drvdata->addr_val[idx + 1] = val2;
 820         drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
 821         drvdata->enable_ctrl1 |= (1 << (idx/2));
 822         spin_unlock(&drvdata->spinlock);
 823
 824         return size;
 825 }
 826 static DEVICE_ATTR_RW(addr_range);
 827
 828 static ssize_t addr_start_show(struct device *dev,
 829                                struct device_attribute *attr, char *buf)
 830 {
 831         u8 idx;
 832         unsigned long val;
 833         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 834
 835         spin_lock(&drvdata->spinlock);
 836         idx = drvdata->addr_idx;
 837         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 838               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 839                 spin_unlock(&drvdata->spinlock);
 840                 return -EPERM;
 841         }
 842
 843         val = drvdata->addr_val[idx];
 844         spin_unlock(&drvdata->spinlock);
 845
 846         return sprintf(buf, "%#lx\n", val);
 847 }
 848
 849 static ssize_t addr_start_store(struct device *dev,
 850                                 struct device_attribute *attr,
 851                                 const char *buf, size_t size)
 852 {
 853         u8 idx;
 854         int ret;
 855         unsigned long val;
 856         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 857
 858         ret = kstrtoul(buf, 16, &val);
 859         if (ret)
 860                 return ret;
 861
 862         spin_lock(&drvdata->spinlock);
 863         idx = drvdata->addr_idx;
 864         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 865               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 866                 spin_unlock(&drvdata->spinlock);
 867                 return -EPERM;
 868         }
 869
 870         drvdata->addr_val[idx] = val;
 871         drvdata->addr_type[idx] = ETM_ADDR_TYPE_START;
 872         drvdata->startstop_ctrl |= (1 << idx);
 873         drvdata->enable_ctrl1 |= BIT(25);
 874         spin_unlock(&drvdata->spinlock);
 875
 876         return size;
 877 }
 878 static DEVICE_ATTR_RW(addr_start);
 879
 880 static ssize_t addr_stop_show(struct device *dev,
 881                               struct device_attribute *attr, char *buf)
 882 {
 883         u8 idx;
 884         unsigned long val;
 885         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 886
 887         spin_lock(&drvdata->spinlock);
 888         idx = drvdata->addr_idx;
 889         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 890               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 891                 spin_unlock(&drvdata->spinlock);
 892                 return -EPERM;
 893         }
 894
 895         val = drvdata->addr_val[idx];
 896         spin_unlock(&drvdata->spinlock);
 897
 898         return sprintf(buf, "%#lx\n", val);
 899 }
 900
 901 static ssize_t addr_stop_store(struct device *dev,
 902                                struct device_attribute *attr,
 903                                const char *buf, size_t size)
 904 {
 905         u8 idx;
 906         int ret;
 907         unsigned long val;
 908         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 909
 910         ret = kstrtoul(buf, 16, &val);
 911         if (ret)
 912                 return ret;
 913
 914         spin_lock(&drvdata->spinlock);
 915         idx = drvdata->addr_idx;
 916         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 917               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 918                 spin_unlock(&drvdata->spinlock);
 919                 return -EPERM;
 920         }
 921
 922         drvdata->addr_val[idx] = val;
 923         drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP;
 924         drvdata->startstop_ctrl |= (1 << (idx + 16));
 925         drvdata->enable_ctrl1 |= ETMTECR1_START_STOP;
 926         spin_unlock(&drvdata->spinlock);
 927
 928         return size;
 929 }
 930 static DEVICE_ATTR_RW(addr_stop);
 931
 932 static ssize_t addr_acctype_show(struct device *dev,
 933                                  struct device_attribute *attr, char *buf)
 934 {
 935         unsigned long val;
 936         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 937
 938         spin_lock(&drvdata->spinlock);
 939         val = drvdata->addr_acctype[drvdata->addr_idx];
 940         spin_unlock(&drvdata->spinlock);
 941
 942         return sprintf(buf, "%#lx\n", val);
 943 }
 944
 945 static ssize_t addr_acctype_store(struct device *dev,
 946                                   struct device_attribute *attr,
 947                                   const char *buf, size_t size)
 948 {
 949         int ret;
 950         unsigned long val;
 951         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 952
 953         ret = kstrtoul(buf, 16, &val);
 954         if (ret)
 955                 return ret;
 956
 957         spin_lock(&drvdata->spinlock);
 958         drvdata->addr_acctype[drvdata->addr_idx] = val;
 959         spin_unlock(&drvdata->spinlock);
 960
 961         return size;
 962 }
 963 static DEVICE_ATTR_RW(addr_acctype);
 964
 965 static ssize_t cntr_idx_show(struct device *dev,
 966                              struct device_attribute *attr, char *buf)
 967 {
 968         unsigned long val;
 969         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 970
 971         val = drvdata->cntr_idx;
 972         return sprintf(buf, "%#lx\n", val);
 973 }
 974
 975 static ssize_t cntr_idx_store(struct device *dev,
 976                               struct device_attribute *attr,
 977                               const char *buf, size_t size)
 978 {
 979         int ret;
 980         unsigned long val;
 981         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 982
 983         ret = kstrtoul(buf, 16, &val);
 984         if (ret)
 985                 return ret;
 986
 987         if (val >= drvdata->nr_cntr)
 988                 return -EINVAL;
 989         /*
 990          * Use spinlock to ensure index doesn't change while it gets
 991          * dereferenced multiple times within a spinlock block elsewhere.
 992          */
 993         spin_lock(&drvdata->spinlock);
 994         drvdata->cntr_idx = val;
 995         spin_unlock(&drvdata->spinlock);
 996
 997         return size;
 998 }
 999 static DEVICE_ATTR_RW(cntr_idx);
1000
1001 static ssize_t cntr_rld_val_show(struct device *dev,
1002                                  struct device_attribute *attr, char *buf)
1003 {
1004         unsigned long val;
1005         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1006
1007         spin_lock(&drvdata->spinlock);
1008         val = drvdata->cntr_rld_val[drvdata->cntr_idx];
1009         spin_unlock(&drvdata->spinlock);
1010
1011         return sprintf(buf, "%#lx\n", val);
1012 }
1013
1014 static ssize_t cntr_rld_val_store(struct device *dev,
1015                                   struct device_attribute *attr,
1016                                   const char *buf, size_t size)
1017 {
1018         int ret;
1019         unsigned long val;
1020         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1021
1022         ret = kstrtoul(buf, 16, &val);
1023         if (ret)
1024                 return ret;
1025
1026         spin_lock(&drvdata->spinlock);
1027         drvdata->cntr_rld_val[drvdata->cntr_idx] = val;
1028         spin_unlock(&drvdata->spinlock);
1029
1030         return size;
1031 }
1032 static DEVICE_ATTR_RW(cntr_rld_val);
1033
1034 static ssize_t cntr_event_show(struct device *dev,
1035                                struct device_attribute *attr, char *buf)
1036 {
1037         unsigned long val;
1038         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1039
1040         spin_lock(&drvdata->spinlock);
1041         val = drvdata->cntr_event[drvdata->cntr_idx];
1042         spin_unlock(&drvdata->spinlock);
1043
1044         return sprintf(buf, "%#lx\n", val);
1045 }
1046
1047 static ssize_t cntr_event_store(struct device *dev,
1048                                 struct device_attribute *attr,
1049                                 const char *buf, size_t size)
1050 {
1051         int ret;
1052         unsigned long val;
1053         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1054
1055         ret = kstrtoul(buf, 16, &val);
1056         if (ret)
1057                 return ret;
1058
1059         spin_lock(&drvdata->spinlock);
1060         drvdata->cntr_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1061         spin_unlock(&drvdata->spinlock);
1062
1063         return size;
1064 }
1065 static DEVICE_ATTR_RW(cntr_event);
1066
1067 static ssize_t cntr_rld_event_show(struct device *dev,
1068                                    struct device_attribute *attr, char *buf)
1069 {
1070         unsigned long val;
1071         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1072
1073         spin_lock(&drvdata->spinlock);
1074         val = drvdata->cntr_rld_event[drvdata->cntr_idx];
1075         spin_unlock(&drvdata->spinlock);
1076
1077         return sprintf(buf, "%#lx\n", val);
1078 }
1079
1080 static ssize_t cntr_rld_event_store(struct device *dev,
1081                                     struct device_attribute *attr,
1082                                     const char *buf, size_t size)
1083 {
1084         int ret;
1085         unsigned long val;
1086         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1087
1088         ret = kstrtoul(buf, 16, &val);
1089         if (ret)
1090                 return ret;
1091
1092         spin_lock(&drvdata->spinlock);
1093         drvdata->cntr_rld_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1094         spin_unlock(&drvdata->spinlock);
1095
1096         return size;
1097 }
1098 static DEVICE_ATTR_RW(cntr_rld_event);
1099
1100 static ssize_t cntr_val_show(struct device *dev,
1101                              struct device_attribute *attr, char *buf)
1102 {
1103         int i, ret = 0;
1104         u32 val;
1105         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1106
1107         if (!drvdata->enable) {
1108                 spin_lock(&drvdata->spinlock);
1109                 for (i = 0; i < drvdata->nr_cntr; i++)
1110                         ret += sprintf(buf, "counter %d: %x\n",
1111                                        i, drvdata->cntr_val[i]);
1112                 spin_unlock(&drvdata->spinlock);
1113                 return ret;
1114         }
1115
1116         for (i = 0; i < drvdata->nr_cntr; i++) {
1117                 val = etm_readl(drvdata, ETMCNTVRn(i));
1118                 ret += sprintf(buf, "counter %d: %x\n", i, val);
1119         }
1120
1121         return ret;
1122 }
1123
1124 static ssize_t cntr_val_store(struct device *dev,
1125                               struct device_attribute *attr,
1126                               const char *buf, size_t size)
1127 {
1128         int ret;
1129         unsigned long val;
1130         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1131
1132         ret = kstrtoul(buf, 16, &val);
1133         if (ret)
1134                 return ret;
1135
1136         spin_lock(&drvdata->spinlock);
1137         drvdata->cntr_val[drvdata->cntr_idx] = val;
1138         spin_unlock(&drvdata->spinlock);
1139
1140         return size;
1141 }
1142 static DEVICE_ATTR_RW(cntr_val);
1143
1144 static ssize_t seq_12_event_show(struct device *dev,
1145                                  struct device_attribute *attr, char *buf)
1146 {
1147         unsigned long val;
1148         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1149
1150         val = drvdata->seq_12_event;
1151         return sprintf(buf, "%#lx\n", val);
1152 }
1153
1154 static ssize_t seq_12_event_store(struct device *dev,
1155                                   struct device_attribute *attr,
1156                                   const char *buf, size_t size)
1157 {
1158         int ret;
1159         unsigned long val;
1160         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1161
1162         ret = kstrtoul(buf, 16, &val);
1163         if (ret)
1164                 return ret;
1165
1166         drvdata->seq_12_event = val & ETM_EVENT_MASK;
1167         return size;
1168 }
1169 static DEVICE_ATTR_RW(seq_12_event);
1170
1171 static ssize_t seq_21_event_show(struct device *dev,
1172                                  struct device_attribute *attr, char *buf)
1173 {
1174         unsigned long val;
1175         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1176
1177         val = drvdata->seq_21_event;
1178         return sprintf(buf, "%#lx\n", val);
1179 }
1180
1181 static ssize_t seq_21_event_store(struct device *dev,
1182                                   struct device_attribute *attr,
1183                                   const char *buf, size_t size)
1184 {
1185         int ret;
1186         unsigned long val;
1187         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1188
1189         ret = kstrtoul(buf, 16, &val);
1190         if (ret)
1191                 return ret;
1192
1193         drvdata->seq_21_event = val & ETM_EVENT_MASK;
1194         return size;
1195 }
1196 static DEVICE_ATTR_RW(seq_21_event);
1197
1198 static ssize_t seq_23_event_show(struct device *dev,
1199                                  struct device_attribute *attr, char *buf)
1200 {
1201         unsigned long val;
1202         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1203
1204         val = drvdata->seq_23_event;
1205         return sprintf(buf, "%#lx\n", val);
1206 }
1207
1208 static ssize_t seq_23_event_store(struct device *dev,
1209                                   struct device_attribute *attr,
1210                                   const char *buf, size_t size)
1211 {
1212         int ret;
1213         unsigned long val;
1214         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1215
1216         ret = kstrtoul(buf, 16, &val);
1217         if (ret)
1218                 return ret;
1219
1220         drvdata->seq_23_event = val & ETM_EVENT_MASK;
1221         return size;
1222 }
1223 static DEVICE_ATTR_RW(seq_23_event);
1224
1225 static ssize_t seq_31_event_show(struct device *dev,
1226                                  struct device_attribute *attr, char *buf)
1227 {
1228         unsigned long val;
1229         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1230
1231         val = drvdata->seq_31_event;
1232         return sprintf(buf, "%#lx\n", val);
1233 }
1234
1235 static ssize_t seq_31_event_store(struct device *dev,
1236                                   struct device_attribute *attr,
1237                                   const char *buf, size_t size)
1238 {
1239         int ret;
1240         unsigned long val;
1241         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1242
1243         ret = kstrtoul(buf, 16, &val);
1244         if (ret)
1245                 return ret;
1246
1247         drvdata->seq_31_event = val & ETM_EVENT_MASK;
1248         return size;
1249 }
1250 static DEVICE_ATTR_RW(seq_31_event);
1251
1252 static ssize_t seq_32_event_show(struct device *dev,
1253                                  struct device_attribute *attr, char *buf)
1254 {
1255         unsigned long val;
1256         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1257
1258         val = drvdata->seq_32_event;
1259         return sprintf(buf, "%#lx\n", val);
1260 }
1261
1262 static ssize_t seq_32_event_store(struct device *dev,
1263                                   struct device_attribute *attr,
1264                                   const char *buf, size_t size)
1265 {
1266         int ret;
1267         unsigned long val;
1268         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1269
1270         ret = kstrtoul(buf, 16, &val);
1271         if (ret)
1272                 return ret;
1273
1274         drvdata->seq_32_event = val & ETM_EVENT_MASK;
1275         return size;
1276 }
1277 static DEVICE_ATTR_RW(seq_32_event);
1278
1279 static ssize_t seq_13_event_show(struct device *dev,
1280                                  struct device_attribute *attr, char *buf)
1281 {
1282         unsigned long val;
1283         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1284
1285         val = drvdata->seq_13_event;
1286         return sprintf(buf, "%#lx\n", val);
1287 }
1288
1289 static ssize_t seq_13_event_store(struct device *dev,
1290                                   struct device_attribute *attr,
1291                                   const char *buf, size_t size)
1292 {
1293         int ret;
1294         unsigned long val;
1295         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1296
1297         ret = kstrtoul(buf, 16, &val);
1298         if (ret)
1299                 return ret;
1300
1301         drvdata->seq_13_event = val & ETM_EVENT_MASK;
1302         return size;
1303 }
1304 static DEVICE_ATTR_RW(seq_13_event);
1305
1306 static ssize_t seq_curr_state_show(struct device *dev,
1307                                    struct device_attribute *attr, char *buf)
1308 {
1309         unsigned long val, flags;
1310         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1311
1312         if (!drvdata->enable) {
1313                 val = drvdata->seq_curr_state;
1314                 goto out;
1315         }
1316
1317         pm_runtime_get_sync(drvdata->dev);
1318
1319         spin_lock_irqsave(&drvdata->spinlock, flags);
1320
1321         CS_UNLOCK(drvdata->base);
1322         val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
1323         CS_LOCK(drvdata->base);
1324
1325         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1326         pm_runtime_put(drvdata->dev);
1327 out:
1328         return sprintf(buf, "%#lx\n", val);
1329 }
1330
1331 static ssize_t seq_curr_state_store(struct device *dev,
1332                                     struct device_attribute *attr,
1333                                     const char *buf, size_t size)
1334 {
1335         int ret;
1336         unsigned long val;
1337         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1338
1339         ret = kstrtoul(buf, 16, &val);
1340         if (ret)
1341                 return ret;
1342
1343         if (val > ETM_SEQ_STATE_MAX_VAL)
1344                 return -EINVAL;
1345
1346         drvdata->seq_curr_state = val;
1347
1348         return size;
1349 }
1350 static DEVICE_ATTR_RW(seq_curr_state);
1351
1352 static ssize_t ctxid_idx_show(struct device *dev,
1353                               struct device_attribute *attr, char *buf)
1354 {
1355         unsigned long val;
1356         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1357
1358         val = drvdata->ctxid_idx;
1359         return sprintf(buf, "%#lx\n", val);
1360 }
1361
1362 static ssize_t ctxid_idx_store(struct device *dev,
1363                                 struct device_attribute *attr,
1364                                 const char *buf, size_t size)
1365 {
1366         int ret;
1367         unsigned long val;
1368         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1369
1370         ret = kstrtoul(buf, 16, &val);
1371         if (ret)
1372                 return ret;
1373
1374         if (val >= drvdata->nr_ctxid_cmp)
1375                 return -EINVAL;
1376
1377         /*
1378          * Use spinlock to ensure index doesn't change while it gets
1379          * dereferenced multiple times within a spinlock block elsewhere.
1380          */
1381         spin_lock(&drvdata->spinlock);
1382         drvdata->ctxid_idx = val;
1383         spin_unlock(&drvdata->spinlock);
1384
1385         return size;
1386 }
1387 static DEVICE_ATTR_RW(ctxid_idx);
1388
1389 static ssize_t ctxid_val_show(struct device *dev,
1390                               struct device_attribute *attr, char *buf)
1391 {
1392         unsigned long val;
1393         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1394
1395         spin_lock(&drvdata->spinlock);
1396         val = drvdata->ctxid_val[drvdata->ctxid_idx];
1397         spin_unlock(&drvdata->spinlock);
1398
1399         return sprintf(buf, "%#lx\n", val);
1400 }
1401
1402 static ssize_t ctxid_val_store(struct device *dev,
1403                                struct device_attribute *attr,
1404                                const char *buf, size_t size)
1405 {
1406         int ret;
1407         unsigned long val;
1408         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1409
1410         ret = kstrtoul(buf, 16, &val);
1411         if (ret)
1412                 return ret;
1413
1414         spin_lock(&drvdata->spinlock);
1415         drvdata->ctxid_val[drvdata->ctxid_idx] = val;
1416         spin_unlock(&drvdata->spinlock);
1417
1418         return size;
1419 }
1420 static DEVICE_ATTR_RW(ctxid_val);
1421
1422 static ssize_t ctxid_mask_show(struct device *dev,
1423                                struct device_attribute *attr, char *buf)
1424 {
1425         unsigned long val;
1426         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1427
1428         val = drvdata->ctxid_mask;
1429         return sprintf(buf, "%#lx\n", val);
1430 }
1431
1432 static ssize_t ctxid_mask_store(struct device *dev,
1433                                 struct device_attribute *attr,
1434                                 const char *buf, size_t size)
1435 {
1436         int ret;
1437         unsigned long val;
1438         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1439
1440         ret = kstrtoul(buf, 16, &val);
1441         if (ret)
1442                 return ret;
1443
1444         drvdata->ctxid_mask = val;
1445         return size;
1446 }
1447 static DEVICE_ATTR_RW(ctxid_mask);
1448
1449 static ssize_t sync_freq_show(struct device *dev,
1450                               struct device_attribute *attr, char *buf)
1451 {
1452         unsigned long val;
1453         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1454
1455         val = drvdata->sync_freq;
1456         return sprintf(buf, "%#lx\n", val);
1457 }
1458
1459 static ssize_t sync_freq_store(struct device *dev,
1460                                struct device_attribute *attr,
1461                                const char *buf, size_t size)
1462 {
1463         int ret;
1464         unsigned long val;
1465         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1466
1467         ret = kstrtoul(buf, 16, &val);
1468         if (ret)
1469                 return ret;
1470
1471         drvdata->sync_freq = val & ETM_SYNC_MASK;
1472         return size;
1473 }
1474 static DEVICE_ATTR_RW(sync_freq);
1475
1476 static ssize_t timestamp_event_show(struct device *dev,
1477                                     struct device_attribute *attr, char *buf)
1478 {
1479         unsigned long val;
1480         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1481
1482         val = drvdata->timestamp_event;
1483         return sprintf(buf, "%#lx\n", val);
1484 }
1485
1486 static ssize_t timestamp_event_store(struct device *dev,
1487                                      struct device_attribute *attr,
1488                                      const char *buf, size_t size)
1489 {
1490         int ret;
1491         unsigned long val;
1492         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1493
1494         ret = kstrtoul(buf, 16, &val);
1495         if (ret)
1496                 return ret;
1497
1498         drvdata->timestamp_event = val & ETM_EVENT_MASK;
1499         return size;
1500 }
1501 static DEVICE_ATTR_RW(timestamp_event);
1502
1503 static ssize_t status_show(struct device *dev,
1504                            struct device_attribute *attr, char *buf)
1505 {
1506         int ret;
1507         unsigned long flags;
1508         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1509
1510         pm_runtime_get_sync(drvdata->dev);
1511         spin_lock_irqsave(&drvdata->spinlock, flags);
1512
1513         CS_UNLOCK(drvdata->base);
1514         ret = sprintf(buf,
1515                       "ETMCCR: 0x%08x\n"
1516                       "ETMCCER: 0x%08x\n"
1517                       "ETMSCR: 0x%08x\n"
1518                       "ETMIDR: 0x%08x\n"
1519                       "ETMCR: 0x%08x\n"
1520                       "ETMTRACEIDR: 0x%08x\n"
1521                       "Enable event: 0x%08x\n"
1522                       "Enable start/stop: 0x%08x\n"
1523                       "Enable control: CR1 0x%08x CR2 0x%08x\n"
1524                       "CPU affinity: %d\n",
1525                       drvdata->etmccr, drvdata->etmccer,
1526                       etm_readl(drvdata, ETMSCR), etm_readl(drvdata, ETMIDR),
1527                       etm_readl(drvdata, ETMCR), etm_trace_id_simple(drvdata),
1528                       etm_readl(drvdata, ETMTEEVR),
1529                       etm_readl(drvdata, ETMTSSCR),
1530                       etm_readl(drvdata, ETMTECR1),
1531                       etm_readl(drvdata, ETMTECR2),
1532                       drvdata->cpu);
1533         CS_LOCK(drvdata->base);
1534
1535         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1536         pm_runtime_put(drvdata->dev);
1537
1538         return ret;
1539 }
1540 static DEVICE_ATTR_RO(status);
1541
1542 static ssize_t traceid_show(struct device *dev,
1543                             struct device_attribute *attr, char *buf)
1544 {
1545         unsigned long val, flags;
1546         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1547
1548         if (!drvdata->enable) {
1549                 val = drvdata->traceid;
1550                 goto out;
1551         }
1552
1553         pm_runtime_get_sync(drvdata->dev);
1554         spin_lock_irqsave(&drvdata->spinlock, flags);
1555         CS_UNLOCK(drvdata->base);
1556
1557         val = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
1558
1559         CS_LOCK(drvdata->base);
1560         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1561         pm_runtime_put(drvdata->dev);
1562 out:
1563         return sprintf(buf, "%#lx\n", val);
1564 }
1565
1566 static ssize_t traceid_store(struct device *dev,
1567                              struct device_attribute *attr,
1568                              const char *buf, size_t size)
1569 {
1570         int ret;
1571         unsigned long val;
1572         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1573
1574         ret = kstrtoul(buf, 16, &val);
1575         if (ret)
1576                 return ret;
1577
1578         drvdata->traceid = val & ETM_TRACEID_MASK;
1579         return size;
1580 }
1581 static DEVICE_ATTR_RW(traceid);
1582
1583 static struct attribute *coresight_etm_attrs[] = {
1584         &dev_attr_nr_addr_cmp.attr,
1585         &dev_attr_nr_cntr.attr,
1586         &dev_attr_nr_ctxid_cmp.attr,
1587         &dev_attr_etmsr.attr,
1588         &dev_attr_reset.attr,
1589         &dev_attr_mode.attr,
1590         &dev_attr_trigger_event.attr,
1591         &dev_attr_enable_event.attr,
1592         &dev_attr_fifofull_level.attr,
1593         &dev_attr_addr_idx.attr,
1594         &dev_attr_addr_single.attr,
1595         &dev_attr_addr_range.attr,
1596         &dev_attr_addr_start.attr,
1597         &dev_attr_addr_stop.attr,
1598         &dev_attr_addr_acctype.attr,
1599         &dev_attr_cntr_idx.attr,
1600         &dev_attr_cntr_rld_val.attr,
1601         &dev_attr_cntr_event.attr,
1602         &dev_attr_cntr_rld_event.attr,
1603         &dev_attr_cntr_val.attr,
1604         &dev_attr_seq_12_event.attr,
1605         &dev_attr_seq_21_event.attr,
1606         &dev_attr_seq_23_event.attr,
1607         &dev_attr_seq_31_event.attr,
1608         &dev_attr_seq_32_event.attr,
1609         &dev_attr_seq_13_event.attr,
1610         &dev_attr_seq_curr_state.attr,
1611         &dev_attr_ctxid_idx.attr,
1612         &dev_attr_ctxid_val.attr,
1613         &dev_attr_ctxid_mask.attr,
1614         &dev_attr_sync_freq.attr,
1615         &dev_attr_timestamp_event.attr,
1616         &dev_attr_status.attr,
1617         &dev_attr_traceid.attr,
1618         NULL,
1619 };
1620 ATTRIBUTE_GROUPS(coresight_etm);
1621
1622 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
1623                             void *hcpu)
1624 {
1625         unsigned int cpu = (unsigned long)hcpu;
1626
1627         if (!etmdrvdata[cpu])
1628                 goto out;
1629
1630         switch (action & (~CPU_TASKS_FROZEN)) {
1631         case CPU_STARTING:
1632                 spin_lock(&etmdrvdata[cpu]->spinlock);
1633                 if (!etmdrvdata[cpu]->os_unlock) {
1634                         etm_os_unlock(etmdrvdata[cpu]);
1635                         etmdrvdata[cpu]->os_unlock = true;
1636                 }
1637
1638                 if (etmdrvdata[cpu]->enable)
1639                         etm_enable_hw(etmdrvdata[cpu]);
1640                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1641                 break;
1642
1643         case CPU_ONLINE:
1644                 if (etmdrvdata[cpu]->boot_enable &&
1645                     !etmdrvdata[cpu]->sticky_enable)
1646                         coresight_enable(etmdrvdata[cpu]->csdev);
1647                 break;
1648
1649         case CPU_DYING:
1650                 spin_lock(&etmdrvdata[cpu]->spinlock);
1651                 if (etmdrvdata[cpu]->enable)
1652                         etm_disable_hw(etmdrvdata[cpu]);
1653                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1654                 break;
1655         }
1656 out:
1657         return NOTIFY_OK;
1658 }
1659
1660 static struct notifier_block etm_cpu_notifier = {
1661         .notifier_call = etm_cpu_callback,
1662 };
1663
1664 static bool etm_arch_supported(u8 arch)
1665 {
1666         switch (arch) {
1667         case ETM_ARCH_V3_3:
1668                 break;
1669         case ETM_ARCH_V3_5:
1670                 break;
1671         case PFT_ARCH_V1_0:
1672                 break;
1673         case PFT_ARCH_V1_1:
1674                 break;
1675         default:
1676                 return false;
1677         }
1678         return true;
1679 }
1680
1681 static void etm_init_arch_data(void *info)
1682 {
1683         u32 etmidr;
1684         u32 etmccr;
1685         struct etm_drvdata *drvdata = info;
1686
1687         CS_UNLOCK(drvdata->base);
1688
1689         /* First dummy read */
1690         (void)etm_readl(drvdata, ETMPDSR);
1691         /* Provide power to ETM: ETMPDCR[3] == 1 */
1692         etm_set_pwrup(drvdata);
1693         /*
1694          * Clear power down bit since when this bit is set writes to
1695          * certain registers might be ignored.
1696          */
1697         etm_clr_pwrdwn(drvdata);
1698         /*
1699          * Set prog bit. It will be set from reset but this is included to
1700          * ensure it is set
1701          */
1702         etm_set_prog(drvdata);
1703
1704         /* Find all capabilities */
1705         etmidr = etm_readl(drvdata, ETMIDR);
1706         drvdata->arch = BMVAL(etmidr, 4, 11);
1707         drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
1708
1709         drvdata->etmccer = etm_readl(drvdata, ETMCCER);
1710         etmccr = etm_readl(drvdata, ETMCCR);
1711         drvdata->etmccr = etmccr;
1712         drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
1713         drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
1714         drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
1715         drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
1716         drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
1717
1718         etm_set_pwrdwn(drvdata);
1719         etm_clr_pwrup(drvdata);
1720         CS_LOCK(drvdata->base);
1721 }
1722
1723 static void etm_init_default_data(struct etm_drvdata *drvdata)
1724 {
1725         /*
1726          * A trace ID of value 0 is invalid, so let's start at some
1727          * random value that fits in 7 bits and will be just as good.
1728          */
1729         static int etm3x_traceid = 0x10;
1730
1731         u32 flags = (1 << 0 | /* instruction execute*/
1732                      3 << 3 | /* ARM instruction */
1733                      0 << 5 | /* No data value comparison */
1734                      0 << 7 | /* No exact mach */
1735                      0 << 8 | /* Ignore context ID */
1736                      0 << 10); /* Security ignored */
1737
1738         /*
1739          * Initial configuration only - guarantees sources handled by
1740          * this driver have a unique ID at startup time but not between
1741          * all other types of sources.  For that we lean on the core
1742          * framework.
1743          */
1744         drvdata->traceid = etm3x_traceid++;
1745         drvdata->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
1746         drvdata->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
1747         if (drvdata->nr_addr_cmp >= 2) {
1748                 drvdata->addr_val[0] = (u32) _stext;
1749                 drvdata->addr_val[1] = (u32) _etext;
1750                 drvdata->addr_acctype[0] = flags;
1751                 drvdata->addr_acctype[1] = flags;
1752                 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
1753                 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
1754         }
1755
1756         etm_set_default(drvdata);
1757 }
1758
1759 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
1760 {
1761         int ret;
1762         void __iomem *base;
1763         struct device *dev = &adev->dev;
1764         struct coresight_platform_data *pdata = NULL;
1765         struct etm_drvdata *drvdata;
1766         struct resource *res = &adev->res;
1767         struct coresight_desc *desc;
1768         struct device_node *np = adev->dev.of_node;
1769
1770         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1771         if (!desc)
1772                 return -ENOMEM;
1773
1774         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1775         if (!drvdata)
1776                 return -ENOMEM;
1777
1778         if (np) {
1779                 pdata = of_get_coresight_platform_data(dev, np);
1780                 if (IS_ERR(pdata))
1781                         return PTR_ERR(pdata);
1782
1783                 adev->dev.platform_data = pdata;
1784                 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
1785         }
1786
1787         drvdata->dev = &adev->dev;
1788         dev_set_drvdata(dev, drvdata);
1789
1790         /* Validity for the resource is already checked by the AMBA core */
1791         base = devm_ioremap_resource(dev, res);
1792         if (IS_ERR(base))
1793                 return PTR_ERR(base);
1794
1795         drvdata->base = base;
1796
1797         spin_lock_init(&drvdata->spinlock);
1798
1799         drvdata->cpu = pdata ? pdata->cpu : 0;
1800
1801         get_online_cpus();
1802         etmdrvdata[drvdata->cpu] = drvdata;
1803
1804         if (!smp_call_function_single(drvdata->cpu, etm_os_unlock, drvdata, 1))
1805                 drvdata->os_unlock = true;
1806
1807         if (smp_call_function_single(drvdata->cpu,
1808                                      etm_init_arch_data,  drvdata, 1))
1809                 dev_err(dev, "ETM arch init failed\n");
1810
1811         if (!etm_count++)
1812                 register_hotcpu_notifier(&etm_cpu_notifier);
1813
1814         put_online_cpus();
1815
1816         if (etm_arch_supported(drvdata->arch) == false) {
1817                 ret = -EINVAL;
1818                 goto err_arch_supported;
1819         }
1820         etm_init_default_data(drvdata);
1821
1822         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
1823         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1824         desc->ops = &etm_cs_ops;
1825         desc->pdata = pdata;
1826         desc->dev = dev;
1827         desc->groups = coresight_etm_groups;
1828         drvdata->csdev = coresight_register(desc);
1829         if (IS_ERR(drvdata->csdev)) {
1830                 ret = PTR_ERR(drvdata->csdev);
1831                 goto err_arch_supported;
1832         }
1833
1834         pm_runtime_put(&adev->dev);
1835         dev_info(dev, "%s initialized\n", (char *)id->data);
1836
1837         if (boot_enable) {
1838                 coresight_enable(drvdata->csdev);
1839                 drvdata->boot_enable = true;
1840         }
1841
1842         return 0;
1843
1844 err_arch_supported:
1845         if (--etm_count == 0)
1846                 unregister_hotcpu_notifier(&etm_cpu_notifier);
1847         return ret;
1848 }
1849
1850 static int etm_remove(struct amba_device *adev)
1851 {
1852         struct etm_drvdata *drvdata = amba_get_drvdata(adev);
1853
1854         coresight_unregister(drvdata->csdev);
1855         if (--etm_count == 0)
1856                 unregister_hotcpu_notifier(&etm_cpu_notifier);
1857
1858         return 0;
1859 }
1860
1861 static struct amba_id etm_ids[] = {
1862         {       /* ETM 3.3 */
1863                 .id     = 0x0003b921,
1864                 .mask   = 0x0003ffff,
1865                 .data   = "ETM 3.3",
1866         },
1867         {       /* ETM 3.5 */
1868                 .id     = 0x0003b956,
1869                 .mask   = 0x0003ffff,
1870                 .data   = "ETM 3.5",
1871         },
1872         {       /* PTM 1.0 */
1873                 .id     = 0x0003b950,
1874                 .mask   = 0x0003ffff,
1875                 .data   = "PTM 1.0",
1876         },
1877         {       /* PTM 1.1 */
1878                 .id     = 0x0003b95f,
1879                 .mask   = 0x0003ffff,
1880                 .data   = "PTM 1.1",
1881         },
1882         { 0, 0},
1883 };
1884
1885 static struct amba_driver etm_driver = {
1886         .drv = {
1887                 .name   = "coresight-etm3x",
1888                 .owner  = THIS_MODULE,
1889         },
1890         .probe          = etm_probe,
1891         .remove         = etm_remove,
1892         .id_table       = etm_ids,
1893 };
1894
1895 module_amba_driver(etm_driver);
1896
1897 MODULE_LICENSE("GPL v2");
1898 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");