2 * Blackfin On-Chip Two Wire Interface Driver
4 * Copyright 2005-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
18 #include <linux/timer.h>
19 #include <linux/spinlock.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
25 #include <asm/blackfin.h>
26 #include <asm/portmux.h>
28 #include <asm/bfin_twi.h>
31 #define TWI_I2C_MODE_STANDARD 1
32 #define TWI_I2C_MODE_STANDARDSUB 2
33 #define TWI_I2C_MODE_COMBINED 3
34 #define TWI_I2C_MODE_REPEAT 4
36 struct bfin_twi_iface {
47 struct i2c_adapter adap;
48 struct completion complete;
54 void __iomem *regs_base;
58 #define DEFINE_TWI_REG(reg, off) \
59 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
60 { return bfin_read16(iface->regs_base + (off)); } \
61 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
62 { bfin_write16(iface->regs_base + (off), v); }
64 DEFINE_TWI_REG(CLKDIV, 0x00)
65 DEFINE_TWI_REG(CONTROL, 0x04)
66 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
67 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
68 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
69 DEFINE_TWI_REG(MASTER_CTL, 0x14)
70 DEFINE_TWI_REG(MASTER_STAT, 0x18)
71 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
72 DEFINE_TWI_REG(INT_STAT, 0x20)
73 DEFINE_TWI_REG(INT_MASK, 0x24)
74 DEFINE_TWI_REG(FIFO_CTL, 0x28)
75 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
76 DEFINE_TWI_REG(XMT_DATA8, 0x80)
77 DEFINE_TWI_REG(XMT_DATA16, 0x84)
78 DEFINE_TWI_REG(RCV_DATA8, 0x88)
79 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
81 static const u16 pin_req[2][3] = {
82 {P_TWI0_SCL, P_TWI0_SDA, 0},
83 {P_TWI1_SCL, P_TWI1_SDA, 0},
86 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
87 unsigned short twi_int_status)
89 unsigned short mast_stat = read_MASTER_STAT(iface);
91 if (twi_int_status & XMTSERV) {
92 /* Transmit next data */
93 if (iface->writeNum > 0) {
95 write_XMT_DATA8(iface, *(iface->transPtr++));
98 /* start receive immediately after complete sending in
101 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
102 write_MASTER_CTL(iface,
103 read_MASTER_CTL(iface) | MDIR);
104 else if (iface->manual_stop)
105 write_MASTER_CTL(iface,
106 read_MASTER_CTL(iface) | STOP);
107 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
108 iface->cur_msg + 1 < iface->msg_num) {
109 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
110 write_MASTER_CTL(iface,
111 read_MASTER_CTL(iface) | MDIR);
113 write_MASTER_CTL(iface,
114 read_MASTER_CTL(iface) & ~MDIR);
117 if (twi_int_status & RCVSERV) {
118 if (iface->readNum > 0) {
119 /* Receive next data */
120 *(iface->transPtr) = read_RCV_DATA8(iface);
121 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
122 /* Change combine mode into sub mode after
125 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
126 /* Get read number from first byte in block
129 if (iface->readNum == 1 && iface->manual_stop)
130 iface->readNum = *iface->transPtr + 1;
136 if (iface->readNum == 0) {
137 if (iface->manual_stop) {
138 /* Temporary workaround to avoid possible bus stall -
139 * Flush FIFO before issuing the STOP condition
141 read_RCV_DATA16(iface);
142 write_MASTER_CTL(iface,
143 read_MASTER_CTL(iface) | STOP);
144 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
145 iface->cur_msg + 1 < iface->msg_num) {
146 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
147 write_MASTER_CTL(iface,
148 read_MASTER_CTL(iface) | MDIR);
150 write_MASTER_CTL(iface,
151 read_MASTER_CTL(iface) & ~MDIR);
155 if (twi_int_status & MERR) {
156 write_INT_MASK(iface, 0);
157 write_MASTER_STAT(iface, 0x3e);
158 write_MASTER_CTL(iface, 0);
159 iface->result = -EIO;
161 if (mast_stat & LOSTARB)
162 dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
163 if (mast_stat & ANAK)
164 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
165 if (mast_stat & DNAK)
166 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
167 if (mast_stat & BUFRDERR)
168 dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
169 if (mast_stat & BUFWRERR)
170 dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
172 /* Faulty slave devices, may drive SDA low after a transfer
173 * finishes. To release the bus this code generates up to 9
174 * extra clocks until SDA is released.
177 if (read_MASTER_STAT(iface) & SDASEN) {
180 write_MASTER_CTL(iface, SCLOVR);
182 write_MASTER_CTL(iface, 0);
184 } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
186 write_MASTER_CTL(iface, SDAOVR | SCLOVR);
188 write_MASTER_CTL(iface, SDAOVR);
190 write_MASTER_CTL(iface, 0);
193 /* If it is a quick transfer, only address without data,
194 * not an err, return 1.
196 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
197 iface->transPtr == NULL &&
198 (twi_int_status & MCOMP) && (mast_stat & DNAK))
201 complete(&iface->complete);
204 if (twi_int_status & MCOMP) {
205 if (twi_int_status & (XMTSERV | RCVSERV) &&
206 (read_MASTER_CTL(iface) & MEN) == 0 &&
207 (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
208 iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
210 write_INT_MASK(iface, 0);
211 write_MASTER_CTL(iface, 0);
212 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
213 if (iface->readNum == 0) {
214 /* set the read number to 1 and ask for manual
215 * stop in block combine mode
218 iface->manual_stop = 1;
219 write_MASTER_CTL(iface,
220 read_MASTER_CTL(iface) | (0xff << 6));
222 /* set the readd number in other
225 write_MASTER_CTL(iface,
226 (read_MASTER_CTL(iface) &
228 (iface->readNum << 6));
230 /* remove restart bit and enable master receive */
231 write_MASTER_CTL(iface,
232 read_MASTER_CTL(iface) & ~RSTART);
233 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
234 iface->cur_msg + 1 < iface->msg_num) {
236 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
237 iface->writeNum = iface->readNum =
238 iface->pmsg[iface->cur_msg].len;
239 /* Set Transmit device address */
240 write_MASTER_ADDR(iface,
241 iface->pmsg[iface->cur_msg].addr);
242 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
243 iface->read_write = I2C_SMBUS_READ;
245 iface->read_write = I2C_SMBUS_WRITE;
246 /* Transmit first data */
247 if (iface->writeNum > 0) {
248 write_XMT_DATA8(iface,
249 *(iface->transPtr++));
254 if (iface->pmsg[iface->cur_msg].len <= 255) {
255 write_MASTER_CTL(iface,
256 (read_MASTER_CTL(iface) &
258 (iface->pmsg[iface->cur_msg].len << 6));
259 iface->manual_stop = 0;
261 write_MASTER_CTL(iface,
262 (read_MASTER_CTL(iface) |
264 iface->manual_stop = 1;
266 /* remove restart bit before last message */
267 if (iface->cur_msg + 1 == iface->msg_num)
268 write_MASTER_CTL(iface,
269 read_MASTER_CTL(iface) & ~RSTART);
272 write_INT_MASK(iface, 0);
273 write_MASTER_CTL(iface, 0);
275 complete(&iface->complete);
279 /* Interrupt handler */
280 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
282 struct bfin_twi_iface *iface = dev_id;
284 unsigned short twi_int_status;
286 spin_lock_irqsave(&iface->lock, flags);
288 twi_int_status = read_INT_STAT(iface);
291 /* Clear interrupt status */
292 write_INT_STAT(iface, twi_int_status);
293 bfin_twi_handle_interrupt(iface, twi_int_status);
296 spin_unlock_irqrestore(&iface->lock, flags);
301 * One i2c master transfer
303 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
304 struct i2c_msg *msgs, int num)
306 struct bfin_twi_iface *iface = adap->algo_data;
307 struct i2c_msg *pmsg;
310 if (!(read_CONTROL(iface) & TWI_ENA))
313 if (read_MASTER_STAT(iface) & BUSBUSY)
317 iface->msg_num = num;
321 if (pmsg->flags & I2C_M_TEN) {
322 dev_err(&adap->dev, "10 bits addr not supported!\n");
326 if (iface->msg_num > 1)
327 iface->cur_mode = TWI_I2C_MODE_REPEAT;
328 iface->manual_stop = 0;
329 iface->transPtr = pmsg->buf;
330 iface->writeNum = iface->readNum = pmsg->len;
332 init_completion(&(iface->complete));
333 /* Set Transmit device address */
334 write_MASTER_ADDR(iface, pmsg->addr);
336 /* FIFO Initiation. Data in FIFO should be
337 * discarded before start a new operation.
339 write_FIFO_CTL(iface, 0x3);
341 write_FIFO_CTL(iface, 0);
344 if (pmsg->flags & I2C_M_RD)
345 iface->read_write = I2C_SMBUS_READ;
347 iface->read_write = I2C_SMBUS_WRITE;
348 /* Transmit first data */
349 if (iface->writeNum > 0) {
350 write_XMT_DATA8(iface, *(iface->transPtr++));
357 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
359 /* Interrupt mask . Enable XMT, RCV interrupt */
360 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
363 if (pmsg->len <= 255)
364 write_MASTER_CTL(iface, pmsg->len << 6);
366 write_MASTER_CTL(iface, 0xff << 6);
367 iface->manual_stop = 1;
371 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
372 (iface->msg_num > 1 ? RSTART : 0) |
373 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
374 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
377 while (!iface->result) {
378 if (!wait_for_completion_timeout(&iface->complete,
381 dev_err(&adap->dev, "master transfer timeout\n");
385 if (iface->result == 1)
386 rc = iface->cur_msg + 1;
394 * Generic i2c master transfer entrypoint
396 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
397 struct i2c_msg *msgs, int num)
399 return bfin_twi_do_master_xfer(adap, msgs, num);
403 * One I2C SMBus transfer
405 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
406 unsigned short flags, char read_write,
407 u8 command, int size, union i2c_smbus_data *data)
409 struct bfin_twi_iface *iface = adap->algo_data;
412 if (!(read_CONTROL(iface) & TWI_ENA))
415 if (read_MASTER_STAT(iface) & BUSBUSY)
421 /* Prepare datas & select mode */
423 case I2C_SMBUS_QUICK:
424 iface->transPtr = NULL;
425 iface->cur_mode = TWI_I2C_MODE_STANDARD;
429 iface->transPtr = NULL;
431 if (read_write == I2C_SMBUS_READ)
435 iface->transPtr = &data->byte;
437 iface->cur_mode = TWI_I2C_MODE_STANDARD;
439 case I2C_SMBUS_BYTE_DATA:
440 if (read_write == I2C_SMBUS_READ) {
442 iface->cur_mode = TWI_I2C_MODE_COMBINED;
445 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
447 iface->transPtr = &data->byte;
449 case I2C_SMBUS_WORD_DATA:
450 if (read_write == I2C_SMBUS_READ) {
452 iface->cur_mode = TWI_I2C_MODE_COMBINED;
455 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
457 iface->transPtr = (u8 *)&data->word;
459 case I2C_SMBUS_PROC_CALL:
462 iface->cur_mode = TWI_I2C_MODE_COMBINED;
463 iface->transPtr = (u8 *)&data->word;
465 case I2C_SMBUS_BLOCK_DATA:
466 if (read_write == I2C_SMBUS_READ) {
468 iface->cur_mode = TWI_I2C_MODE_COMBINED;
470 iface->writeNum = data->block[0] + 1;
471 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
473 iface->transPtr = data->block;
475 case I2C_SMBUS_I2C_BLOCK_DATA:
476 if (read_write == I2C_SMBUS_READ) {
477 iface->readNum = data->block[0];
478 iface->cur_mode = TWI_I2C_MODE_COMBINED;
480 iface->writeNum = data->block[0];
481 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
483 iface->transPtr = (u8 *)&data->block[1];
490 iface->manual_stop = 0;
491 iface->read_write = read_write;
492 iface->command = command;
493 init_completion(&(iface->complete));
495 /* FIFO Initiation. Data in FIFO should be discarded before
496 * start a new operation.
498 write_FIFO_CTL(iface, 0x3);
500 write_FIFO_CTL(iface, 0);
503 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
505 /* Set Transmit device address */
506 write_MASTER_ADDR(iface, addr);
509 switch (iface->cur_mode) {
510 case TWI_I2C_MODE_STANDARDSUB:
511 write_XMT_DATA8(iface, iface->command);
512 write_INT_MASK(iface, MCOMP | MERR |
513 ((iface->read_write == I2C_SMBUS_READ) ?
517 if (iface->writeNum + 1 <= 255)
518 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
520 write_MASTER_CTL(iface, 0xff << 6);
521 iface->manual_stop = 1;
524 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
525 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
527 case TWI_I2C_MODE_COMBINED:
528 write_XMT_DATA8(iface, iface->command);
529 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
532 if (iface->writeNum > 0)
533 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
535 write_MASTER_CTL(iface, 0x1 << 6);
537 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
538 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
541 write_MASTER_CTL(iface, 0);
542 if (size != I2C_SMBUS_QUICK) {
543 /* Don't access xmit data register when this is a
546 if (iface->read_write != I2C_SMBUS_READ) {
547 if (iface->writeNum > 0) {
548 write_XMT_DATA8(iface,
549 *(iface->transPtr++));
550 if (iface->writeNum <= 255)
551 write_MASTER_CTL(iface,
552 iface->writeNum << 6);
554 write_MASTER_CTL(iface,
556 iface->manual_stop = 1;
560 write_XMT_DATA8(iface, iface->command);
561 write_MASTER_CTL(iface, 1 << 6);
564 if (iface->readNum > 0 && iface->readNum <= 255)
565 write_MASTER_CTL(iface,
566 iface->readNum << 6);
567 else if (iface->readNum > 255) {
568 write_MASTER_CTL(iface, 0xff << 6);
569 iface->manual_stop = 1;
574 write_INT_MASK(iface, MCOMP | MERR |
575 ((iface->read_write == I2C_SMBUS_READ) ?
580 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
581 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
582 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
587 while (!iface->result) {
588 if (!wait_for_completion_timeout(&iface->complete,
591 dev_err(&adap->dev, "smbus transfer timeout\n");
595 rc = (iface->result >= 0) ? 0 : -1;
601 * Generic I2C SMBus transfer entrypoint
603 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
604 unsigned short flags, char read_write,
605 u8 command, int size, union i2c_smbus_data *data)
607 return bfin_twi_do_smbus_xfer(adap, addr, flags,
608 read_write, command, size, data);
612 * Return what the adapter supports
614 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
616 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
617 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
618 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
619 I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
622 static struct i2c_algorithm bfin_twi_algorithm = {
623 .master_xfer = bfin_twi_master_xfer,
624 .smbus_xfer = bfin_twi_smbus_xfer,
625 .functionality = bfin_twi_functionality,
628 static int i2c_bfin_twi_suspend(struct device *dev)
630 struct bfin_twi_iface *iface = dev_get_drvdata(dev);
632 iface->saved_clkdiv = read_CLKDIV(iface);
633 iface->saved_control = read_CONTROL(iface);
635 free_irq(iface->irq, iface);
638 write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
643 static int i2c_bfin_twi_resume(struct device *dev)
645 struct bfin_twi_iface *iface = dev_get_drvdata(dev);
647 int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
648 0, to_platform_device(dev)->name, iface);
650 dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
654 /* Resume TWI interface clock as specified */
655 write_CLKDIV(iface, iface->saved_clkdiv);
658 write_CONTROL(iface, iface->saved_control);
663 static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
664 i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
666 static int i2c_bfin_twi_probe(struct platform_device *pdev)
668 struct bfin_twi_iface *iface;
669 struct i2c_adapter *p_adap;
670 struct resource *res;
672 unsigned int clkhilow;
674 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
676 dev_err(&pdev->dev, "Cannot allocate memory\n");
678 goto out_error_nomem;
681 spin_lock_init(&(iface->lock));
683 /* Find and map our resources */
684 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
686 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
688 goto out_error_get_res;
691 iface->regs_base = ioremap(res->start, resource_size(res));
692 if (iface->regs_base == NULL) {
693 dev_err(&pdev->dev, "Cannot map IO\n");
695 goto out_error_ioremap;
698 iface->irq = platform_get_irq(pdev, 0);
699 if (iface->irq < 0) {
700 dev_err(&pdev->dev, "No IRQ specified\n");
702 goto out_error_no_irq;
705 p_adap = &iface->adap;
706 p_adap->nr = pdev->id;
707 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
708 p_adap->algo = &bfin_twi_algorithm;
709 p_adap->algo_data = iface;
710 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
711 p_adap->dev.parent = &pdev->dev;
712 p_adap->timeout = 5 * HZ;
715 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
717 dev_err(&pdev->dev, "Can't setup pin mux!\n");
718 goto out_error_pin_mux;
721 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
722 0, pdev->name, iface);
724 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
726 goto out_error_req_irq;
729 /* Set TWI internal clock as 10MHz */
730 write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
733 * We will not end up with a CLKDIV=0 because no one will specify
734 * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
736 clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
738 /* Set Twi interface clock as specified */
739 write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
742 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
745 rc = i2c_add_numbered_adapter(p_adap);
747 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
748 goto out_error_add_adapter;
751 platform_set_drvdata(pdev, iface);
753 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
754 "regs_base@%p\n", iface->regs_base);
758 out_error_add_adapter:
759 free_irq(iface->irq, iface);
762 peripheral_free_list(pin_req[pdev->id]);
764 iounmap(iface->regs_base);
772 static int i2c_bfin_twi_remove(struct platform_device *pdev)
774 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
776 platform_set_drvdata(pdev, NULL);
778 i2c_del_adapter(&(iface->adap));
779 free_irq(iface->irq, iface);
780 peripheral_free_list(pin_req[pdev->id]);
781 iounmap(iface->regs_base);
787 static struct platform_driver i2c_bfin_twi_driver = {
788 .probe = i2c_bfin_twi_probe,
789 .remove = i2c_bfin_twi_remove,
791 .name = "i2c-bfin-twi",
792 .owner = THIS_MODULE,
793 .pm = &i2c_bfin_twi_pm,
797 static int __init i2c_bfin_twi_init(void)
799 return platform_driver_register(&i2c_bfin_twi_driver);
802 static void __exit i2c_bfin_twi_exit(void)
804 platform_driver_unregister(&i2c_bfin_twi_driver);
807 subsys_initcall(i2c_bfin_twi_init);
808 module_exit(i2c_bfin_twi_exit);
810 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
811 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
812 MODULE_LICENSE("GPL");
813 MODULE_ALIAS("platform:i2c-bfin-twi");