2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/errno.h>
31 #include <linux/err.h>
32 #include <linux/i2c.h>
33 #include <linux/interrupt.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/delay.h>
37 #include <linux/module.h>
38 #include "i2c-designware-core.h"
45 #define DW_IC_DATA_CMD 0x10
46 #define DW_IC_SS_SCL_HCNT 0x14
47 #define DW_IC_SS_SCL_LCNT 0x18
48 #define DW_IC_FS_SCL_HCNT 0x1c
49 #define DW_IC_FS_SCL_LCNT 0x20
50 #define DW_IC_INTR_STAT 0x2c
51 #define DW_IC_INTR_MASK 0x30
52 #define DW_IC_RAW_INTR_STAT 0x34
53 #define DW_IC_RX_TL 0x38
54 #define DW_IC_TX_TL 0x3c
55 #define DW_IC_CLR_INTR 0x40
56 #define DW_IC_CLR_RX_UNDER 0x44
57 #define DW_IC_CLR_RX_OVER 0x48
58 #define DW_IC_CLR_TX_OVER 0x4c
59 #define DW_IC_CLR_RD_REQ 0x50
60 #define DW_IC_CLR_TX_ABRT 0x54
61 #define DW_IC_CLR_RX_DONE 0x58
62 #define DW_IC_CLR_ACTIVITY 0x5c
63 #define DW_IC_CLR_STOP_DET 0x60
64 #define DW_IC_CLR_START_DET 0x64
65 #define DW_IC_CLR_GEN_CALL 0x68
66 #define DW_IC_ENABLE 0x6c
67 #define DW_IC_STATUS 0x70
68 #define DW_IC_TXFLR 0x74
69 #define DW_IC_RXFLR 0x78
70 #define DW_IC_TX_ABRT_SOURCE 0x80
71 #define DW_IC_COMP_PARAM_1 0xf4
72 #define DW_IC_COMP_TYPE 0xfc
73 #define DW_IC_COMP_TYPE_VALUE 0x44570140
75 #define DW_IC_INTR_RX_UNDER 0x001
76 #define DW_IC_INTR_RX_OVER 0x002
77 #define DW_IC_INTR_RX_FULL 0x004
78 #define DW_IC_INTR_TX_OVER 0x008
79 #define DW_IC_INTR_TX_EMPTY 0x010
80 #define DW_IC_INTR_RD_REQ 0x020
81 #define DW_IC_INTR_TX_ABRT 0x040
82 #define DW_IC_INTR_RX_DONE 0x080
83 #define DW_IC_INTR_ACTIVITY 0x100
84 #define DW_IC_INTR_STOP_DET 0x200
85 #define DW_IC_INTR_START_DET 0x400
86 #define DW_IC_INTR_GEN_CALL 0x800
88 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
89 DW_IC_INTR_TX_EMPTY | \
90 DW_IC_INTR_TX_ABRT | \
93 #define DW_IC_STATUS_ACTIVITY 0x1
95 #define DW_IC_ERR_TX_ABRT 0x1
100 #define STATUS_IDLE 0x0
101 #define STATUS_WRITE_IN_PROGRESS 0x1
102 #define STATUS_READ_IN_PROGRESS 0x2
104 #define TIMEOUT 20 /* ms */
107 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
109 * only expected abort codes are listed here
110 * refer to the datasheet for the full list
112 #define ABRT_7B_ADDR_NOACK 0
113 #define ABRT_10ADDR1_NOACK 1
114 #define ABRT_10ADDR2_NOACK 2
115 #define ABRT_TXDATA_NOACK 3
116 #define ABRT_GCALL_NOACK 4
117 #define ABRT_GCALL_READ 5
118 #define ABRT_SBYTE_ACKDET 7
119 #define ABRT_SBYTE_NORSTRT 9
120 #define ABRT_10B_RD_NORSTRT 10
121 #define ABRT_MASTER_DIS 11
124 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
125 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
126 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
127 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
128 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
129 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
130 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
131 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
132 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
133 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
134 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
136 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
137 DW_IC_TX_ABRT_10ADDR1_NOACK | \
138 DW_IC_TX_ABRT_10ADDR2_NOACK | \
139 DW_IC_TX_ABRT_TXDATA_NOACK | \
140 DW_IC_TX_ABRT_GCALL_NOACK)
142 static char *abort_sources[] = {
143 [ABRT_7B_ADDR_NOACK] =
144 "slave address not acknowledged (7bit mode)",
145 [ABRT_10ADDR1_NOACK] =
146 "first address byte not acknowledged (10bit mode)",
147 [ABRT_10ADDR2_NOACK] =
148 "second address byte not acknowledged (10bit mode)",
149 [ABRT_TXDATA_NOACK] =
150 "data not acknowledged",
152 "no acknowledgement for a general call",
154 "read after general call",
155 [ABRT_SBYTE_ACKDET] =
156 "start byte acknowledged",
157 [ABRT_SBYTE_NORSTRT] =
158 "trying to send start byte when restart is disabled",
159 [ABRT_10B_RD_NORSTRT] =
160 "trying to read when restart is disabled (10bit mode)",
162 "trying to use disabled adapter",
167 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
171 if (dev->accessor_flags & ACCESS_16BIT)
172 value = readw(dev->base + offset) |
173 (readw(dev->base + offset + 2) << 16);
175 value = readl(dev->base + offset);
177 if (dev->accessor_flags & ACCESS_SWAP)
178 return swab32(value);
183 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
185 if (dev->accessor_flags & ACCESS_SWAP)
188 if (dev->accessor_flags & ACCESS_16BIT) {
189 writew((u16)b, dev->base + offset);
190 writew((u16)(b >> 16), dev->base + offset + 2);
192 writel(b, dev->base + offset);
197 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
200 * DesignWare I2C core doesn't seem to have solid strategy to meet
201 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
202 * will result in violation of the tHD;STA spec.
206 * Conditional expression:
208 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
210 * This is based on the DW manuals, and represents an ideal
211 * configuration. The resulting I2C bus speed will be
212 * faster than any of the others.
214 * If your hardware is free from tHD;STA issue, try this one.
216 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
219 * Conditional expression:
221 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
223 * This is just experimental rule; the tHD;STA period turned
224 * out to be proportinal to (_HCNT + 3). With this setting,
225 * we could meet both tHIGH and tHD;STA timing specs.
227 * If unsure, you'd better to take this alternative.
229 * The reason why we need to take into account "tf" here,
230 * is the same as described in i2c_dw_scl_lcnt().
232 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
235 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
238 * Conditional expression:
240 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
242 * DW I2C core starts counting the SCL CNTs for the LOW period
243 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
244 * In order to meet the tLOW timing spec, we need to take into
245 * account the fall time of SCL signal (tf). Default tf value
246 * should be 0.3 us, for safety.
248 return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
252 * i2c_dw_init() - initialize the designware i2c master hardware
253 * @dev: device private data
255 * This functions configures and enables the I2C master.
256 * This function is called during I2C init function, and in case of timeout at
259 int i2c_dw_init(struct dw_i2c_dev *dev)
265 input_clock_khz = dev->get_clk_rate_khz(dev);
267 reg = dw_readl(dev, DW_IC_COMP_TYPE);
268 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
269 /* Configure register endianess access */
270 dev->accessor_flags |= ACCESS_SWAP;
271 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
272 /* Configure register access mode 16bit */
273 dev->accessor_flags |= ACCESS_16BIT;
274 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
275 dev_err(dev->dev, "Unknown Synopsys component type: "
280 /* Disable the adapter */
281 dw_writel(dev, 0, DW_IC_ENABLE);
283 /* set standard and fast speed deviders for high/low periods */
286 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
287 40, /* tHD;STA = tHIGH = 4.0 us */
289 0, /* 0: DW default, 1: Ideal */
291 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
292 47, /* tLOW = 4.7 us */
295 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
296 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
297 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
300 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
301 6, /* tHD;STA = tHIGH = 0.6 us */
303 0, /* 0: DW default, 1: Ideal */
305 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
306 13, /* tLOW = 1.3 us */
309 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
310 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
311 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
313 /* Configure Tx/Rx FIFO threshold levels */
314 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
315 dw_writel(dev, 0, DW_IC_RX_TL);
317 /* configure the i2c master */
318 dw_writel(dev, dev->master_cfg , DW_IC_CON);
321 EXPORT_SYMBOL_GPL(i2c_dw_init);
324 * Waiting for bus not busy
326 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
328 int timeout = TIMEOUT;
330 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
332 dev_warn(dev->dev, "timeout waiting for bus ready\n");
342 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
344 struct i2c_msg *msgs = dev->msgs;
347 /* Disable the adapter */
348 dw_writel(dev, 0, DW_IC_ENABLE);
350 /* set the slave (target) address */
351 dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
353 /* if the slave address is ten bit address, enable 10BITADDR */
354 ic_con = dw_readl(dev, DW_IC_CON);
355 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
356 ic_con |= DW_IC_CON_10BITADDR_MASTER;
358 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
359 dw_writel(dev, ic_con, DW_IC_CON);
361 /* Enable the adapter */
362 dw_writel(dev, 1, DW_IC_ENABLE);
364 /* Enable interrupts */
365 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
369 * Initiate (and continue) low level master read/write transaction.
370 * This function is only called from i2c_dw_isr, and pumping i2c_msg
371 * messages into the tx buffer. Even if the size of i2c_msg data is
372 * longer than the size of the tx buffer, it handles everything.
375 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
377 struct i2c_msg *msgs = dev->msgs;
379 int tx_limit, rx_limit;
380 u32 addr = msgs[dev->msg_write_idx].addr;
381 u32 buf_len = dev->tx_buf_len;
382 u8 *buf = dev->tx_buf;
384 intr_mask = DW_IC_INTR_DEFAULT_MASK;
386 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
388 * if target address has changed, we need to
389 * reprogram the target address in the i2c
390 * adapter when we are done with this transfer
392 if (msgs[dev->msg_write_idx].addr != addr) {
394 "%s: invalid target address\n", __func__);
395 dev->msg_err = -EINVAL;
399 if (msgs[dev->msg_write_idx].len == 0) {
401 "%s: invalid message length\n", __func__);
402 dev->msg_err = -EINVAL;
406 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
408 buf = msgs[dev->msg_write_idx].buf;
409 buf_len = msgs[dev->msg_write_idx].len;
412 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
413 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
415 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
416 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
417 dw_writel(dev, 0x100, DW_IC_DATA_CMD);
420 dw_writel(dev, *buf++, DW_IC_DATA_CMD);
421 tx_limit--; buf_len--;
425 dev->tx_buf_len = buf_len;
428 /* more bytes to be written */
429 dev->status |= STATUS_WRITE_IN_PROGRESS;
432 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
436 * If i2c_msg index search is completed, we don't need TX_EMPTY
437 * interrupt any more.
439 if (dev->msg_write_idx == dev->msgs_num)
440 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
445 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
449 i2c_dw_read(struct dw_i2c_dev *dev)
451 struct i2c_msg *msgs = dev->msgs;
454 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
458 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
461 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
462 len = msgs[dev->msg_read_idx].len;
463 buf = msgs[dev->msg_read_idx].buf;
465 len = dev->rx_buf_len;
469 rx_valid = dw_readl(dev, DW_IC_RXFLR);
471 for (; len > 0 && rx_valid > 0; len--, rx_valid--)
472 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
475 dev->status |= STATUS_READ_IN_PROGRESS;
476 dev->rx_buf_len = len;
480 dev->status &= ~STATUS_READ_IN_PROGRESS;
484 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
486 unsigned long abort_source = dev->abort_source;
489 if (abort_source & DW_IC_TX_ABRT_NOACK) {
490 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
492 "%s: %s\n", __func__, abort_sources[i]);
496 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
497 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
499 if (abort_source & DW_IC_TX_ARB_LOST)
501 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
502 return -EINVAL; /* wrong msgs[] data */
508 * Prepare controller for a transaction and call i2c_dw_xfer_msg
511 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
513 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
516 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
518 mutex_lock(&dev->lock);
519 pm_runtime_get_sync(dev->dev);
521 INIT_COMPLETION(dev->cmd_complete);
525 dev->msg_write_idx = 0;
526 dev->msg_read_idx = 0;
528 dev->status = STATUS_IDLE;
529 dev->abort_source = 0;
531 ret = i2c_dw_wait_bus_not_busy(dev);
535 /* start the transfers */
536 i2c_dw_xfer_init(dev);
538 /* wait for tx to complete */
539 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
541 dev_err(dev->dev, "controller timed out\n");
554 if (likely(!dev->cmd_err)) {
555 /* Disable the adapter */
556 dw_writel(dev, 0, DW_IC_ENABLE);
561 /* We have an error */
562 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
563 ret = i2c_dw_handle_tx_abort(dev);
569 pm_runtime_put(dev->dev);
570 mutex_unlock(&dev->lock);
574 EXPORT_SYMBOL_GPL(i2c_dw_xfer);
576 u32 i2c_dw_func(struct i2c_adapter *adap)
578 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
579 return dev->functionality;
581 EXPORT_SYMBOL_GPL(i2c_dw_func);
583 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
588 * The IC_INTR_STAT register just indicates "enabled" interrupts.
589 * Ths unmasked raw version of interrupt status bits are available
590 * in the IC_RAW_INTR_STAT register.
593 * stat = dw_readl(IC_INTR_STAT);
595 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
597 * The raw version might be useful for debugging purposes.
599 stat = dw_readl(dev, DW_IC_INTR_STAT);
602 * Do not use the IC_CLR_INTR register to clear interrupts, or
603 * you'll miss some interrupts, triggered during the period from
604 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
606 * Instead, use the separately-prepared IC_CLR_* registers.
608 if (stat & DW_IC_INTR_RX_UNDER)
609 dw_readl(dev, DW_IC_CLR_RX_UNDER);
610 if (stat & DW_IC_INTR_RX_OVER)
611 dw_readl(dev, DW_IC_CLR_RX_OVER);
612 if (stat & DW_IC_INTR_TX_OVER)
613 dw_readl(dev, DW_IC_CLR_TX_OVER);
614 if (stat & DW_IC_INTR_RD_REQ)
615 dw_readl(dev, DW_IC_CLR_RD_REQ);
616 if (stat & DW_IC_INTR_TX_ABRT) {
618 * The IC_TX_ABRT_SOURCE register is cleared whenever
619 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
621 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
622 dw_readl(dev, DW_IC_CLR_TX_ABRT);
624 if (stat & DW_IC_INTR_RX_DONE)
625 dw_readl(dev, DW_IC_CLR_RX_DONE);
626 if (stat & DW_IC_INTR_ACTIVITY)
627 dw_readl(dev, DW_IC_CLR_ACTIVITY);
628 if (stat & DW_IC_INTR_STOP_DET)
629 dw_readl(dev, DW_IC_CLR_STOP_DET);
630 if (stat & DW_IC_INTR_START_DET)
631 dw_readl(dev, DW_IC_CLR_START_DET);
632 if (stat & DW_IC_INTR_GEN_CALL)
633 dw_readl(dev, DW_IC_CLR_GEN_CALL);
639 * Interrupt service routine. This gets called whenever an I2C interrupt
642 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
644 struct dw_i2c_dev *dev = dev_id;
647 enabled = dw_readl(dev, DW_IC_ENABLE);
648 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
649 dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
650 dev->adapter.name, enabled, stat);
651 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
654 stat = i2c_dw_read_clear_intrbits(dev);
656 if (stat & DW_IC_INTR_TX_ABRT) {
657 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
658 dev->status = STATUS_IDLE;
661 * Anytime TX_ABRT is set, the contents of the tx/rx
662 * buffers are flushed. Make sure to skip them.
664 dw_writel(dev, 0, DW_IC_INTR_MASK);
668 if (stat & DW_IC_INTR_RX_FULL)
671 if (stat & DW_IC_INTR_TX_EMPTY)
672 i2c_dw_xfer_msg(dev);
675 * No need to modify or disable the interrupt mask here.
676 * i2c_dw_xfer_msg() will take care of it according to
677 * the current transmit status.
681 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
682 complete(&dev->cmd_complete);
686 EXPORT_SYMBOL_GPL(i2c_dw_isr);
688 void i2c_dw_enable(struct dw_i2c_dev *dev)
690 /* Enable the adapter */
691 dw_writel(dev, 1, DW_IC_ENABLE);
693 EXPORT_SYMBOL_GPL(i2c_dw_enable);
695 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
697 return dw_readl(dev, DW_IC_ENABLE);
699 EXPORT_SYMBOL_GPL(i2c_dw_is_enabled);
701 void i2c_dw_disable(struct dw_i2c_dev *dev)
703 /* Disable controller */
704 dw_writel(dev, 0, DW_IC_ENABLE);
706 /* Disable all interupts */
707 dw_writel(dev, 0, DW_IC_INTR_MASK);
708 dw_readl(dev, DW_IC_CLR_INTR);
710 EXPORT_SYMBOL_GPL(i2c_dw_disable);
712 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
714 dw_readl(dev, DW_IC_CLR_INTR);
716 EXPORT_SYMBOL_GPL(i2c_dw_clear_int);
718 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
720 dw_writel(dev, 0, DW_IC_INTR_MASK);
722 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
724 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
726 return dw_readl(dev, DW_IC_COMP_PARAM_1);
728 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
730 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
731 MODULE_LICENSE("GPL");