drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/i2c-tegra.h>
  29 #include <linux/of_i2c.h>
  30 #include <linux/of_device.h>
  31 #include <linux/module.h>
  32 #include <linux/clk/tegra.h>
  33
  34 #include <asm/unaligned.h>
  35
  36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  37 #define BYTES_PER_FIFO_WORD 4
  38
  39 #define I2C_CNFG                                0x000
  40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  41 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  42 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  43 #define I2C_STATUS                              0x01C
  44 #define I2C_SL_CNFG                             0x020
  45 #define I2C_SL_CNFG_NACK                        (1<<1)
  46 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  47 #define I2C_SL_ADDR1                            0x02c
  48 #define I2C_SL_ADDR2                            0x030
  49 #define I2C_TX_FIFO                             0x050
  50 #define I2C_RX_FIFO                             0x054
  51 #define I2C_PACKET_TRANSFER_STATUS              0x058
  52 #define I2C_FIFO_CONTROL                        0x05c
  53 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  54 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  57 #define I2C_FIFO_STATUS                         0x060
  58 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  59 #define I2C_FIFO_STATUS_TX_SHIFT                4
  60 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  61 #define I2C_FIFO_STATUS_RX_SHIFT                0
  62 #define I2C_INT_MASK                            0x064
  63 #define I2C_INT_STATUS                          0x068
  64 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  66 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  67 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  68 #define I2C_INT_NO_ACK                          (1<<3)
  69 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  70 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  71 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  72 #define I2C_CLK_DIVISOR                         0x06c
  73
  74 #define DVC_CTRL_REG1                           0x000
  75 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  76 #define DVC_CTRL_REG2                           0x004
  77 #define DVC_CTRL_REG3                           0x008
  78 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  80 #define DVC_STATUS                              0x00c
  81 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  82
  83 #define I2C_ERR_NONE                            0x00
  84 #define I2C_ERR_NO_ACK                          0x01
  85 #define I2C_ERR_ARBITRATION_LOST                0x02
  86 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  87
  88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  89 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  90 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  91 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  92
  93 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  94 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  95 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  96 #define I2C_HEADER_READ                         (1<<19)
  97 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  98 #define I2C_HEADER_IE_ENABLE                    (1<<17)
  99 #define I2C_HEADER_REPEAT_START                 (1<<16)
 100 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 101 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 102 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 103 /*
 104  * msg_end_type: The bus control which need to be send at end of transfer.
 105  * @MSG_END_STOP: Send stop pulse at end of transfer.
 106  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 107  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 108  *              stop or repeat start.
 109  */
 110 enum msg_end_type {
 111         MSG_END_STOP,
 112         MSG_END_REPEAT_START,
 113         MSG_END_CONTINUE,
 114 };
 115
 116 /**
 117  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 118  * @has_continue_xfer_support: Continue transfer supports.
 119  */
 120
 121 struct tegra_i2c_hw_feature {
 122         bool has_continue_xfer_support;
 123 };
 124
 125 /**
 126  * struct tegra_i2c_dev - per device i2c context
 127  * @dev: device reference for power management
 128  * @hw: Tegra i2c hw feature.
 129  * @adapter: core i2c layer adapter information
 130  * @div_clk: clock reference for div clock of i2c controller.
 131  * @fast_clk: clock reference for fast clock of i2c controller.
 132  * @base: ioremapped registers cookie
 133  * @cont_id: i2c controller id, used for for packet header
 134  * @irq: irq number of transfer complete interrupt
 135  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 136  * @msg_complete: transfer completion notifier
 137  * @msg_err: error code for completed message
 138  * @msg_buf: pointer to current message data
 139  * @msg_buf_remaining: size of unsent data in the message buffer
 140  * @msg_read: identifies read transfers
 141  * @bus_clk_rate: current i2c bus clock rate
 142  * @is_suspended: prevents i2c controller accesses after suspend is called
 143  */
 144 struct tegra_i2c_dev {
 145         struct device *dev;
 146         const struct tegra_i2c_hw_feature *hw;
 147         struct i2c_adapter adapter;
 148         struct clk *div_clk;
 149         struct clk *fast_clk;
 150         void __iomem *base;
 151         int cont_id;
 152         int irq;
 153         bool irq_disabled;
 154         int is_dvc;
 155         struct completion msg_complete;
 156         int msg_err;
 157         u8 *msg_buf;
 158         size_t msg_buf_remaining;
 159         int msg_read;
 160         unsigned long bus_clk_rate;
 161         bool is_suspended;
 162 };
 163
 164 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 165 {
 166         writel(val, i2c_dev->base + reg);
 167 }
 168
 169 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 170 {
 171         return readl(i2c_dev->base + reg);
 172 }
 173
 174 /*
 175  * i2c_writel and i2c_readl will offset the register if necessary to talk
 176  * to the I2C block inside the DVC block
 177  */
 178 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 179         unsigned long reg)
 180 {
 181         if (i2c_dev->is_dvc)
 182                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 183         return reg;
 184 }
 185
 186 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 187         unsigned long reg)
 188 {
 189         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 190
 191         /* Read back register to make sure that register writes completed */
 192         if (reg != I2C_TX_FIFO)
 193                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 194 }
 195
 196 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 197 {
 198         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 199 }
 200
 201 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 202         unsigned long reg, int len)
 203 {
 204         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 205 }
 206
 207 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 208         unsigned long reg, int len)
 209 {
 210         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 211 }
 212
 213 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 214 {
 215         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 216         int_mask &= ~mask;
 217         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 218 }
 219
 220 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 221 {
 222         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 223         int_mask |= mask;
 224         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 225 }
 226
 227 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 228 {
 229         unsigned long timeout = jiffies + HZ;
 230         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 231         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 232         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 233
 234         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 235                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 236                 if (time_after(jiffies, timeout)) {
 237                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 238                         return -ETIMEDOUT;
 239                 }
 240                 msleep(1);
 241         }
 242         return 0;
 243 }
 244
 245 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 246 {
 247         u32 val;
 248         int rx_fifo_avail;
 249         u8 *buf = i2c_dev->msg_buf;
 250         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 251         int words_to_transfer;
 252
 253         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 254         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 255                 I2C_FIFO_STATUS_RX_SHIFT;
 256
 257         /* Rounds down to not include partial word at the end of buf */
 258         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 259         if (words_to_transfer > rx_fifo_avail)
 260                 words_to_transfer = rx_fifo_avail;
 261
 262         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 263
 264         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 265         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 266         rx_fifo_avail -= words_to_transfer;
 267
 268         /*
 269          * If there is a partial word at the end of buf, handle it manually to
 270          * prevent overwriting past the end of buf
 271          */
 272         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 273                 BUG_ON(buf_remaining > 3);
 274                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 275                 memcpy(buf, &val, buf_remaining);
 276                 buf_remaining = 0;
 277                 rx_fifo_avail--;
 278         }
 279
 280         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 281         i2c_dev->msg_buf_remaining = buf_remaining;
 282         i2c_dev->msg_buf = buf;
 283         return 0;
 284 }
 285
 286 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 287 {
 288         u32 val;
 289         int tx_fifo_avail;
 290         u8 *buf = i2c_dev->msg_buf;
 291         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 292         int words_to_transfer;
 293
 294         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 295         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 296                 I2C_FIFO_STATUS_TX_SHIFT;
 297
 298         /* Rounds down to not include partial word at the end of buf */
 299         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 300
 301         /* It's very common to have < 4 bytes, so optimize that case. */
 302         if (words_to_transfer) {
 303                 if (words_to_transfer > tx_fifo_avail)
 304                         words_to_transfer = tx_fifo_avail;
 305
 306                 /*
 307                  * Update state before writing to FIFO.  If this casues us
 308                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 309                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 310                  * not maskable).  We need to make sure that the isr sees
 311                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 312                  */
 313                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 314                 tx_fifo_avail -= words_to_transfer;
 315                 i2c_dev->msg_buf_remaining = buf_remaining;
 316                 i2c_dev->msg_buf = buf +
 317                         words_to_transfer * BYTES_PER_FIFO_WORD;
 318                 barrier();
 319
 320                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 321
 322                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 323         }
 324
 325         /*
 326          * If there is a partial word at the end of buf, handle it manually to
 327          * prevent reading past the end of buf, which could cross a page
 328          * boundary and fault.
 329          */
 330         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 331                 BUG_ON(buf_remaining > 3);
 332                 memcpy(&val, buf, buf_remaining);
 333
 334                 /* Again update before writing to FIFO to make sure isr sees. */
 335                 i2c_dev->msg_buf_remaining = 0;
 336                 i2c_dev->msg_buf = NULL;
 337                 barrier();
 338
 339                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 340         }
 341
 342         return 0;
 343 }
 344
 345 /*
 346  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 347  * block.  This block is identical to the rest of the I2C blocks, except that
 348  * it only supports master mode, it has registers moved around, and it needs
 349  * some extra init to get it into I2C mode.  The register moves are handled
 350  * by i2c_readl and i2c_writel
 351  */
 352 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 353 {
 354         u32 val = 0;
 355         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 356         val |= DVC_CTRL_REG3_SW_PROG;
 357         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 358         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 359
 360         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 361         val |= DVC_CTRL_REG1_INTR_EN;
 362         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 363 }
 364
 365 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 366 {
 367         int ret;
 368         ret = clk_prepare_enable(i2c_dev->fast_clk);
 369         if (ret < 0) {
 370                 dev_err(i2c_dev->dev,
 371                         "Enabling fast clk failed, err %d\n", ret);
 372                 return ret;
 373         }
 374         ret = clk_prepare_enable(i2c_dev->div_clk);
 375         if (ret < 0) {
 376                 dev_err(i2c_dev->dev,
 377                         "Enabling div clk failed, err %d\n", ret);
 378                 clk_disable_unprepare(i2c_dev->fast_clk);
 379         }
 380         return ret;
 381 }
 382
 383 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 384 {
 385         clk_disable_unprepare(i2c_dev->div_clk);
 386         clk_disable_unprepare(i2c_dev->fast_clk);
 387 }
 388
 389 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 390 {
 391         u32 val;
 392         int err = 0;
 393
 394         tegra_i2c_clock_enable(i2c_dev);
 395
 396         tegra_periph_reset_assert(i2c_dev->div_clk);
 397         udelay(2);
 398         tegra_periph_reset_deassert(i2c_dev->div_clk);
 399
 400         if (i2c_dev->is_dvc)
 401                 tegra_dvc_init(i2c_dev);
 402
 403         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 404                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 405         i2c_writel(i2c_dev, val, I2C_CNFG);
 406         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 407         clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * 8);
 408
 409         if (!i2c_dev->is_dvc) {
 410                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 411                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 412                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 413                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 414                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 415
 416         }
 417
 418         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 419                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 420         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 421
 422         if (tegra_i2c_flush_fifos(i2c_dev))
 423                 err = -ETIMEDOUT;
 424
 425         tegra_i2c_clock_disable(i2c_dev);
 426
 427         if (i2c_dev->irq_disabled) {
 428                 i2c_dev->irq_disabled = 0;
 429                 enable_irq(i2c_dev->irq);
 430         }
 431
 432         return err;
 433 }
 434
 435 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 436 {
 437         u32 status;
 438         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 439         struct tegra_i2c_dev *i2c_dev = dev_id;
 440
 441         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 442
 443         if (status == 0) {
 444                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 445                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 446                          i2c_readl(i2c_dev, I2C_STATUS),
 447                          i2c_readl(i2c_dev, I2C_CNFG));
 448                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 449
 450                 if (!i2c_dev->irq_disabled) {
 451                         disable_irq_nosync(i2c_dev->irq);
 452                         i2c_dev->irq_disabled = 1;
 453                 }
 454                 goto err;
 455         }
 456
 457         if (unlikely(status & status_err)) {
 458                 if (status & I2C_INT_NO_ACK)
 459                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 460                 if (status & I2C_INT_ARBITRATION_LOST)
 461                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 462                 goto err;
 463         }
 464
 465         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 466                 if (i2c_dev->msg_buf_remaining)
 467                         tegra_i2c_empty_rx_fifo(i2c_dev);
 468                 else
 469                         BUG();
 470         }
 471
 472         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 473                 if (i2c_dev->msg_buf_remaining)
 474                         tegra_i2c_fill_tx_fifo(i2c_dev);
 475                 else
 476                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 477         }
 478
 479         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 480         if (i2c_dev->is_dvc)
 481                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 482
 483         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 484                 BUG_ON(i2c_dev->msg_buf_remaining);
 485                 complete(&i2c_dev->msg_complete);
 486         }
 487         return IRQ_HANDLED;
 488 err:
 489         /* An error occurred, mask all interrupts */
 490         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 491                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 492                 I2C_INT_RX_FIFO_DATA_REQ);
 493         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 494         if (i2c_dev->is_dvc)
 495                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 496
 497         complete(&i2c_dev->msg_complete);
 498         return IRQ_HANDLED;
 499 }
 500
 501 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 502         struct i2c_msg *msg, enum msg_end_type end_state)
 503 {
 504         u32 packet_header;
 505         u32 int_mask;
 506         int ret;
 507
 508         tegra_i2c_flush_fifos(i2c_dev);
 509
 510         if (msg->len == 0)
 511                 return -EINVAL;
 512
 513         i2c_dev->msg_buf = msg->buf;
 514         i2c_dev->msg_buf_remaining = msg->len;
 515         i2c_dev->msg_err = I2C_ERR_NONE;
 516         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 517         INIT_COMPLETION(i2c_dev->msg_complete);
 518
 519         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 520                         PACKET_HEADER0_PROTOCOL_I2C |
 521                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 522                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 523         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 524
 525         packet_header = msg->len - 1;
 526         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 527
 528         packet_header = I2C_HEADER_IE_ENABLE;
 529         if (end_state == MSG_END_CONTINUE)
 530                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 531         else if (end_state == MSG_END_REPEAT_START)
 532                 packet_header |= I2C_HEADER_REPEAT_START;
 533         if (msg->flags & I2C_M_TEN) {
 534                 packet_header |= msg->addr;
 535                 packet_header |= I2C_HEADER_10BIT_ADDR;
 536         } else {
 537                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 538         }
 539         if (msg->flags & I2C_M_IGNORE_NAK)
 540                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 541         if (msg->flags & I2C_M_RD)
 542                 packet_header |= I2C_HEADER_READ;
 543         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 544
 545         if (!(msg->flags & I2C_M_RD))
 546                 tegra_i2c_fill_tx_fifo(i2c_dev);
 547
 548         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 549         if (msg->flags & I2C_M_RD)
 550                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 551         else if (i2c_dev->msg_buf_remaining)
 552                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 553         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 554         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 555                 i2c_readl(i2c_dev, I2C_INT_MASK));
 556
 557         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 558         tegra_i2c_mask_irq(i2c_dev, int_mask);
 559
 560         if (WARN_ON(ret == 0)) {
 561                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 562
 563                 tegra_i2c_init(i2c_dev);
 564                 return -ETIMEDOUT;
 565         }
 566
 567         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 568                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 569
 570         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 571                 return 0;
 572
 573         /*
 574          * NACK interrupt is generated before the I2C controller generates the
 575          * STOP condition on the bus. So wait for 2 clock periods before resetting
 576          * the controller so that STOP condition has been delivered properly.
 577          */
 578         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 579                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 580
 581         tegra_i2c_init(i2c_dev);
 582         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 583                 if (msg->flags & I2C_M_IGNORE_NAK)
 584                         return 0;
 585                 return -EREMOTEIO;
 586         }
 587
 588         return -EIO;
 589 }
 590
 591 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 592         int num)
 593 {
 594         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 595         int i;
 596         int ret = 0;
 597
 598         if (i2c_dev->is_suspended)
 599                 return -EBUSY;
 600
 601         tegra_i2c_clock_enable(i2c_dev);
 602         for (i = 0; i < num; i++) {
 603                 enum msg_end_type end_type = MSG_END_STOP;
 604                 if (i < (num - 1)) {
 605                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 606                                 end_type = MSG_END_CONTINUE;
 607                         else
 608                                 end_type = MSG_END_REPEAT_START;
 609                 }
 610                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 611                 if (ret)
 612                         break;
 613         }
 614         tegra_i2c_clock_disable(i2c_dev);
 615         return ret ?: i;
 616 }
 617
 618 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 619 {
 620         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 621         u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
 622                                 I2C_FUNC_PROTOCOL_MANGLING;
 623
 624         if (i2c_dev->hw->has_continue_xfer_support)
 625                 ret |= I2C_FUNC_NOSTART;
 626         return ret;
 627 }
 628
 629 static const struct i2c_algorithm tegra_i2c_algo = {
 630         .master_xfer    = tegra_i2c_xfer,
 631         .functionality  = tegra_i2c_func,
 632 };
 633
 634 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 635         .has_continue_xfer_support = false,
 636 };
 637
 638 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 639         .has_continue_xfer_support = true,
 640 };
 641
 642 #if defined(CONFIG_OF)
 643 /* Match table for of_platform binding */
 644 static const struct of_device_id tegra_i2c_of_match[] = {
 645         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 646         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 647         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 648         {},
 649 };
 650 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 651 #endif
 652
 653 static int tegra_i2c_probe(struct platform_device *pdev)
 654 {
 655         struct tegra_i2c_dev *i2c_dev;
 656         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
 657         struct resource *res;
 658         struct clk *div_clk;
 659         struct clk *fast_clk;
 660         const unsigned int *prop;
 661         void __iomem *base;
 662         int irq;
 663         int ret = 0;
 664
 665         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 666         if (!res) {
 667                 dev_err(&pdev->dev, "no mem resource\n");
 668                 return -EINVAL;
 669         }
 670
 671         base = devm_ioremap_resource(&pdev->dev, res);
 672         if (IS_ERR(base))
 673                 return PTR_ERR(base);
 674
 675         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 676         if (!res) {
 677                 dev_err(&pdev->dev, "no irq resource\n");
 678                 return -EINVAL;
 679         }
 680         irq = res->start;
 681
 682         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 683         if (IS_ERR(div_clk)) {
 684                 dev_err(&pdev->dev, "missing controller clock");
 685                 return PTR_ERR(div_clk);
 686         }
 687
 688         fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 689         if (IS_ERR(fast_clk)) {
 690                 dev_err(&pdev->dev, "missing bus clock");
 691                 return PTR_ERR(fast_clk);
 692         }
 693
 694         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 695         if (!i2c_dev) {
 696                 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
 697                 return -ENOMEM;
 698         }
 699
 700         i2c_dev->base = base;
 701         i2c_dev->div_clk = div_clk;
 702         i2c_dev->fast_clk = fast_clk;
 703         i2c_dev->adapter.algo = &tegra_i2c_algo;
 704         i2c_dev->irq = irq;
 705         i2c_dev->cont_id = pdev->id;
 706         i2c_dev->dev = &pdev->dev;
 707
 708         i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 709         if (pdata) {
 710                 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
 711
 712         } else if (i2c_dev->dev->of_node) {    /* if there is a device tree node ... */
 713                 prop = of_get_property(i2c_dev->dev->of_node,
 714                                 "clock-frequency", NULL);
 715                 if (prop)
 716                         i2c_dev->bus_clk_rate = be32_to_cpup(prop);
 717         }
 718
 719         i2c_dev->hw = &tegra20_i2c_hw;
 720
 721         if (pdev->dev.of_node) {
 722                 const struct of_device_id *match;
 723                 match = of_match_device(of_match_ptr(tegra_i2c_of_match),
 724                                                 &pdev->dev);
 725                 i2c_dev->hw = match->data;
 726                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 727                                                 "nvidia,tegra20-i2c-dvc");
 728         } else if (pdev->id == 3) {
 729                 i2c_dev->is_dvc = 1;
 730         }
 731         init_completion(&i2c_dev->msg_complete);
 732
 733         platform_set_drvdata(pdev, i2c_dev);
 734
 735         ret = tegra_i2c_init(i2c_dev);
 736         if (ret) {
 737                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 738                 return ret;
 739         }
 740
 741         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 742                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 743         if (ret) {
 744                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 745                 return ret;
 746         }
 747
 748         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 749         i2c_dev->adapter.owner = THIS_MODULE;
 750         i2c_dev->adapter.class = I2C_CLASS_HWMON;
 751         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 752                 sizeof(i2c_dev->adapter.name));
 753         i2c_dev->adapter.algo = &tegra_i2c_algo;
 754         i2c_dev->adapter.dev.parent = &pdev->dev;
 755         i2c_dev->adapter.nr = pdev->id;
 756         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 757
 758         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 759         if (ret) {
 760                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 761                 return ret;
 762         }
 763
 764         of_i2c_register_devices(&i2c_dev->adapter);
 765
 766         return 0;
 767 }
 768
 769 static int tegra_i2c_remove(struct platform_device *pdev)
 770 {
 771         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 772         i2c_del_adapter(&i2c_dev->adapter);
 773         return 0;
 774 }
 775
 776 #ifdef CONFIG_PM_SLEEP
 777 static int tegra_i2c_suspend(struct device *dev)
 778 {
 779         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 780
 781         i2c_lock_adapter(&i2c_dev->adapter);
 782         i2c_dev->is_suspended = true;
 783         i2c_unlock_adapter(&i2c_dev->adapter);
 784
 785         return 0;
 786 }
 787
 788 static int tegra_i2c_resume(struct device *dev)
 789 {
 790         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 791         int ret;
 792
 793         i2c_lock_adapter(&i2c_dev->adapter);
 794
 795         ret = tegra_i2c_init(i2c_dev);
 796
 797         if (ret) {
 798                 i2c_unlock_adapter(&i2c_dev->adapter);
 799                 return ret;
 800         }
 801
 802         i2c_dev->is_suspended = false;
 803
 804         i2c_unlock_adapter(&i2c_dev->adapter);
 805
 806         return 0;
 807 }
 808
 809 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
 810 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
 811 #else
 812 #define TEGRA_I2C_PM    NULL
 813 #endif
 814
 815 static struct platform_driver tegra_i2c_driver = {
 816         .probe   = tegra_i2c_probe,
 817         .remove  = tegra_i2c_remove,
 818         .driver  = {
 819                 .name  = "tegra-i2c",
 820                 .owner = THIS_MODULE,
 821                 .of_match_table = of_match_ptr(tegra_i2c_of_match),
 822                 .pm    = TEGRA_I2C_PM,
 823         },
 824 };
 825
 826 static int __init tegra_i2c_init_driver(void)
 827 {
 828         return platform_driver_register(&tegra_i2c_driver);
 829 }
 830
 831 static void __exit tegra_i2c_exit_driver(void)
 832 {
 833         platform_driver_unregister(&tegra_i2c_driver);
 834 }
 835
 836 subsys_initcall(tegra_i2c_init_driver);
 837 module_exit(tegra_i2c_exit_driver);
 838
 839 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 840 MODULE_AUTHOR("Colin Cross");
 841 MODULE_LICENSE("GPL v2");