2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/funcmux.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch-tegra/clk_rst.h>
18 #include <asm/arch-tegra/tegra_i2c.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* Information about i2c controller */
25 enum periph_id periph_id;
28 struct i2c_control *control;
29 struct i2c_ctlr *regs;
30 int is_dvc; /* DVC type, rather than I2C */
31 int is_scs; /* single clock source (T114+) */
32 int inited; /* bus is inited */
35 static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
37 static void set_packet_mode(struct i2c_bus *i2c_bus)
41 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
43 if (i2c_bus->is_dvc) {
44 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
46 writel(config, &dvc->cnfg);
48 writel(config, &i2c_bus->regs->cnfg);
50 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
51 * issues, i.e., some slaves may be wrongly detected.
53 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
57 static void i2c_reset_controller(struct i2c_bus *i2c_bus)
59 /* Reset I2C controller. */
60 reset_periph(i2c_bus->periph_id, 1);
62 /* re-program config register to packet mode */
63 set_packet_mode(i2c_bus);
66 static void i2c_init_controller(struct i2c_bus *i2c_bus)
69 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
70 * here, in section 23.3.1, but in fact we seem to need a factor of
71 * 16 to get the right frequency.
73 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
74 i2c_bus->speed * 2 * 8);
76 if (i2c_bus->is_scs) {
78 * T114 I2C went to a single clock source for standard/fast and
79 * HS clock speeds. The new clock rate setting calculation is:
80 * SCL = CLK_SOURCE.I2C /
81 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
82 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
84 * NOTE: We do this here, after the initial clock/pll start,
85 * because if we read the clk_div reg before the controller
86 * is running, we hang, and we need it for the new calc.
88 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
89 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
92 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
93 CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
97 /* Reset I2C controller. */
98 i2c_reset_controller(i2c_bus);
100 /* Configure I2C controller. */
101 if (i2c_bus->is_dvc) { /* only for DVC I2C */
102 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
104 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
107 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config);
110 static void send_packet_headers(
111 struct i2c_bus *i2c_bus,
112 struct i2c_trans_info *trans,
117 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
118 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
119 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
120 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
121 writel(data, &i2c_bus->control->tx_fifo);
122 debug("pkt header 1 sent (0x%x)\n", data);
124 /* prepare header2 */
125 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
126 writel(data, &i2c_bus->control->tx_fifo);
127 debug("pkt header 2 sent (0x%x)\n", data);
129 /* prepare IO specific header: configure the slave address */
130 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
132 /* Enable Read if it is not a write transaction */
133 if (!(trans->flags & I2C_IS_WRITE))
134 data |= PKT_HDR3_READ_MODE_MASK;
136 /* Write I2C specific header */
137 writel(data, &i2c_bus->control->tx_fifo);
138 debug("pkt header 3 sent (0x%x)\n", data);
141 static int wait_for_tx_fifo_empty(struct i2c_control *control)
144 int timeout_us = I2C_TIMEOUT_USEC;
146 while (timeout_us >= 0) {
147 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
148 >> TX_FIFO_EMPTY_CNT_SHIFT;
149 if (count == I2C_FIFO_DEPTH)
158 static int wait_for_rx_fifo_notempty(struct i2c_control *control)
161 int timeout_us = I2C_TIMEOUT_USEC;
163 while (timeout_us >= 0) {
164 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
165 >> TX_FIFO_FULL_CNT_SHIFT;
175 static int wait_for_transfer_complete(struct i2c_control *control)
178 int timeout_us = I2C_TIMEOUT_USEC;
180 while (timeout_us >= 0) {
181 int_status = readl(&control->int_status);
182 if (int_status & I2C_INT_NO_ACK_MASK)
184 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
186 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
196 static int send_recv_packets(struct i2c_bus *i2c_bus,
197 struct i2c_trans_info *trans)
199 struct i2c_control *control = i2c_bus->control;
206 int is_write = trans->flags & I2C_IS_WRITE;
208 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
209 int_status = readl(&control->int_status);
210 writel(int_status, &control->int_status);
212 send_packet_headers(i2c_bus, trans, 1);
214 words = DIV_ROUND_UP(trans->num_bytes, 4);
215 last_bytes = trans->num_bytes & 3;
219 u32 *wptr = (u32 *)dptr;
222 /* deal with word alignment */
223 if ((unsigned)dptr & 3) {
224 memcpy(&local, dptr, sizeof(u32));
225 writel(local, &control->tx_fifo);
226 debug("pkt data sent (0x%x)\n", local);
228 writel(*wptr, &control->tx_fifo);
229 debug("pkt data sent (0x%x)\n", *wptr);
231 if (!wait_for_tx_fifo_empty(control)) {
236 if (!wait_for_rx_fifo_notempty(control)) {
241 * for the last word, we read into our local buffer,
242 * in case that caller did not provide enough buffer.
244 local = readl(&control->rx_fifo);
245 if ((words == 1) && last_bytes)
246 memcpy(dptr, (char *)&local, last_bytes);
247 else if ((unsigned)dptr & 3)
248 memcpy(dptr, &local, sizeof(u32));
251 debug("pkt data received (0x%x)\n", local);
257 if (wait_for_transfer_complete(control)) {
263 /* error, reset the controller. */
264 i2c_reset_controller(i2c_bus);
269 static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
273 struct i2c_trans_info trans_info;
275 trans_info.address = addr;
276 trans_info.buf = data;
277 trans_info.flags = I2C_IS_WRITE;
278 trans_info.num_bytes = len;
279 trans_info.is_10bit_address = 0;
281 error = send_recv_packets(bus, &trans_info);
283 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
288 static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data,
292 struct i2c_trans_info trans_info;
294 trans_info.address = addr | 1;
295 trans_info.buf = data;
296 trans_info.flags = 0;
297 trans_info.num_bytes = len;
298 trans_info.is_10bit_address = 0;
300 error = send_recv_packets(bus, &trans_info);
302 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
307 #ifndef CONFIG_OF_CONTROL
308 #error "Please enable device tree support to use this driver"
312 * Check that a bus number is valid and return a pointer to it
314 * @param bus_num Bus number to check / return
315 * @return pointer to bus, if valid, else NULL
317 static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap)
321 bus = &i2c_controllers[adap->hwadapnr];
323 debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
330 static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
335 bus = tegra_i2c_get_bus(adap);
339 i2c_init_controller(bus);
344 static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
346 i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
349 * We don't have a binding for pinmux yet. Leave it out for now. So
350 * far no one needs anything other than the default.
352 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
353 i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
354 i2c_bus->periph_id = clock_decode_periph_id(blob, node);
357 * We can't specify the pinmux config in the fdt, so I2C2 will not
358 * work on Seaboard. It normally has no devices on it anyway.
359 * You could add in this little hack if you need to use it.
360 * The correct solution is a pinmux binding in the fdt.
362 * if (i2c_bus->periph_id == PERIPH_ID_I2C2)
363 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
365 if (i2c_bus->periph_id == -1)
366 return -FDT_ERR_NOTFOUND;
372 * Process a list of nodes, adding them to our list of I2C ports.
374 * @param blob fdt blob
375 * @param node_list list of nodes to process (any <=0 are ignored)
376 * @param count number of nodes to process
377 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
378 * @param is_scs 1 if this HW uses a single clock source (T114+)
379 * @return 0 if ok, -1 on error
381 static int process_nodes(const void *blob, int node_list[], int count,
382 int is_dvc, int is_scs)
384 struct i2c_bus *i2c_bus;
387 /* build the i2c_controllers[] for each controller */
388 for (i = 0; i < count; i++) {
389 int node = node_list[i];
394 i2c_bus = &i2c_controllers[i];
397 if (i2c_get_config(blob, node, i2c_bus)) {
398 printf("i2c_init_board: failed to decode bus %d\n", i);
402 i2c_bus->is_scs = is_scs;
404 i2c_bus->is_dvc = is_dvc;
407 &((struct dvc_ctlr *)i2c_bus->regs)->control;
409 i2c_bus->control = &i2c_bus->regs->control;
411 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
412 is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
413 i2c_bus->periph_id, i2c_bus->speed);
414 i2c_init_controller(i2c_bus);
418 /* Mark position as used */
425 /* Sadly there is no error return from this function */
426 void i2c_init_board(void)
428 int node_list[TEGRA_I2C_NUM_CONTROLLERS];
429 const void *blob = gd->fdt_blob;
432 /* First check for newer (T114+) I2C ports */
433 count = fdtdec_find_aliases_for_id(blob, "i2c",
434 COMPAT_NVIDIA_TEGRA114_I2C, node_list,
435 TEGRA_I2C_NUM_CONTROLLERS);
436 if (process_nodes(blob, node_list, count, 0, 1))
439 /* Now get the older (T20/T30) normal I2C ports */
440 count = fdtdec_find_aliases_for_id(blob, "i2c",
441 COMPAT_NVIDIA_TEGRA20_I2C, node_list,
442 TEGRA_I2C_NUM_CONTROLLERS);
443 if (process_nodes(blob, node_list, count, 0, 0))
446 /* Now look for dvc ports */
447 count = fdtdec_add_aliases_for_id(blob, "i2c",
448 COMPAT_NVIDIA_TEGRA20_DVC, node_list,
449 TEGRA_I2C_NUM_CONTROLLERS);
450 if (process_nodes(blob, node_list, count, 1, 0))
454 static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
456 /* This will override the speed selected in the fdt for that port */
457 debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
458 i2c_set_bus_speed(speed);
461 /* i2c write version without the register address */
462 int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
466 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
467 debug("write_data: ");
468 /* use rc for counter */
469 for (rc = 0; rc < len; ++rc)
470 debug(" 0x%02x", buffer[rc]);
473 /* Shift 7-bit address over for lower-level i2c functions */
474 rc = tegra_i2c_write_data(bus, chip << 1, buffer, len);
476 debug("i2c_write_data(): rc=%d\n", rc);
481 /* i2c read version without the register address */
482 int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer, int len)
486 debug("inside i2c_read_data():\n");
487 /* Shift 7-bit address over for lower-level i2c functions */
488 rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
490 debug("i2c_read_data(): rc=%d\n", rc);
494 debug("i2c_read_data: ");
495 /* reuse rc for counter*/
496 for (rc = 0; rc < len; ++rc)
497 debug(" 0x%02x", buffer[rc]);
503 /* Probe to see if a chip is present. */
504 static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
510 debug("i2c_probe: addr=0x%x\n", chip);
511 bus = tegra_i2c_get_bus(adap);
515 rc = i2c_write_data(bus, chip, ®, 1);
517 debug("Error probing 0x%x.\n", chip);
523 static int i2c_addr_ok(const uint addr, const int alen)
525 /* We support 7 or 10 bit addresses, so one or two bytes each */
526 return alen == 1 || alen == 2;
530 static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
531 int alen, uchar *buffer, int len)
537 debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n",
539 bus = tegra_i2c_get_bus(adap);
542 if (!i2c_addr_ok(addr, alen)) {
543 debug("i2c_read: Bad address %x.%d.\n", addr, alen);
546 for (offset = 0; offset < len; offset++) {
549 for (i = 0; i < alen; i++) {
551 (addr + offset) >> (8 * i);
553 if (i2c_write_data(bus, chip, data, alen)) {
554 debug("i2c_read: error sending (0x%x)\n",
559 if (i2c_read_data(bus, chip, buffer + offset, 1)) {
560 debug("i2c_read: error reading (0x%x)\n", addr);
569 static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
570 int alen, uchar *buffer, int len)
576 debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n",
578 bus = tegra_i2c_get_bus(adap);
581 if (!i2c_addr_ok(addr, alen)) {
582 debug("i2c_write: Bad address %x.%d.\n", addr, alen);
585 for (offset = 0; offset < len; offset++) {
586 uchar data[alen + 1];
587 for (i = 0; i < alen; i++)
588 data[alen - i - 1] = (addr + offset) >> (8 * i);
589 data[alen] = buffer[offset];
590 if (i2c_write_data(bus, chip, data, alen + 1)) {
591 debug("i2c_write: error sending (0x%x)\n", addr);
599 int tegra_i2c_get_dvc_bus_num(void)
603 for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
604 struct i2c_bus *bus = &i2c_controllers[i];
606 if (bus->inited && bus->is_dvc)
614 * Register soft i2c adapters
616 U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
617 tegra_i2c_read, tegra_i2c_write,
618 tegra_i2c_set_bus_speed, 100000, 0, 0)
619 U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
620 tegra_i2c_read, tegra_i2c_write,
621 tegra_i2c_set_bus_speed, 100000, 0, 1)
622 U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
623 tegra_i2c_read, tegra_i2c_write,
624 tegra_i2c_set_bus_speed, 100000, 0, 2)
625 U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
626 tegra_i2c_read, tegra_i2c_write,
627 tegra_i2c_set_bus_speed, 100000, 0, 3)