2 * linux/drivers/ide/pci/cmd64x.c Version 1.50 May 10, 2007
4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
5 * Due to massive hardware bugs, UltraDMA is only supported
6 * on the 646U2 and not on the 646U.
8 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
11 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/hdreg.h>
20 #include <linux/ide.h>
21 #include <linux/init.h>
25 #define DISPLAY_CMD64X_TIMINGS
30 #define cmdprintk(x...) printk(x)
32 #define cmdprintk(x...)
36 * CMD64x specific registers definition.
39 #define CFR_INTR_CH0 0x04
41 #define CNTRL_ENA_1ST 0x04
42 #define CNTRL_ENA_2ND 0x08
43 #define CNTRL_DIS_RA0 0x40
44 #define CNTRL_DIS_RA1 0x80
52 #define ARTTIM23_DIS_RA2 0x04
53 #define ARTTIM23_DIS_RA3 0x08
54 #define ARTTIM23_INTR_CH1 0x10
61 #define MRDMODE_INTR_CH0 0x04
62 #define MRDMODE_INTR_CH1 0x08
63 #define MRDMODE_BLK_CH0 0x10
64 #define MRDMODE_BLK_CH1 0x20
66 #define UDIDETCR0 0x73
71 #define UDIDETCR1 0x7B
74 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
75 #include <linux/stat.h>
76 #include <linux/proc_fs.h>
78 static u8 cmd64x_proc = 0;
80 #define CMD_MAX_DEVS 5
82 static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
83 static int n_cmd_devs;
85 static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
88 u8 reg72 = 0, reg73 = 0; /* primary */
89 u8 reg7a = 0, reg7b = 0; /* secondary */
90 u8 reg50 = 1, reg51 = 1, reg57 = 0, reg71 = 0; /* extra */
92 p += sprintf(p, "\nController: %d\n", index);
93 p += sprintf(p, "PCI-%x Chipset.\n", dev->device);
95 (void) pci_read_config_byte(dev, CFR, ®50);
96 (void) pci_read_config_byte(dev, CNTRL, ®51);
97 (void) pci_read_config_byte(dev, ARTTIM23, ®57);
98 (void) pci_read_config_byte(dev, MRDMODE, ®71);
99 (void) pci_read_config_byte(dev, BMIDESR0, ®72);
100 (void) pci_read_config_byte(dev, UDIDETCR0, ®73);
101 (void) pci_read_config_byte(dev, BMIDESR1, ®7a);
102 (void) pci_read_config_byte(dev, UDIDETCR1, ®7b);
104 /* PCI0643/6 originally didn't have the primary channel enable bit */
105 if ((dev->device == PCI_DEVICE_ID_CMD_643) ||
106 (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 3))
107 reg51 |= CNTRL_ENA_1ST;
109 p += sprintf(p, "---------------- Primary Channel "
110 "---------------- Secondary Channel ------------\n");
111 p += sprintf(p, " %s %s\n",
112 (reg51 & CNTRL_ENA_1ST) ? "enabled " : "disabled",
113 (reg51 & CNTRL_ENA_2ND) ? "enabled " : "disabled");
114 p += sprintf(p, "---------------- drive0 --------- drive1 "
115 "-------- drive0 --------- drive1 ------\n");
116 p += sprintf(p, "DMA enabled: %s %s"
118 (reg72 & 0x20) ? "yes" : "no ", (reg72 & 0x40) ? "yes" : "no ",
119 (reg7a & 0x20) ? "yes" : "no ", (reg7a & 0x40) ? "yes" : "no ");
120 p += sprintf(p, "UltraDMA mode: %s (%c) %s (%c)",
121 ( reg73 & 0x01) ? " on" : "off",
122 ((reg73 & 0x30) == 0x30) ? ((reg73 & 0x04) ? '3' : '0') :
123 ((reg73 & 0x30) == 0x20) ? ((reg73 & 0x04) ? '3' : '1') :
124 ((reg73 & 0x30) == 0x10) ? ((reg73 & 0x04) ? '4' : '2') :
125 ((reg73 & 0x30) == 0x00) ? ((reg73 & 0x04) ? '5' : '2') : '?',
126 ( reg73 & 0x02) ? " on" : "off",
127 ((reg73 & 0xC0) == 0xC0) ? ((reg73 & 0x08) ? '3' : '0') :
128 ((reg73 & 0xC0) == 0x80) ? ((reg73 & 0x08) ? '3' : '1') :
129 ((reg73 & 0xC0) == 0x40) ? ((reg73 & 0x08) ? '4' : '2') :
130 ((reg73 & 0xC0) == 0x00) ? ((reg73 & 0x08) ? '5' : '2') : '?');
131 p += sprintf(p, " %s (%c) %s (%c)\n",
132 ( reg7b & 0x01) ? " on" : "off",
133 ((reg7b & 0x30) == 0x30) ? ((reg7b & 0x04) ? '3' : '0') :
134 ((reg7b & 0x30) == 0x20) ? ((reg7b & 0x04) ? '3' : '1') :
135 ((reg7b & 0x30) == 0x10) ? ((reg7b & 0x04) ? '4' : '2') :
136 ((reg7b & 0x30) == 0x00) ? ((reg7b & 0x04) ? '5' : '2') : '?',
137 ( reg7b & 0x02) ? " on" : "off",
138 ((reg7b & 0xC0) == 0xC0) ? ((reg7b & 0x08) ? '3' : '0') :
139 ((reg7b & 0xC0) == 0x80) ? ((reg7b & 0x08) ? '3' : '1') :
140 ((reg7b & 0xC0) == 0x40) ? ((reg7b & 0x08) ? '4' : '2') :
141 ((reg7b & 0xC0) == 0x00) ? ((reg7b & 0x08) ? '5' : '2') : '?');
142 p += sprintf(p, "Interrupt: %s, %s %s, %s\n",
143 (reg71 & MRDMODE_BLK_CH0 ) ? "blocked" : "enabled",
144 (reg50 & CFR_INTR_CH0 ) ? "pending" : "clear ",
145 (reg71 & MRDMODE_BLK_CH1 ) ? "blocked" : "enabled",
146 (reg57 & ARTTIM23_INTR_CH1) ? "pending" : "clear ");
151 static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
156 for (i = 0; i < n_cmd_devs; i++) {
157 struct pci_dev *dev = cmd_devs[i];
158 p = print_cmd64x_get_info(p, dev, i);
160 return p-buffer; /* => must be less than 4k! */
163 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
165 static u8 quantize_timing(int timing, int quant)
167 return (timing + quant - 1) / quant;
171 * This routine calculates active/recovery counts and then writes them into
172 * the chipset registers.
174 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
176 struct pci_dev *dev = HWIF(drive)->pci_dev;
177 int clock_time = 1000 / system_bus_clock();
178 u8 cycle_count, active_count, recovery_count, drwtim;
179 static const u8 recovery_values[] =
180 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
181 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
183 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
184 cycle_time, active_time);
186 cycle_count = quantize_timing( cycle_time, clock_time);
187 active_count = quantize_timing(active_time, clock_time);
188 recovery_count = cycle_count - active_count;
191 * In case we've got too long recovery phase, try to lengthen
194 if (recovery_count > 16) {
195 active_count += recovery_count - 16;
198 if (active_count > 16) /* shouldn't actually happen... */
201 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
202 cycle_count, active_count, recovery_count);
205 * Convert values to internal chipset representation
207 recovery_count = recovery_values[recovery_count];
208 active_count &= 0x0f;
210 /* Program the active/recovery counts into the DRWTIM register */
211 drwtim = (active_count << 4) | recovery_count;
212 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
213 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
217 * This routine selects drive's best PIO mode and writes into the chipset
218 * registers setup/active/recovery timings.
220 static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
222 ide_hwif_t *hwif = HWIF(drive);
223 struct pci_dev *dev = hwif->pci_dev;
225 u8 pio_mode, setup_count, arttim = 0;
226 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
227 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
228 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
230 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)\n",
231 drive->name, mode_wanted, pio_mode, pio.cycle_time);
233 program_cycle_times(drive, pio.cycle_time,
234 ide_pio_timings[pio_mode].active_time);
236 setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
237 1000 / system_bus_clock());
240 * The primary channel has individual address setup timing registers
241 * for each drive and the hardware selects the slowest timing itself.
242 * The secondary channel has one common register and we have to select
243 * the slowest address setup timing ourselves.
246 ide_drive_t *drives = hwif->drives;
248 drive->drive_data = setup_count;
249 setup_count = max(drives[0].drive_data, drives[1].drive_data);
252 if (setup_count > 5) /* shouldn't actually happen... */
254 cmdprintk("Final address setup count: %d\n", setup_count);
257 * Program the address setup clocks into the ARTTIM registers.
258 * Avoid clearing the secondary channel's interrupt bit.
260 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
262 arttim &= ~ARTTIM23_INTR_CH1;
264 arttim |= setup_values[setup_count];
265 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
266 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
272 * Attempts to set drive's PIO mode.
273 * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
274 * and 255: auto-select best mode (used at boot time).
276 static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio)
279 * Filter out the prefetch control values
280 * to prevent PIO5 from being programmed
282 if (pio == 8 || pio == 9)
285 pio = cmd64x_tune_pio(drive, pio);
286 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
289 static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
291 ide_hwif_t *hwif = HWIF(drive);
292 struct pci_dev *dev = hwif->pci_dev;
293 u8 unit = drive->dn & 0x01;
294 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
296 speed = ide_rate_filter(drive, speed);
298 if (speed >= XFER_SW_DMA_0) {
299 (void) pci_read_config_byte(dev, pciU, ®U);
300 regU &= ~(unit ? 0xCA : 0x35);
305 regU |= unit ? 0x0A : 0x05;
308 regU |= unit ? 0x4A : 0x15;
311 regU |= unit ? 0x8A : 0x25;
314 regU |= unit ? 0x42 : 0x11;
317 regU |= unit ? 0x82 : 0x21;
320 regU |= unit ? 0xC2 : 0x31;
323 program_cycle_times(drive, 120, 70);
326 program_cycle_times(drive, 150, 80);
329 program_cycle_times(drive, 480, 215);
337 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
343 if (speed >= XFER_SW_DMA_0)
344 (void) pci_write_config_byte(dev, pciU, regU);
346 return ide_config_drive_speed(drive, speed);
349 static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
351 if (ide_tune_dma(drive))
354 if (ide_use_fast_pio(drive))
355 cmd64x_tune_drive(drive, 255);
360 static int cmd648_ide_dma_end (ide_drive_t *drive)
362 ide_hwif_t *hwif = HWIF(drive);
363 int err = __ide_dma_end(drive);
364 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
366 u8 mrdmode = inb(hwif->dma_master + 0x01);
368 /* clear the interrupt bit */
369 outb(mrdmode | irq_mask, hwif->dma_master + 0x01);
374 static int cmd64x_ide_dma_end (ide_drive_t *drive)
376 ide_hwif_t *hwif = HWIF(drive);
377 struct pci_dev *dev = hwif->pci_dev;
378 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
379 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
382 int err = __ide_dma_end(drive);
384 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
385 /* clear the interrupt bit */
386 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
391 static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
393 ide_hwif_t *hwif = HWIF(drive);
394 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
396 u8 dma_stat = inb(hwif->dma_status);
397 u8 mrdmode = inb(hwif->dma_master + 0x01);
400 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
401 drive->name, dma_stat, mrdmode, irq_mask);
403 if (!(mrdmode & irq_mask))
406 /* return 1 if INTR asserted */
413 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
415 ide_hwif_t *hwif = HWIF(drive);
416 struct pci_dev *dev = hwif->pci_dev;
417 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
418 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
420 u8 dma_stat = inb(hwif->dma_status);
423 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
426 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
427 drive->name, dma_stat, irq_stat, irq_mask);
429 if (!(irq_stat & irq_mask))
432 /* return 1 if INTR asserted */
440 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
441 * event order for DMA transfers.
444 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
446 ide_hwif_t *hwif = HWIF(drive);
447 u8 dma_stat = 0, dma_cmd = 0;
449 drive->waiting_for_dma = 0;
451 dma_stat = inb(hwif->dma_status);
452 /* read DMA command state */
453 dma_cmd = inb(hwif->dma_command);
455 outb(dma_cmd & ~1, hwif->dma_command);
456 /* clear the INTR & ERROR bits */
457 outb(dma_stat | 6, hwif->dma_status);
458 /* and free any DMA resources */
459 ide_destroy_dmatable(drive);
460 /* verify good DMA status */
461 return (dma_stat & 7) != 4;
464 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
468 if (dev->device == PCI_DEVICE_ID_CMD_646) {
471 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
476 printk("%s: UltraDMA capable", name);
480 printk("%s: MultiWord DMA force limited", name);
483 printk("%s: MultiWord DMA limited, "
484 "IRQ workaround enabled\n", name);
489 /* Set a good latency timer and cache line size value. */
490 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
491 /* FIXME: pci_set_master() to ensure a good latency timer value */
494 * Enable interrupts, select MEMORY READ LINE for reads.
496 * NOTE: although not mentioned in the PCI0646U specs,
497 * bits 0-1 are write only and won't be read back as
498 * set or not -- PCI0646U2 specs clarify this point.
500 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
502 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
504 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
506 cmd_devs[n_cmd_devs++] = dev;
510 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
512 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_IDE_PROC_FS */
517 static u8 __devinit ata66_cmd64x(ide_hwif_t *hwif)
519 struct pci_dev *dev = hwif->pci_dev;
520 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
522 switch (dev->device) {
523 case PCI_DEVICE_ID_CMD_648:
524 case PCI_DEVICE_ID_CMD_649:
525 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
526 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
528 return ATA_CBL_PATA40;
532 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
534 struct pci_dev *dev = hwif->pci_dev;
537 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
539 hwif->tuneproc = &cmd64x_tune_drive;
540 hwif->speedproc = &cmd64x_tune_chipset;
542 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
548 hwif->mwdma_mask = 0x07;
549 hwif->ultra_mask = hwif->cds->udma_mask;
552 * UltraDMA only supported on PCI646U and PCI646U2, which
553 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
554 * Actually, although the CMD tech support people won't
555 * tell me the details, the 0x03 revision cannot support
556 * UDMA correctly without hardware modifications, and even
557 * then it only works with Quantum disks due to some
558 * hold time assumptions in the 646U part which are fixed
561 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
563 if (dev->device == PCI_DEVICE_ID_CMD_646 && rev < 5)
564 hwif->ultra_mask = 0x00;
566 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
568 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
569 hwif->cbl = ata66_cmd64x(hwif);
571 switch (dev->device) {
572 case PCI_DEVICE_ID_CMD_648:
573 case PCI_DEVICE_ID_CMD_649:
575 hwif->ide_dma_end = &cmd648_ide_dma_end;
576 hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
578 case PCI_DEVICE_ID_CMD_646:
579 hwif->chipset = ide_cmd646;
581 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
583 } else if (rev >= 0x03)
587 hwif->ide_dma_end = &cmd64x_ide_dma_end;
588 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
594 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
597 static int __devinit init_setup_cmd64x(struct pci_dev *dev, ide_pci_device_t *d)
599 return ide_setup_pci_device(dev, d);
602 static int __devinit init_setup_cmd646(struct pci_dev *dev, ide_pci_device_t *d)
605 * The original PCI0646 didn't have the primary channel enable bit,
606 * it appeared starting with PCI0646U (i.e. revision ID 3).
608 if (dev->revision < 3)
609 d->enablebits[0].reg = 0;
611 return ide_setup_pci_device(dev, d);
614 static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
617 .init_setup = init_setup_cmd64x,
618 .init_chipset = init_chipset_cmd64x,
619 .init_hwif = init_hwif_cmd64x,
621 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
622 .bootable = ON_BOARD,
623 .udma_mask = 0x00, /* no udma */
626 .init_setup = init_setup_cmd646,
627 .init_chipset = init_chipset_cmd64x,
628 .init_hwif = init_hwif_cmd64x,
630 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
631 .bootable = ON_BOARD,
632 .udma_mask = 0x07, /* udma0-2 */
635 .init_setup = init_setup_cmd64x,
636 .init_chipset = init_chipset_cmd64x,
637 .init_hwif = init_hwif_cmd64x,
639 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
640 .bootable = ON_BOARD,
641 .udma_mask = 0x1f, /* udma0-4 */
644 .init_setup = init_setup_cmd64x,
645 .init_chipset = init_chipset_cmd64x,
646 .init_hwif = init_hwif_cmd64x,
648 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
649 .bootable = ON_BOARD,
650 .udma_mask = 0x3f, /* udma0-5 */
655 * We may have to modify enablebits for PCI0646, so we'd better pass
656 * a local copy of the ide_pci_device_t structure down the call chain...
658 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
660 ide_pci_device_t d = cmd64x_chipsets[id->driver_data];
662 return d.init_setup(dev, &d);
665 static struct pci_device_id cmd64x_pci_tbl[] = {
666 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
667 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
668 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
669 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
672 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
674 static struct pci_driver driver = {
675 .name = "CMD64x_IDE",
676 .id_table = cmd64x_pci_tbl,
677 .probe = cmd64x_init_one,
680 static int __init cmd64x_ide_init(void)
682 return ide_pci_register_driver(&driver);
685 module_init(cmd64x_ide_init);
687 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
688 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
689 MODULE_LICENSE("GPL");