2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
10 * Copyright (c) 2014, Intel Corporation.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/gpio/consumer.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/iio/iio.h>
32 #include <linux/iio/sysfs.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/events.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
38 #include <linux/regmap.h>
40 #include "bmc150-accel.h"
42 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
43 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
45 #define BMC150_ACCEL_REG_CHIP_ID 0x00
47 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
48 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
49 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
51 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
52 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
54 #define BMC150_ACCEL_REG_PMU_LPW 0x11
55 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
56 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
58 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
60 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
62 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
63 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
64 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
65 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
67 /* Default BW: 125Hz */
68 #define BMC150_ACCEL_REG_PMU_BW 0x10
69 #define BMC150_ACCEL_DEF_BW 125
71 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
72 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
74 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
75 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
76 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
77 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
79 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
80 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
81 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
82 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
84 #define BMC150_ACCEL_REG_INT_EN_0 0x16
85 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
86 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
87 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
89 #define BMC150_ACCEL_REG_INT_EN_1 0x17
90 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
91 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
92 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
94 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
95 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
97 #define BMC150_ACCEL_REG_INT_5 0x27
98 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
100 #define BMC150_ACCEL_REG_INT_6 0x28
101 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
103 /* Slope duration in terms of number of samples */
104 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
105 /* in terms of multiples of g's/LSB, based on range */
106 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
108 #define BMC150_ACCEL_REG_XOUT_L 0x02
110 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
112 /* Sleep Duration values */
113 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
114 #define BMC150_ACCEL_SLEEP_1_MS 0x06
115 #define BMC150_ACCEL_SLEEP_2_MS 0x07
116 #define BMC150_ACCEL_SLEEP_4_MS 0x08
117 #define BMC150_ACCEL_SLEEP_6_MS 0x09
118 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
119 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
120 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
121 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
122 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
123 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
125 #define BMC150_ACCEL_REG_TEMP 0x08
126 #define BMC150_ACCEL_TEMP_CENTER_VAL 24
128 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
129 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
131 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
132 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
133 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
134 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
135 #define BMC150_ACCEL_FIFO_LENGTH 32
137 enum bmc150_accel_axis {
143 enum bmc150_power_modes {
144 BMC150_ACCEL_SLEEP_MODE_NORMAL,
145 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
146 BMC150_ACCEL_SLEEP_MODE_LPM,
147 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
150 struct bmc150_scale_info {
155 struct bmc150_accel_chip_info {
158 const struct iio_chan_spec *channels;
160 const struct bmc150_scale_info scale_table[4];
163 struct bmc150_accel_interrupt {
164 const struct bmc150_accel_interrupt_info *info;
168 struct bmc150_accel_trigger {
169 struct bmc150_accel_data *data;
170 struct iio_trigger *indio_trig;
171 int (*setup)(struct bmc150_accel_trigger *t, bool state);
176 enum bmc150_accel_interrupt_id {
177 BMC150_ACCEL_INT_DATA_READY,
178 BMC150_ACCEL_INT_ANY_MOTION,
179 BMC150_ACCEL_INT_WATERMARK,
180 BMC150_ACCEL_INTERRUPTS,
183 enum bmc150_accel_trigger_id {
184 BMC150_ACCEL_TRIGGER_DATA_READY,
185 BMC150_ACCEL_TRIGGER_ANY_MOTION,
186 BMC150_ACCEL_TRIGGERS,
189 struct bmc150_accel_data {
190 struct regmap *regmap;
193 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
194 atomic_t active_intr;
195 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
197 u8 fifo_mode, watermark;
204 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
205 const struct bmc150_accel_chip_info *chip_info;
208 static const struct {
212 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
221 static const struct {
224 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
233 static const struct {
236 } bmc150_accel_sleep_value_table[] = { {0, 0},
237 {500, BMC150_ACCEL_SLEEP_500_MICRO},
238 {1000, BMC150_ACCEL_SLEEP_1_MS},
239 {2000, BMC150_ACCEL_SLEEP_2_MS},
240 {4000, BMC150_ACCEL_SLEEP_4_MS},
241 {6000, BMC150_ACCEL_SLEEP_6_MS},
242 {10000, BMC150_ACCEL_SLEEP_10_MS},
243 {25000, BMC150_ACCEL_SLEEP_25_MS},
244 {50000, BMC150_ACCEL_SLEEP_50_MS},
245 {100000, BMC150_ACCEL_SLEEP_100_MS},
246 {500000, BMC150_ACCEL_SLEEP_500_MS},
247 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
249 static const struct regmap_config bmc150_i2c_regmap_conf = {
252 .max_register = 0x3f,
255 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
256 enum bmc150_power_modes mode,
265 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
267 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
270 bmc150_accel_sleep_value_table[i].reg_value;
279 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
280 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
282 dev_dbg(data->dev, "Set Mode bits %x\n", lpw_bits);
284 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
286 dev_err(data->dev, "Error writing reg_pmu_lpw\n");
293 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
299 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
300 if (bmc150_accel_samp_freq_table[i].val == val &&
301 bmc150_accel_samp_freq_table[i].val2 == val2) {
302 ret = regmap_write(data->regmap,
303 BMC150_ACCEL_REG_PMU_BW,
304 bmc150_accel_samp_freq_table[i].bw_bits);
309 bmc150_accel_samp_freq_table[i].bw_bits;
317 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
321 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
324 dev_err(data->dev, "Error writing reg_int_6\n");
328 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
329 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
331 dev_err(data->dev, "Error updating reg_int_5\n");
335 dev_dbg(data->dev, "%s: %x %x\n", __func__, data->slope_thres,
341 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
345 return bmc150_accel_update_slope(t->data);
350 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
355 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
356 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
357 *val = bmc150_accel_samp_freq_table[i].val;
358 *val2 = bmc150_accel_samp_freq_table[i].val2;
359 return IIO_VAL_INT_PLUS_MICRO;
367 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
371 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
372 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
373 return bmc150_accel_sample_upd_time[i].msec;
376 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
379 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
384 ret = pm_runtime_get_sync(data->dev);
386 pm_runtime_mark_last_busy(data->dev);
387 ret = pm_runtime_put_autosuspend(data->dev);
392 "Failed: bmc150_accel_set_power_state for %d\n", on);
394 pm_runtime_put_noidle(data->dev);
402 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
408 static const struct bmc150_accel_interrupt_info {
413 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
414 { /* data ready interrupt */
415 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
416 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
417 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
418 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
420 { /* motion interrupt */
421 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
422 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
423 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
424 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
425 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
426 BMC150_ACCEL_INT_EN_BIT_SLP_Z
428 { /* fifo watermark interrupt */
429 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
430 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
431 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
432 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
436 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
437 struct bmc150_accel_data *data)
441 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
442 data->interrupts[i].info = &bmc150_accel_interrupts[i];
445 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
448 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
449 const struct bmc150_accel_interrupt_info *info = intr->info;
453 if (atomic_inc_return(&intr->users) > 1)
456 if (atomic_dec_return(&intr->users) > 0)
461 * We will expect the enable and disable to do operation in reverse
462 * order. This will happen here anyway, as our resume operation uses
463 * sync mode runtime pm calls. The suspend operation will be delayed
464 * by autosuspend delay.
465 * So the disable operation will still happen in reverse order of
466 * enable operation. When runtime pm is disabled the mode is always on,
467 * so sequence doesn't matter.
469 ret = bmc150_accel_set_power_state(data, state);
473 /* map the interrupt to the appropriate pins */
474 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
475 (state ? info->map_bitmask : 0));
477 dev_err(data->dev, "Error updating reg_int_map\n");
478 goto out_fix_power_state;
481 /* enable/disable the interrupt */
482 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
483 (state ? info->en_bitmask : 0));
485 dev_err(data->dev, "Error updating reg_int_en\n");
486 goto out_fix_power_state;
490 atomic_inc(&data->active_intr);
492 atomic_dec(&data->active_intr);
497 bmc150_accel_set_power_state(data, false);
501 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
505 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
506 if (data->chip_info->scale_table[i].scale == val) {
507 ret = regmap_write(data->regmap,
508 BMC150_ACCEL_REG_PMU_RANGE,
509 data->chip_info->scale_table[i].reg_range);
512 "Error writing pmu_range\n");
516 data->range = data->chip_info->scale_table[i].reg_range;
524 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
529 mutex_lock(&data->mutex);
531 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
533 dev_err(data->dev, "Error reading reg_temp\n");
534 mutex_unlock(&data->mutex);
537 *val = sign_extend32(value, 7);
539 mutex_unlock(&data->mutex);
544 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
545 struct iio_chan_spec const *chan,
549 int axis = chan->scan_index;
552 mutex_lock(&data->mutex);
553 ret = bmc150_accel_set_power_state(data, true);
555 mutex_unlock(&data->mutex);
559 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
560 &raw_val, sizeof(raw_val));
562 dev_err(data->dev, "Error reading axis %d\n", axis);
563 bmc150_accel_set_power_state(data, false);
564 mutex_unlock(&data->mutex);
567 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
568 chan->scan_type.realbits - 1);
569 ret = bmc150_accel_set_power_state(data, false);
570 mutex_unlock(&data->mutex);
577 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
578 struct iio_chan_spec const *chan,
579 int *val, int *val2, long mask)
581 struct bmc150_accel_data *data = iio_priv(indio_dev);
585 case IIO_CHAN_INFO_RAW:
586 switch (chan->type) {
588 return bmc150_accel_get_temp(data, val);
590 if (iio_buffer_enabled(indio_dev))
593 return bmc150_accel_get_axis(data, chan, val);
597 case IIO_CHAN_INFO_OFFSET:
598 if (chan->type == IIO_TEMP) {
599 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
604 case IIO_CHAN_INFO_SCALE:
606 switch (chan->type) {
609 return IIO_VAL_INT_PLUS_MICRO;
613 const struct bmc150_scale_info *si;
614 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
616 for (i = 0; i < st_size; ++i) {
617 si = &data->chip_info->scale_table[i];
618 if (si->reg_range == data->range) {
620 return IIO_VAL_INT_PLUS_MICRO;
628 case IIO_CHAN_INFO_SAMP_FREQ:
629 mutex_lock(&data->mutex);
630 ret = bmc150_accel_get_bw(data, val, val2);
631 mutex_unlock(&data->mutex);
638 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
639 struct iio_chan_spec const *chan,
640 int val, int val2, long mask)
642 struct bmc150_accel_data *data = iio_priv(indio_dev);
646 case IIO_CHAN_INFO_SAMP_FREQ:
647 mutex_lock(&data->mutex);
648 ret = bmc150_accel_set_bw(data, val, val2);
649 mutex_unlock(&data->mutex);
651 case IIO_CHAN_INFO_SCALE:
655 mutex_lock(&data->mutex);
656 ret = bmc150_accel_set_scale(data, val2);
657 mutex_unlock(&data->mutex);
666 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
667 const struct iio_chan_spec *chan,
668 enum iio_event_type type,
669 enum iio_event_direction dir,
670 enum iio_event_info info,
673 struct bmc150_accel_data *data = iio_priv(indio_dev);
677 case IIO_EV_INFO_VALUE:
678 *val = data->slope_thres;
680 case IIO_EV_INFO_PERIOD:
681 *val = data->slope_dur;
690 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
691 const struct iio_chan_spec *chan,
692 enum iio_event_type type,
693 enum iio_event_direction dir,
694 enum iio_event_info info,
697 struct bmc150_accel_data *data = iio_priv(indio_dev);
699 if (data->ev_enable_state)
703 case IIO_EV_INFO_VALUE:
704 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
706 case IIO_EV_INFO_PERIOD:
707 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
716 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
717 const struct iio_chan_spec *chan,
718 enum iio_event_type type,
719 enum iio_event_direction dir)
721 struct bmc150_accel_data *data = iio_priv(indio_dev);
723 return data->ev_enable_state;
726 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
727 const struct iio_chan_spec *chan,
728 enum iio_event_type type,
729 enum iio_event_direction dir,
732 struct bmc150_accel_data *data = iio_priv(indio_dev);
735 if (state == data->ev_enable_state)
738 mutex_lock(&data->mutex);
740 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
743 mutex_unlock(&data->mutex);
747 data->ev_enable_state = state;
748 mutex_unlock(&data->mutex);
753 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
754 struct iio_trigger *trig)
756 struct bmc150_accel_data *data = iio_priv(indio_dev);
759 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
760 if (data->triggers[i].indio_trig == trig)
767 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
768 struct device_attribute *attr,
771 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
772 struct bmc150_accel_data *data = iio_priv(indio_dev);
775 mutex_lock(&data->mutex);
776 wm = data->watermark;
777 mutex_unlock(&data->mutex);
779 return sprintf(buf, "%d\n", wm);
782 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
783 struct device_attribute *attr,
786 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
787 struct bmc150_accel_data *data = iio_priv(indio_dev);
790 mutex_lock(&data->mutex);
791 state = data->fifo_mode;
792 mutex_unlock(&data->mutex);
794 return sprintf(buf, "%d\n", state);
797 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
798 static IIO_CONST_ATTR(hwfifo_watermark_max,
799 __stringify(BMC150_ACCEL_FIFO_LENGTH));
800 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
801 bmc150_accel_get_fifo_state, NULL, 0);
802 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
803 bmc150_accel_get_fifo_watermark, NULL, 0);
805 static const struct attribute *bmc150_accel_fifo_attributes[] = {
806 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
807 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
808 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
809 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
813 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
815 struct bmc150_accel_data *data = iio_priv(indio_dev);
817 if (val > BMC150_ACCEL_FIFO_LENGTH)
818 val = BMC150_ACCEL_FIFO_LENGTH;
820 mutex_lock(&data->mutex);
821 data->watermark = val;
822 mutex_unlock(&data->mutex);
828 * We must read at least one full frame in one burst, otherwise the rest of the
829 * frame data is discarded.
831 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
832 char *buffer, int samples)
834 int sample_length = 3 * 2;
836 int total_length = samples * sample_length;
838 size_t step = regmap_get_raw_read_max(data->regmap);
840 if (!step || step > total_length)
842 else if (step < total_length)
843 step = sample_length;
846 * Seems we have a bus with size limitation so we have to execute
849 for (i = 0; i < total_length; i += step) {
850 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
857 dev_err(data->dev, "Error transferring data from fifo in single steps of %zu\n",
863 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
864 unsigned samples, bool irq)
866 struct bmc150_accel_data *data = iio_priv(indio_dev);
869 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
871 uint64_t sample_period;
874 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
876 dev_err(data->dev, "Error reading reg_fifo_status\n");
886 * If we getting called from IRQ handler we know the stored timestamp is
887 * fairly accurate for the last stored sample. Otherwise, if we are
888 * called as a result of a read operation from userspace and hence
889 * before the watermark interrupt was triggered, take a timestamp
890 * now. We can fall anywhere in between two samples so the error in this
891 * case is at most one sample period.
894 data->old_timestamp = data->timestamp;
895 data->timestamp = iio_get_time_ns();
899 * Approximate timestamps for each of the sample based on the sampling
900 * frequency, timestamp for last sample and number of samples.
902 * Note that we can't use the current bandwidth settings to compute the
903 * sample period because the sample rate varies with the device
904 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
905 * small variation adds when we store a large number of samples and
906 * creates significant jitter between the last and first samples in
907 * different batches (e.g. 32ms vs 21ms).
909 * To avoid this issue we compute the actual sample period ourselves
910 * based on the timestamp delta between the last two flush operations.
912 sample_period = (data->timestamp - data->old_timestamp);
913 do_div(sample_period, count);
914 tstamp = data->timestamp - (count - 1) * sample_period;
916 if (samples && count > samples)
919 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
924 * Ideally we want the IIO core to handle the demux when running in fifo
925 * mode but not when running in triggered buffer mode. Unfortunately
926 * this does not seem to be possible, so stick with driver demux for
929 for (i = 0; i < count; i++) {
934 for_each_set_bit(bit, indio_dev->active_scan_mask,
935 indio_dev->masklength)
936 memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
938 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
940 tstamp += sample_period;
946 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
948 struct bmc150_accel_data *data = iio_priv(indio_dev);
951 mutex_lock(&data->mutex);
952 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
953 mutex_unlock(&data->mutex);
958 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
959 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
961 static struct attribute *bmc150_accel_attributes[] = {
962 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
966 static const struct attribute_group bmc150_accel_attrs_group = {
967 .attrs = bmc150_accel_attributes,
970 static const struct iio_event_spec bmc150_accel_event = {
971 .type = IIO_EV_TYPE_ROC,
972 .dir = IIO_EV_DIR_EITHER,
973 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
974 BIT(IIO_EV_INFO_ENABLE) |
975 BIT(IIO_EV_INFO_PERIOD)
978 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
981 .channel2 = IIO_MOD_##_axis, \
982 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
983 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
984 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
985 .scan_index = AXIS_##_axis, \
988 .realbits = (bits), \
990 .shift = 16 - (bits), \
991 .endianness = IIO_LE, \
993 .event_spec = &bmc150_accel_event, \
994 .num_event_specs = 1 \
997 #define BMC150_ACCEL_CHANNELS(bits) { \
1000 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1001 BIT(IIO_CHAN_INFO_SCALE) | \
1002 BIT(IIO_CHAN_INFO_OFFSET), \
1005 BMC150_ACCEL_CHANNEL(X, bits), \
1006 BMC150_ACCEL_CHANNEL(Y, bits), \
1007 BMC150_ACCEL_CHANNEL(Z, bits), \
1008 IIO_CHAN_SOFT_TIMESTAMP(3), \
1011 static const struct iio_chan_spec bma222e_accel_channels[] =
1012 BMC150_ACCEL_CHANNELS(8);
1013 static const struct iio_chan_spec bma250e_accel_channels[] =
1014 BMC150_ACCEL_CHANNELS(10);
1015 static const struct iio_chan_spec bmc150_accel_channels[] =
1016 BMC150_ACCEL_CHANNELS(12);
1017 static const struct iio_chan_spec bma280_accel_channels[] =
1018 BMC150_ACCEL_CHANNELS(14);
1020 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1024 .channels = bmc150_accel_channels,
1025 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1026 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1027 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1028 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1029 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1034 .channels = bmc150_accel_channels,
1035 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1036 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1037 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1038 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1039 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1044 .channels = bmc150_accel_channels,
1045 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1046 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1047 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1048 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1049 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1054 .channels = bma250e_accel_channels,
1055 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1056 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1057 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1058 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1059 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1064 .channels = bma222e_accel_channels,
1065 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1066 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1067 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1068 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1069 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1074 .channels = bma280_accel_channels,
1075 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1076 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1077 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1078 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1079 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1083 static const struct iio_info bmc150_accel_info = {
1084 .attrs = &bmc150_accel_attrs_group,
1085 .read_raw = bmc150_accel_read_raw,
1086 .write_raw = bmc150_accel_write_raw,
1087 .read_event_value = bmc150_accel_read_event,
1088 .write_event_value = bmc150_accel_write_event,
1089 .write_event_config = bmc150_accel_write_event_config,
1090 .read_event_config = bmc150_accel_read_event_config,
1091 .driver_module = THIS_MODULE,
1094 static const struct iio_info bmc150_accel_info_fifo = {
1095 .attrs = &bmc150_accel_attrs_group,
1096 .read_raw = bmc150_accel_read_raw,
1097 .write_raw = bmc150_accel_write_raw,
1098 .read_event_value = bmc150_accel_read_event,
1099 .write_event_value = bmc150_accel_write_event,
1100 .write_event_config = bmc150_accel_write_event_config,
1101 .read_event_config = bmc150_accel_read_event_config,
1102 .validate_trigger = bmc150_accel_validate_trigger,
1103 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1104 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1105 .driver_module = THIS_MODULE,
1108 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1110 struct iio_poll_func *pf = p;
1111 struct iio_dev *indio_dev = pf->indio_dev;
1112 struct bmc150_accel_data *data = iio_priv(indio_dev);
1113 int bit, ret, i = 0;
1114 unsigned int raw_val;
1116 mutex_lock(&data->mutex);
1117 for_each_set_bit(bit, indio_dev->active_scan_mask,
1118 indio_dev->masklength) {
1119 ret = regmap_bulk_read(data->regmap,
1120 BMC150_ACCEL_AXIS_TO_REG(bit), &raw_val,
1123 mutex_unlock(&data->mutex);
1126 data->buffer[i++] = raw_val;
1128 mutex_unlock(&data->mutex);
1130 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1133 iio_trigger_notify_done(indio_dev->trig);
1138 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1140 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1141 struct bmc150_accel_data *data = t->data;
1144 /* new data interrupts don't need ack */
1145 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1148 mutex_lock(&data->mutex);
1149 /* clear any latched interrupt */
1150 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1151 BMC150_ACCEL_INT_MODE_LATCH_INT |
1152 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1153 mutex_unlock(&data->mutex);
1156 "Error writing reg_int_rst_latch\n");
1163 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1166 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1167 struct bmc150_accel_data *data = t->data;
1170 mutex_lock(&data->mutex);
1172 if (t->enabled == state) {
1173 mutex_unlock(&data->mutex);
1178 ret = t->setup(t, state);
1180 mutex_unlock(&data->mutex);
1185 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1187 mutex_unlock(&data->mutex);
1193 mutex_unlock(&data->mutex);
1198 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1199 .set_trigger_state = bmc150_accel_trigger_set_state,
1200 .try_reenable = bmc150_accel_trig_try_reen,
1201 .owner = THIS_MODULE,
1204 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1206 struct bmc150_accel_data *data = iio_priv(indio_dev);
1211 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1213 dev_err(data->dev, "Error reading reg_int_status_2\n");
1217 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1218 dir = IIO_EV_DIR_FALLING;
1220 dir = IIO_EV_DIR_RISING;
1222 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1223 iio_push_event(indio_dev,
1224 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1231 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1232 iio_push_event(indio_dev,
1233 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1240 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1241 iio_push_event(indio_dev,
1242 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1252 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1254 struct iio_dev *indio_dev = private;
1255 struct bmc150_accel_data *data = iio_priv(indio_dev);
1259 mutex_lock(&data->mutex);
1261 if (data->fifo_mode) {
1262 ret = __bmc150_accel_fifo_flush(indio_dev,
1263 BMC150_ACCEL_FIFO_LENGTH, true);
1268 if (data->ev_enable_state) {
1269 ret = bmc150_accel_handle_roc_event(indio_dev);
1275 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1276 BMC150_ACCEL_INT_MODE_LATCH_INT |
1277 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1279 dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1286 mutex_unlock(&data->mutex);
1291 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1293 struct iio_dev *indio_dev = private;
1294 struct bmc150_accel_data *data = iio_priv(indio_dev);
1298 data->old_timestamp = data->timestamp;
1299 data->timestamp = iio_get_time_ns();
1301 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1302 if (data->triggers[i].enabled) {
1303 iio_trigger_poll(data->triggers[i].indio_trig);
1309 if (data->ev_enable_state || data->fifo_mode)
1310 return IRQ_WAKE_THREAD;
1318 static const struct {
1321 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1322 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1329 .name = "%s-any-motion-dev%d",
1330 .setup = bmc150_accel_any_motion_setup,
1334 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1339 for (i = from; i >= 0; i--) {
1340 if (data->triggers[i].indio_trig) {
1341 iio_trigger_unregister(data->triggers[i].indio_trig);
1342 data->triggers[i].indio_trig = NULL;
1347 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1348 struct bmc150_accel_data *data)
1352 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1353 struct bmc150_accel_trigger *t = &data->triggers[i];
1355 t->indio_trig = devm_iio_trigger_alloc(data->dev,
1356 bmc150_accel_triggers[i].name,
1359 if (!t->indio_trig) {
1364 t->indio_trig->dev.parent = data->dev;
1365 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1366 t->intr = bmc150_accel_triggers[i].intr;
1368 t->setup = bmc150_accel_triggers[i].setup;
1369 iio_trigger_set_drvdata(t->indio_trig, t);
1371 ret = iio_trigger_register(t->indio_trig);
1377 bmc150_accel_unregister_triggers(data, i - 1);
1382 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1383 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1384 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1386 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1388 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1391 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1393 dev_err(data->dev, "Error writing reg_fifo_config1\n");
1397 if (!data->fifo_mode)
1400 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1403 dev_err(data->dev, "Error writing reg_fifo_config0\n");
1408 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1410 struct bmc150_accel_data *data = iio_priv(indio_dev);
1412 return bmc150_accel_set_power_state(data, true);
1415 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1417 struct bmc150_accel_data *data = iio_priv(indio_dev);
1420 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1421 return iio_triggered_buffer_postenable(indio_dev);
1423 mutex_lock(&data->mutex);
1425 if (!data->watermark)
1428 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1433 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1435 ret = bmc150_accel_fifo_set_mode(data);
1437 data->fifo_mode = 0;
1438 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1443 mutex_unlock(&data->mutex);
1448 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1450 struct bmc150_accel_data *data = iio_priv(indio_dev);
1452 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1453 return iio_triggered_buffer_predisable(indio_dev);
1455 mutex_lock(&data->mutex);
1457 if (!data->fifo_mode)
1460 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1461 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1462 data->fifo_mode = 0;
1463 bmc150_accel_fifo_set_mode(data);
1466 mutex_unlock(&data->mutex);
1471 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1473 struct bmc150_accel_data *data = iio_priv(indio_dev);
1475 return bmc150_accel_set_power_state(data, false);
1478 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1479 .preenable = bmc150_accel_buffer_preenable,
1480 .postenable = bmc150_accel_buffer_postenable,
1481 .predisable = bmc150_accel_buffer_predisable,
1482 .postdisable = bmc150_accel_buffer_postdisable,
1485 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1490 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1493 "Error: Reading chip id\n");
1497 dev_dbg(data->dev, "Chip Id %x\n", val);
1498 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1499 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1500 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1505 if (!data->chip_info) {
1506 dev_err(data->dev, "Invalid chip %x\n", val);
1510 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1515 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1519 /* Set Default Range */
1520 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1521 BMC150_ACCEL_DEF_RANGE_4G);
1524 "Error writing reg_pmu_range\n");
1528 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1530 /* Set default slope duration and thresholds */
1531 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1532 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1533 ret = bmc150_accel_update_slope(data);
1537 /* Set default as latched interrupts */
1538 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1539 BMC150_ACCEL_INT_MODE_LATCH_INT |
1540 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1543 "Error writing reg_int_rst_latch\n");
1550 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1551 const char *name, bool block_supported)
1553 struct bmc150_accel_data *data;
1554 struct iio_dev *indio_dev;
1557 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1561 data = iio_priv(indio_dev);
1562 dev_set_drvdata(dev, indio_dev);
1566 data->regmap = regmap;
1568 ret = bmc150_accel_chip_init(data);
1572 mutex_init(&data->mutex);
1574 indio_dev->dev.parent = dev;
1575 indio_dev->channels = data->chip_info->channels;
1576 indio_dev->num_channels = data->chip_info->num_channels;
1577 indio_dev->name = name ? name : data->chip_info->name;
1578 indio_dev->modes = INDIO_DIRECT_MODE;
1579 indio_dev->info = &bmc150_accel_info;
1581 ret = iio_triggered_buffer_setup(indio_dev,
1582 &iio_pollfunc_store_time,
1583 bmc150_accel_trigger_handler,
1584 &bmc150_accel_buffer_ops);
1586 dev_err(data->dev, "Failed: iio triggered buffer setup\n");
1590 if (data->irq > 0) {
1591 ret = devm_request_threaded_irq(
1592 data->dev, data->irq,
1593 bmc150_accel_irq_handler,
1594 bmc150_accel_irq_thread_handler,
1595 IRQF_TRIGGER_RISING,
1596 BMC150_ACCEL_IRQ_NAME,
1599 goto err_buffer_cleanup;
1602 * Set latched mode interrupt. While certain interrupts are
1603 * non-latched regardless of this settings (e.g. new data) we
1604 * want to use latch mode when we can to prevent interrupt
1607 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1608 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1610 dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1611 goto err_buffer_cleanup;
1614 bmc150_accel_interrupts_setup(indio_dev, data);
1616 ret = bmc150_accel_triggers_setup(indio_dev, data);
1618 goto err_buffer_cleanup;
1620 if (block_supported) {
1621 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1622 indio_dev->info = &bmc150_accel_info_fifo;
1623 indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1627 ret = pm_runtime_set_active(dev);
1629 goto err_trigger_unregister;
1631 pm_runtime_enable(dev);
1632 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1633 pm_runtime_use_autosuspend(dev);
1635 ret = iio_device_register(indio_dev);
1637 dev_err(dev, "Unable to register iio device\n");
1638 goto err_trigger_unregister;
1643 err_trigger_unregister:
1644 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1646 iio_triggered_buffer_cleanup(indio_dev);
1650 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1652 int bmc150_accel_core_remove(struct device *dev)
1654 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1655 struct bmc150_accel_data *data = iio_priv(indio_dev);
1657 iio_device_unregister(indio_dev);
1659 pm_runtime_disable(data->dev);
1660 pm_runtime_set_suspended(data->dev);
1661 pm_runtime_put_noidle(data->dev);
1663 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1665 iio_triggered_buffer_cleanup(indio_dev);
1667 mutex_lock(&data->mutex);
1668 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1669 mutex_unlock(&data->mutex);
1673 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1675 #ifdef CONFIG_PM_SLEEP
1676 static int bmc150_accel_suspend(struct device *dev)
1678 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1679 struct bmc150_accel_data *data = iio_priv(indio_dev);
1681 mutex_lock(&data->mutex);
1682 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1683 mutex_unlock(&data->mutex);
1688 static int bmc150_accel_resume(struct device *dev)
1690 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1691 struct bmc150_accel_data *data = iio_priv(indio_dev);
1693 mutex_lock(&data->mutex);
1694 if (atomic_read(&data->active_intr))
1695 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1696 bmc150_accel_fifo_set_mode(data);
1697 mutex_unlock(&data->mutex);
1704 static int bmc150_accel_runtime_suspend(struct device *dev)
1706 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1707 struct bmc150_accel_data *data = iio_priv(indio_dev);
1710 dev_dbg(data->dev, __func__);
1711 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1718 static int bmc150_accel_runtime_resume(struct device *dev)
1720 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1721 struct bmc150_accel_data *data = iio_priv(indio_dev);
1725 dev_dbg(data->dev, __func__);
1727 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1730 ret = bmc150_accel_fifo_set_mode(data);
1734 sleep_val = bmc150_accel_get_startup_times(data);
1736 usleep_range(sleep_val * 1000, 20000);
1738 msleep_interruptible(sleep_val);
1744 const struct dev_pm_ops bmc150_accel_pm_ops = {
1745 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1746 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1747 bmc150_accel_runtime_resume, NULL)
1749 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1751 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1752 MODULE_LICENSE("GPL v2");
1753 MODULE_DESCRIPTION("BMC150 accelerometer driver");