2 * Freescale Vybrid vf610 ADC driver
4 * Copyright 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/completion.h>
31 #include <linux/of_irq.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/of_platform.h>
34 #include <linux/err.h>
36 #include <linux/iio/iio.h>
37 #include <linux/iio/sysfs.h>
38 #include <linux/iio/driver.h>
40 /* This will be the driver name the kernel reports */
41 #define DRIVER_NAME "vf610-adc"
43 /* Vybrid/IMX ADC registers */
44 #define VF610_REG_ADC_HC0 0x00
45 #define VF610_REG_ADC_HC1 0x04
46 #define VF610_REG_ADC_HS 0x08
47 #define VF610_REG_ADC_R0 0x0c
48 #define VF610_REG_ADC_R1 0x10
49 #define VF610_REG_ADC_CFG 0x14
50 #define VF610_REG_ADC_GC 0x18
51 #define VF610_REG_ADC_GS 0x1c
52 #define VF610_REG_ADC_CV 0x20
53 #define VF610_REG_ADC_OFS 0x24
54 #define VF610_REG_ADC_CAL 0x28
55 #define VF610_REG_ADC_PCTL 0x30
57 /* Configuration register field define */
58 #define VF610_ADC_MODE_BIT8 0x00
59 #define VF610_ADC_MODE_BIT10 0x04
60 #define VF610_ADC_MODE_BIT12 0x08
61 #define VF610_ADC_MODE_MASK 0x0c
62 #define VF610_ADC_BUSCLK2_SEL 0x01
63 #define VF610_ADC_ALTCLK_SEL 0x02
64 #define VF610_ADC_ADACK_SEL 0x03
65 #define VF610_ADC_ADCCLK_MASK 0x03
66 #define VF610_ADC_CLK_DIV2 0x20
67 #define VF610_ADC_CLK_DIV4 0x40
68 #define VF610_ADC_CLK_DIV8 0x60
69 #define VF610_ADC_CLK_MASK 0x60
70 #define VF610_ADC_ADLSMP_LONG 0x10
71 #define VF610_ADC_ADSTS_SHORT 0x100
72 #define VF610_ADC_ADSTS_NORMAL 0x200
73 #define VF610_ADC_ADSTS_LONG 0x300
74 #define VF610_ADC_ADSTS_MASK 0x300
75 #define VF610_ADC_ADLPC_EN 0x80
76 #define VF610_ADC_ADHSC_EN 0x400
77 #define VF610_ADC_REFSEL_VALT 0x100
78 #define VF610_ADC_REFSEL_VBG 0x1000
79 #define VF610_ADC_ADTRG_HARD 0x2000
80 #define VF610_ADC_AVGS_8 0x4000
81 #define VF610_ADC_AVGS_16 0x8000
82 #define VF610_ADC_AVGS_32 0xC000
83 #define VF610_ADC_AVGS_MASK 0xC000
84 #define VF610_ADC_OVWREN 0x10000
86 /* General control register field define */
87 #define VF610_ADC_ADACKEN 0x1
88 #define VF610_ADC_DMAEN 0x2
89 #define VF610_ADC_ACREN 0x4
90 #define VF610_ADC_ACFGT 0x8
91 #define VF610_ADC_ACFE 0x10
92 #define VF610_ADC_AVGEN 0x20
93 #define VF610_ADC_ADCON 0x40
94 #define VF610_ADC_CAL 0x80
96 /* Other field define */
97 #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
98 #define VF610_ADC_AIEN (0x1 << 7)
99 #define VF610_ADC_CONV_DISABLE 0x1F
100 #define VF610_ADC_HS_COCO0 0x1
101 #define VF610_ADC_CALF 0x2
102 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
104 #define DEFAULT_SAMPLE_TIME 1000
107 VF610_ADCIOC_BUSCLK_SET,
108 VF610_ADCIOC_ALTCLK_SET,
109 VF610_ADCIOC_ADACK_SET,
113 VF610_ADCIOC_VR_VREF_SET,
114 VF610_ADCIOC_VR_VALT_SET,
115 VF610_ADCIOC_VR_VBG_SET,
126 enum conversion_mode_sel {
127 VF610_ADC_CONV_NORMAL,
128 VF610_ADC_CONV_HIGH_SPEED,
129 VF610_ADC_CONV_LOW_POWER,
137 VF610_ADCK_CYCLES_13,
138 VF610_ADCK_CYCLES_17,
139 VF610_ADCK_CYCLES_21,
140 VF610_ADCK_CYCLES_25,
143 struct vf610_adc_feature {
144 enum clk_sel clk_sel;
145 enum vol_ref vol_ref;
146 enum conversion_mode_sel conv_mode;
152 u32 default_sample_time;
165 struct regulator *vref;
167 u32 max_adck_rate[3];
168 struct vf610_adc_feature adc_feature;
170 u32 sample_freq_avail[5];
172 struct completion completion;
175 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
176 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
178 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
180 struct vf610_adc_feature *adc_feature = &info->adc_feature;
181 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
182 u32 adck_period, lst_addr_min;
185 adck_rate = info->max_adck_rate[adc_feature->conv_mode];
188 /* calculate clk divider which is within specification */
189 divisor = ipg_rate / adck_rate;
190 adc_feature->clk_div = 1 << fls(divisor + 1);
192 /* fall-back value using a safe divisor */
193 adc_feature->clk_div = 8;
197 * Determine the long sample time adder value to be used based
198 * on the default minimum sample time provided.
200 adck_period = NSEC_PER_SEC / adck_rate;
201 lst_addr_min = adc_feature->default_sample_time / adck_period;
202 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
203 if (vf610_lst_adder[i] > lst_addr_min) {
204 adc_feature->lst_adder_index = i;
210 * Calculate ADC sample frequencies
211 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
212 * which is the same as bus clock.
214 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
215 * SFCAdder: fixed to 6 ADCK cycles
216 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
217 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
218 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
220 adck_rate = ipg_rate / info->adc_feature.clk_div;
221 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
222 info->sample_freq_avail[i] =
223 adck_rate / (6 + vf610_hw_avgs[i] *
224 (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
227 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
229 struct vf610_adc_feature *adc_feature = &info->adc_feature;
231 /* set default Configuration for ADC controller */
232 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
233 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
235 adc_feature->calibration = true;
236 adc_feature->ovwren = true;
238 adc_feature->res_mode = 12;
239 adc_feature->sample_rate = 1;
241 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
243 vf610_adc_calculate_rates(info);
246 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
248 struct vf610_adc_feature *adc_feature = &info->adc_feature;
252 switch (adc_feature->clk_sel) {
253 case VF610_ADCIOC_ALTCLK_SET:
254 cfg_data |= VF610_ADC_ALTCLK_SEL;
256 case VF610_ADCIOC_ADACK_SET:
257 cfg_data |= VF610_ADC_ADACK_SEL;
263 /* low power set for calibration */
264 cfg_data |= VF610_ADC_ADLPC_EN;
266 /* enable high speed for calibration */
267 cfg_data |= VF610_ADC_ADHSC_EN;
269 /* voltage reference */
270 switch (adc_feature->vol_ref) {
271 case VF610_ADCIOC_VR_VREF_SET:
273 case VF610_ADCIOC_VR_VALT_SET:
274 cfg_data |= VF610_ADC_REFSEL_VALT;
276 case VF610_ADCIOC_VR_VBG_SET:
277 cfg_data |= VF610_ADC_REFSEL_VBG;
280 dev_err(info->dev, "error voltage reference\n");
283 /* data overwrite enable */
284 if (adc_feature->ovwren)
285 cfg_data |= VF610_ADC_OVWREN;
287 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
288 writel(gc_data, info->regs + VF610_REG_ADC_GC);
291 static void vf610_adc_calibration(struct vf610_adc *info)
295 if (!info->adc_feature.calibration)
298 /* enable calibration interrupt */
299 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
300 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
302 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
303 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
305 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
306 dev_err(info->dev, "Timeout for adc calibration\n");
308 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
309 if (adc_gc & VF610_ADC_CALF)
310 dev_err(info->dev, "ADC calibration failed\n");
312 info->adc_feature.calibration = false;
315 static void vf610_adc_cfg_set(struct vf610_adc *info)
317 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
320 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
322 cfg_data &= ~VF610_ADC_ADLPC_EN;
323 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
324 cfg_data |= VF610_ADC_ADLPC_EN;
326 cfg_data &= ~VF610_ADC_ADHSC_EN;
327 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
328 cfg_data |= VF610_ADC_ADHSC_EN;
330 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
333 static void vf610_adc_sample_set(struct vf610_adc *info)
335 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
336 int cfg_data, gc_data;
338 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
339 gc_data = readl(info->regs + VF610_REG_ADC_GC);
341 /* resolution mode */
342 cfg_data &= ~VF610_ADC_MODE_MASK;
343 switch (adc_feature->res_mode) {
345 cfg_data |= VF610_ADC_MODE_BIT8;
348 cfg_data |= VF610_ADC_MODE_BIT10;
351 cfg_data |= VF610_ADC_MODE_BIT12;
354 dev_err(info->dev, "error resolution mode\n");
358 /* clock select and clock divider */
359 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
360 switch (adc_feature->clk_div) {
364 cfg_data |= VF610_ADC_CLK_DIV2;
367 cfg_data |= VF610_ADC_CLK_DIV4;
370 cfg_data |= VF610_ADC_CLK_DIV8;
373 switch (adc_feature->clk_sel) {
374 case VF610_ADCIOC_BUSCLK_SET:
375 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
378 dev_err(info->dev, "error clk divider\n");
385 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
388 switch (adc_feature->lst_adder_index) {
389 case VF610_ADCK_CYCLES_3:
391 case VF610_ADCK_CYCLES_5:
392 cfg_data |= VF610_ADC_ADSTS_SHORT;
394 case VF610_ADCK_CYCLES_7:
395 cfg_data |= VF610_ADC_ADSTS_NORMAL;
397 case VF610_ADCK_CYCLES_9:
398 cfg_data |= VF610_ADC_ADSTS_LONG;
400 case VF610_ADCK_CYCLES_13:
401 cfg_data |= VF610_ADC_ADLSMP_LONG;
403 case VF610_ADCK_CYCLES_17:
404 cfg_data |= VF610_ADC_ADLSMP_LONG;
405 cfg_data |= VF610_ADC_ADSTS_SHORT;
407 case VF610_ADCK_CYCLES_21:
408 cfg_data |= VF610_ADC_ADLSMP_LONG;
409 cfg_data |= VF610_ADC_ADSTS_NORMAL;
411 case VF610_ADCK_CYCLES_25:
412 cfg_data |= VF610_ADC_ADLSMP_LONG;
413 cfg_data |= VF610_ADC_ADSTS_NORMAL;
416 dev_err(info->dev, "error in sample time select\n");
419 /* update hardware average selection */
420 cfg_data &= ~VF610_ADC_AVGS_MASK;
421 gc_data &= ~VF610_ADC_AVGEN;
422 switch (adc_feature->sample_rate) {
423 case VF610_ADC_SAMPLE_1:
425 case VF610_ADC_SAMPLE_4:
426 gc_data |= VF610_ADC_AVGEN;
428 case VF610_ADC_SAMPLE_8:
429 gc_data |= VF610_ADC_AVGEN;
430 cfg_data |= VF610_ADC_AVGS_8;
432 case VF610_ADC_SAMPLE_16:
433 gc_data |= VF610_ADC_AVGEN;
434 cfg_data |= VF610_ADC_AVGS_16;
436 case VF610_ADC_SAMPLE_32:
437 gc_data |= VF610_ADC_AVGEN;
438 cfg_data |= VF610_ADC_AVGS_32;
442 "error hardware sample average select\n");
445 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
446 writel(gc_data, info->regs + VF610_REG_ADC_GC);
449 static void vf610_adc_hw_init(struct vf610_adc *info)
451 /* CFG: Feature set */
452 vf610_adc_cfg_post_set(info);
453 vf610_adc_sample_set(info);
455 /* adc calibration */
456 vf610_adc_calibration(info);
458 /* CFG: power and speed set */
459 vf610_adc_cfg_set(info);
462 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
463 const struct iio_chan_spec *chan,
466 struct vf610_adc *info = iio_priv(indio_dev);
468 mutex_lock(&indio_dev->mlock);
469 info->adc_feature.conv_mode = mode;
470 vf610_adc_calculate_rates(info);
471 vf610_adc_hw_init(info);
472 mutex_unlock(&indio_dev->mlock);
477 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
478 const struct iio_chan_spec *chan)
480 struct vf610_adc *info = iio_priv(indio_dev);
482 return info->adc_feature.conv_mode;
485 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
488 static const struct iio_enum vf610_conversion_mode = {
489 .items = vf610_conv_modes,
490 .num_items = ARRAY_SIZE(vf610_conv_modes),
491 .get = vf610_get_conversion_mode,
492 .set = vf610_set_conversion_mode,
495 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
496 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
500 #define VF610_ADC_CHAN(_idx, _chan_type) { \
501 .type = (_chan_type), \
504 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
505 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
506 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
507 .ext_info = vf610_ext_info, \
510 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
511 .type = (_chan_type), \
513 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
516 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
517 VF610_ADC_CHAN(0, IIO_VOLTAGE),
518 VF610_ADC_CHAN(1, IIO_VOLTAGE),
519 VF610_ADC_CHAN(2, IIO_VOLTAGE),
520 VF610_ADC_CHAN(3, IIO_VOLTAGE),
521 VF610_ADC_CHAN(4, IIO_VOLTAGE),
522 VF610_ADC_CHAN(5, IIO_VOLTAGE),
523 VF610_ADC_CHAN(6, IIO_VOLTAGE),
524 VF610_ADC_CHAN(7, IIO_VOLTAGE),
525 VF610_ADC_CHAN(8, IIO_VOLTAGE),
526 VF610_ADC_CHAN(9, IIO_VOLTAGE),
527 VF610_ADC_CHAN(10, IIO_VOLTAGE),
528 VF610_ADC_CHAN(11, IIO_VOLTAGE),
529 VF610_ADC_CHAN(12, IIO_VOLTAGE),
530 VF610_ADC_CHAN(13, IIO_VOLTAGE),
531 VF610_ADC_CHAN(14, IIO_VOLTAGE),
532 VF610_ADC_CHAN(15, IIO_VOLTAGE),
533 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
537 static int vf610_adc_read_data(struct vf610_adc *info)
541 result = readl(info->regs + VF610_REG_ADC_R0);
543 switch (info->adc_feature.res_mode) {
560 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
562 struct vf610_adc *info = (struct vf610_adc *)dev_id;
565 coco = readl(info->regs + VF610_REG_ADC_HS);
566 if (coco & VF610_ADC_HS_COCO0) {
567 info->value = vf610_adc_read_data(info);
568 complete(&info->completion);
574 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
575 struct device_attribute *attr, char *buf)
577 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
581 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
582 len += scnprintf(buf + len, PAGE_SIZE - len,
583 "%u ", info->sample_freq_avail[i]);
585 /* replace trailing space by newline */
591 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
593 static struct attribute *vf610_attributes[] = {
594 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
598 static const struct attribute_group vf610_attribute_group = {
599 .attrs = vf610_attributes,
602 static int vf610_read_raw(struct iio_dev *indio_dev,
603 struct iio_chan_spec const *chan,
608 struct vf610_adc *info = iio_priv(indio_dev);
613 case IIO_CHAN_INFO_RAW:
614 case IIO_CHAN_INFO_PROCESSED:
615 mutex_lock(&indio_dev->mlock);
616 reinit_completion(&info->completion);
618 hc_cfg = VF610_ADC_ADCHC(chan->channel);
619 hc_cfg |= VF610_ADC_AIEN;
620 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
621 ret = wait_for_completion_interruptible_timeout
622 (&info->completion, VF610_ADC_TIMEOUT);
624 mutex_unlock(&indio_dev->mlock);
628 mutex_unlock(&indio_dev->mlock);
632 switch (chan->type) {
638 * Calculate in degree Celsius times 1000
639 * Using sensor slope of 1.84 mV/°C and
640 * V at 25°C of 696 mV
642 *val = 25000 - ((int)info->value - 864) * 1000000 / 1840;
645 mutex_unlock(&indio_dev->mlock);
649 mutex_unlock(&indio_dev->mlock);
652 case IIO_CHAN_INFO_SCALE:
653 *val = info->vref_uv / 1000;
654 *val2 = info->adc_feature.res_mode;
655 return IIO_VAL_FRACTIONAL_LOG2;
657 case IIO_CHAN_INFO_SAMP_FREQ:
658 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
669 static int vf610_write_raw(struct iio_dev *indio_dev,
670 struct iio_chan_spec const *chan,
675 struct vf610_adc *info = iio_priv(indio_dev);
679 case IIO_CHAN_INFO_SAMP_FREQ:
681 i < ARRAY_SIZE(info->sample_freq_avail);
683 if (val == info->sample_freq_avail[i]) {
684 info->adc_feature.sample_rate = i;
685 vf610_adc_sample_set(info);
697 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
698 unsigned reg, unsigned writeval,
701 struct vf610_adc *info = iio_priv(indio_dev);
703 if ((readval == NULL) ||
704 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
707 *readval = readl(info->regs + reg);
712 static const struct iio_info vf610_adc_iio_info = {
713 .driver_module = THIS_MODULE,
714 .read_raw = &vf610_read_raw,
715 .write_raw = &vf610_write_raw,
716 .debugfs_reg_access = &vf610_adc_reg_access,
717 .attrs = &vf610_attribute_group,
720 static const struct of_device_id vf610_adc_match[] = {
721 { .compatible = "fsl,vf610-adc", },
724 MODULE_DEVICE_TABLE(of, vf610_adc_match);
726 static int vf610_adc_probe(struct platform_device *pdev)
728 struct vf610_adc *info;
729 struct iio_dev *indio_dev;
730 struct resource *mem;
734 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
736 dev_err(&pdev->dev, "Failed allocating iio device\n");
740 info = iio_priv(indio_dev);
741 info->dev = &pdev->dev;
743 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
744 info->regs = devm_ioremap_resource(&pdev->dev, mem);
745 if (IS_ERR(info->regs))
746 return PTR_ERR(info->regs);
748 irq = platform_get_irq(pdev, 0);
750 dev_err(&pdev->dev, "no irq resource?\n");
754 ret = devm_request_irq(info->dev, irq,
756 dev_name(&pdev->dev), info);
758 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
762 info->clk = devm_clk_get(&pdev->dev, "adc");
763 if (IS_ERR(info->clk)) {
764 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
766 return PTR_ERR(info->clk);
769 info->vref = devm_regulator_get(&pdev->dev, "vref");
770 if (IS_ERR(info->vref))
771 return PTR_ERR(info->vref);
773 ret = regulator_enable(info->vref);
777 info->vref_uv = regulator_get_voltage(info->vref);
779 of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
780 info->max_adck_rate, 3);
782 ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
783 &info->adc_feature.default_sample_time);
785 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
787 platform_set_drvdata(pdev, indio_dev);
789 init_completion(&info->completion);
791 indio_dev->name = dev_name(&pdev->dev);
792 indio_dev->dev.parent = &pdev->dev;
793 indio_dev->dev.of_node = pdev->dev.of_node;
794 indio_dev->info = &vf610_adc_iio_info;
795 indio_dev->modes = INDIO_DIRECT_MODE;
796 indio_dev->channels = vf610_adc_iio_channels;
797 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
799 ret = clk_prepare_enable(info->clk);
802 "Could not prepare or enable the clock.\n");
803 goto error_adc_clk_enable;
806 vf610_adc_cfg_init(info);
807 vf610_adc_hw_init(info);
809 ret = iio_device_register(indio_dev);
811 dev_err(&pdev->dev, "Couldn't register the device.\n");
812 goto error_iio_device_register;
818 error_iio_device_register:
819 clk_disable_unprepare(info->clk);
820 error_adc_clk_enable:
821 regulator_disable(info->vref);
826 static int vf610_adc_remove(struct platform_device *pdev)
828 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
829 struct vf610_adc *info = iio_priv(indio_dev);
831 iio_device_unregister(indio_dev);
832 regulator_disable(info->vref);
833 clk_disable_unprepare(info->clk);
838 #ifdef CONFIG_PM_SLEEP
839 static int vf610_adc_suspend(struct device *dev)
841 struct iio_dev *indio_dev = dev_get_drvdata(dev);
842 struct vf610_adc *info = iio_priv(indio_dev);
845 /* ADC controller enters to stop mode */
846 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
847 hc_cfg |= VF610_ADC_CONV_DISABLE;
848 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
850 clk_disable_unprepare(info->clk);
851 regulator_disable(info->vref);
856 static int vf610_adc_resume(struct device *dev)
858 struct iio_dev *indio_dev = dev_get_drvdata(dev);
859 struct vf610_adc *info = iio_priv(indio_dev);
862 ret = regulator_enable(info->vref);
866 ret = clk_prepare_enable(info->clk);
870 vf610_adc_hw_init(info);
875 regulator_disable(info->vref);
880 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
882 static struct platform_driver vf610_adc_driver = {
883 .probe = vf610_adc_probe,
884 .remove = vf610_adc_remove,
887 .of_match_table = vf610_adc_match,
888 .pm = &vf610_adc_pm_ops,
892 module_platform_driver(vf610_adc_driver);
894 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
895 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
896 MODULE_LICENSE("GPL v2");