drivers/infiniband/hw/hns/hns_roce_hw_v1.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/platform_device.h>
  34 #include <linux/acpi.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/of.h>
  37 #include <rdma/ib_umem.h>
  38 #include "hns_roce_common.h"
  39 #include "hns_roce_device.h"
  40 #include "hns_roce_cmd.h"
  41 #include "hns_roce_hem.h"
  42 #include "hns_roce_hw_v1.h"
  43
  44 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
  45 {
  46         dseg->lkey = cpu_to_le32(sg->lkey);
  47         dseg->addr = cpu_to_le64(sg->addr);
  48         dseg->len  = cpu_to_le32(sg->length);
  49 }
  50
  51 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
  52                           u32 rkey)
  53 {
  54         rseg->raddr = cpu_to_le64(remote_addr);
  55         rseg->rkey  = cpu_to_le32(rkey);
  56         rseg->len   = 0;
  57 }
  58
  59 int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  60                           struct ib_send_wr **bad_wr)
  61 {
  62         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  63         struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
  64         struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
  65         struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
  66         struct hns_roce_wqe_data_seg *dseg = NULL;
  67         struct hns_roce_qp *qp = to_hr_qp(ibqp);
  68         struct device *dev = &hr_dev->pdev->dev;
  69         struct hns_roce_sq_db sq_db;
  70         int ps_opcode = 0, i = 0;
  71         unsigned long flags = 0;
  72         void *wqe = NULL;
  73         u32 doorbell[2];
  74         int nreq = 0;
  75         u32 ind = 0;
  76         int ret = 0;
  77         u8 *smac;
  78         int loopback;
  79
  80         if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
  81                 ibqp->qp_type != IB_QPT_RC)) {
  82                 dev_err(dev, "un-supported QP type\n");
  83                 *bad_wr = NULL;
  84                 return -EOPNOTSUPP;
  85         }
  86
  87         spin_lock_irqsave(&qp->sq.lock, flags);
  88         ind = qp->sq_next_wqe;
  89         for (nreq = 0; wr; ++nreq, wr = wr->next) {
  90                 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
  91                         ret = -ENOMEM;
  92                         *bad_wr = wr;
  93                         goto out;
  94                 }
  95
  96                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
  97                         dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
  98                                 wr->num_sge, qp->sq.max_gs);
  99                         ret = -EINVAL;
 100                         *bad_wr = wr;
 101                         goto out;
 102                 }
 103
 104                 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 105                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
 106                                                                       wr->wr_id;
 107
 108                 /* Corresponding to the RC and RD type wqe process separately */
 109                 if (ibqp->qp_type == IB_QPT_GSI) {
 110                         ud_sq_wqe = wqe;
 111                         roce_set_field(ud_sq_wqe->dmac_h,
 112                                        UD_SEND_WQE_U32_4_DMAC_0_M,
 113                                        UD_SEND_WQE_U32_4_DMAC_0_S,
 114                                        ah->av.mac[0]);
 115                         roce_set_field(ud_sq_wqe->dmac_h,
 116                                        UD_SEND_WQE_U32_4_DMAC_1_M,
 117                                        UD_SEND_WQE_U32_4_DMAC_1_S,
 118                                        ah->av.mac[1]);
 119                         roce_set_field(ud_sq_wqe->dmac_h,
 120                                        UD_SEND_WQE_U32_4_DMAC_2_M,
 121                                        UD_SEND_WQE_U32_4_DMAC_2_S,
 122                                        ah->av.mac[2]);
 123                         roce_set_field(ud_sq_wqe->dmac_h,
 124                                        UD_SEND_WQE_U32_4_DMAC_3_M,
 125                                        UD_SEND_WQE_U32_4_DMAC_3_S,
 126                                        ah->av.mac[3]);
 127
 128                         roce_set_field(ud_sq_wqe->u32_8,
 129                                        UD_SEND_WQE_U32_8_DMAC_4_M,
 130                                        UD_SEND_WQE_U32_8_DMAC_4_S,
 131                                        ah->av.mac[4]);
 132                         roce_set_field(ud_sq_wqe->u32_8,
 133                                        UD_SEND_WQE_U32_8_DMAC_5_M,
 134                                        UD_SEND_WQE_U32_8_DMAC_5_S,
 135                                        ah->av.mac[5]);
 136
 137                         smac = (u8 *)hr_dev->dev_addr[qp->port];
 138                         loopback = ether_addr_equal_unaligned(ah->av.mac,
 139                                                               smac) ? 1 : 0;
 140                         roce_set_bit(ud_sq_wqe->u32_8,
 141                                      UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
 142                                      loopback);
 143
 144                         roce_set_field(ud_sq_wqe->u32_8,
 145                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
 146                                        UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
 147                                        HNS_ROCE_WQE_OPCODE_SEND);
 148                         roce_set_field(ud_sq_wqe->u32_8,
 149                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
 150                                        UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
 151                                        2);
 152                         roce_set_bit(ud_sq_wqe->u32_8,
 153                                 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
 154                                 1);
 155
 156                         ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
 157                                 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 158                                 (wr->send_flags & IB_SEND_SOLICITED ?
 159                                 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 160                                 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
 161                                 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
 162
 163                         roce_set_field(ud_sq_wqe->u32_16,
 164                                        UD_SEND_WQE_U32_16_DEST_QP_M,
 165                                        UD_SEND_WQE_U32_16_DEST_QP_S,
 166                                        ud_wr(wr)->remote_qpn);
 167                         roce_set_field(ud_sq_wqe->u32_16,
 168                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
 169                                        UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
 170                                        ah->av.stat_rate);
 171
 172                         roce_set_field(ud_sq_wqe->u32_36,
 173                                        UD_SEND_WQE_U32_36_FLOW_LABEL_M,
 174                                        UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0);
 175                         roce_set_field(ud_sq_wqe->u32_36,
 176                                        UD_SEND_WQE_U32_36_PRIORITY_M,
 177                                        UD_SEND_WQE_U32_36_PRIORITY_S,
 178                                        ah->av.sl_tclass_flowlabel >>
 179                                        HNS_ROCE_SL_SHIFT);
 180                         roce_set_field(ud_sq_wqe->u32_36,
 181                                        UD_SEND_WQE_U32_36_SGID_INDEX_M,
 182                                        UD_SEND_WQE_U32_36_SGID_INDEX_S,
 183                                        hns_get_gid_index(hr_dev, qp->phy_port,
 184                                                          ah->av.gid_index));
 185
 186                         roce_set_field(ud_sq_wqe->u32_40,
 187                                        UD_SEND_WQE_U32_40_HOP_LIMIT_M,
 188                                        UD_SEND_WQE_U32_40_HOP_LIMIT_S,
 189                                        ah->av.hop_limit);
 190                         roce_set_field(ud_sq_wqe->u32_40,
 191                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
 192                                        UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S, 0);
 193
 194                         memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
 195
 196                         ud_sq_wqe->va0_l = (u32)wr->sg_list[0].addr;
 197                         ud_sq_wqe->va0_h = (wr->sg_list[0].addr) >> 32;
 198                         ud_sq_wqe->l_key0 = wr->sg_list[0].lkey;
 199
 200                         ud_sq_wqe->va1_l = (u32)wr->sg_list[1].addr;
 201                         ud_sq_wqe->va1_h = (wr->sg_list[1].addr) >> 32;
 202                         ud_sq_wqe->l_key1 = wr->sg_list[1].lkey;
 203                         ind++;
 204                 } else if (ibqp->qp_type == IB_QPT_RC) {
 205                         ctrl = wqe;
 206                         memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
 207                         for (i = 0; i < wr->num_sge; i++)
 208                                 ctrl->msg_length += wr->sg_list[i].length;
 209
 210                         ctrl->sgl_pa_h = 0;
 211                         ctrl->flag = 0;
 212                         ctrl->imm_data = send_ieth(wr);
 213
 214                         /*Ctrl field, ctrl set type: sig, solic, imm, fence */
 215                         /* SO wait for conforming application scenarios */
 216                         ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
 217                                       cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
 218                                       (wr->send_flags & IB_SEND_SOLICITED ?
 219                                       cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
 220                                       ((wr->opcode == IB_WR_SEND_WITH_IMM ||
 221                                       wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
 222                                       cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
 223                                       (wr->send_flags & IB_SEND_FENCE ?
 224                                       (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
 225
 226                         wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
 227
 228                         switch (wr->opcode) {
 229                         case IB_WR_RDMA_READ:
 230                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
 231                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
 232                                               atomic_wr(wr)->rkey);
 233                                 break;
 234                         case IB_WR_RDMA_WRITE:
 235                         case IB_WR_RDMA_WRITE_WITH_IMM:
 236                                 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
 237                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
 238                                               atomic_wr(wr)->rkey);
 239                                 break;
 240                         case IB_WR_SEND:
 241                         case IB_WR_SEND_WITH_INV:
 242                         case IB_WR_SEND_WITH_IMM:
 243                                 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
 244                                 break;
 245                         case IB_WR_LOCAL_INV:
 246                                 break;
 247                         case IB_WR_ATOMIC_CMP_AND_SWP:
 248                         case IB_WR_ATOMIC_FETCH_AND_ADD:
 249                         case IB_WR_LSO:
 250                         default:
 251                                 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
 252                                 break;
 253                         }
 254                         ctrl->flag |= cpu_to_le32(ps_opcode);
 255                         wqe += sizeof(struct hns_roce_wqe_raddr_seg);
 256
 257                         dseg = wqe;
 258                         if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
 259                                 if (ctrl->msg_length >
 260                                         hr_dev->caps.max_sq_inline) {
 261                                         ret = -EINVAL;
 262                                         *bad_wr = wr;
 263                                         dev_err(dev, "inline len(1-%d)=%d, illegal",
 264                                                 ctrl->msg_length,
 265                                                 hr_dev->caps.max_sq_inline);
 266                                         goto out;
 267                                 }
 268                                 for (i = 0; i < wr->num_sge; i++) {
 269                                         memcpy(wqe, ((void *) (uintptr_t)
 270                                                wr->sg_list[i].addr),
 271                                                wr->sg_list[i].length);
 272                                         wqe += wr->sg_list[i].length;
 273                                 }
 274                                 ctrl->flag |= HNS_ROCE_WQE_INLINE;
 275                         } else {
 276                                 /*sqe num is two */
 277                                 for (i = 0; i < wr->num_sge; i++)
 278                                         set_data_seg(dseg + i, wr->sg_list + i);
 279
 280                                 ctrl->flag |= cpu_to_le32(wr->num_sge <<
 281                                               HNS_ROCE_WQE_SGE_NUM_BIT);
 282                         }
 283                         ind++;
 284                 }
 285         }
 286
 287 out:
 288         /* Set DB return */
 289         if (likely(nreq)) {
 290                 qp->sq.head += nreq;
 291                 /* Memory barrier */
 292                 wmb();
 293
 294                 sq_db.u32_4 = 0;
 295                 sq_db.u32_8 = 0;
 296                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
 297                                SQ_DOORBELL_U32_4_SQ_HEAD_S,
 298                               (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
 299                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
 300                                SQ_DOORBELL_U32_4_SL_S, qp->sl);
 301                 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
 302                                SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
 303                 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
 304                                SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
 305                 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
 306
 307                 doorbell[0] = sq_db.u32_4;
 308                 doorbell[1] = sq_db.u32_8;
 309
 310                 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
 311                 qp->sq_next_wqe = ind;
 312         }
 313
 314         spin_unlock_irqrestore(&qp->sq.lock, flags);
 315
 316         return ret;
 317 }
 318
 319 int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 320                           struct ib_recv_wr **bad_wr)
 321 {
 322         int ret = 0;
 323         int nreq = 0;
 324         int ind = 0;
 325         int i = 0;
 326         u32 reg_val = 0;
 327         unsigned long flags = 0;
 328         struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
 329         struct hns_roce_wqe_data_seg *scat = NULL;
 330         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
 331         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
 332         struct device *dev = &hr_dev->pdev->dev;
 333         struct hns_roce_rq_db rq_db;
 334         uint32_t doorbell[2] = {0};
 335
 336         spin_lock_irqsave(&hr_qp->rq.lock, flags);
 337         ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
 338
 339         for (nreq = 0; wr; ++nreq, wr = wr->next) {
 340                 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
 341                         hr_qp->ibqp.recv_cq)) {
 342                         ret = -ENOMEM;
 343                         *bad_wr = wr;
 344                         goto out;
 345                 }
 346
 347                 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
 348                         dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
 349                                 wr->num_sge, hr_qp->rq.max_gs);
 350                         ret = -EINVAL;
 351                         *bad_wr = wr;
 352                         goto out;
 353                 }
 354
 355                 ctrl = get_recv_wqe(hr_qp, ind);
 356
 357                 roce_set_field(ctrl->rwqe_byte_12,
 358                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
 359                                RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
 360                                wr->num_sge);
 361
 362                 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
 363
 364                 for (i = 0; i < wr->num_sge; i++)
 365                         set_data_seg(scat + i, wr->sg_list + i);
 366
 367                 hr_qp->rq.wrid[ind] = wr->wr_id;
 368
 369                 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
 370         }
 371
 372 out:
 373         if (likely(nreq)) {
 374                 hr_qp->rq.head += nreq;
 375                 /* Memory barrier */
 376                 wmb();
 377
 378                 if (ibqp->qp_type == IB_QPT_GSI) {
 379                         /* SW update GSI rq header */
 380                         reg_val = roce_read(to_hr_dev(ibqp->device),
 381                                             ROCEE_QP1C_CFG3_0_REG +
 382                                             QP1C_CFGN_OFFSET * hr_qp->phy_port);
 383                         roce_set_field(reg_val,
 384                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
 385                                        ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
 386                                        hr_qp->rq.head);
 387                         roce_write(to_hr_dev(ibqp->device),
 388                                    ROCEE_QP1C_CFG3_0_REG +
 389                                    QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
 390                 } else {
 391                         rq_db.u32_4 = 0;
 392                         rq_db.u32_8 = 0;
 393
 394                         roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
 395                                        RQ_DOORBELL_U32_4_RQ_HEAD_S,
 396                                        hr_qp->rq.head);
 397                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
 398                                        RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
 399                         roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
 400                                        RQ_DOORBELL_U32_8_CMD_S, 1);
 401                         roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
 402                                      1);
 403
 404                         doorbell[0] = rq_db.u32_4;
 405                         doorbell[1] = rq_db.u32_8;
 406
 407                         hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
 408                 }
 409         }
 410         spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
 411
 412         return ret;
 413 }
 414
 415 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
 416                                        int sdb_mode, int odb_mode)
 417 {
 418         u32 val;
 419
 420         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 421         roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
 422         roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
 423         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 424 }
 425
 426 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
 427                                      u32 odb_mode)
 428 {
 429         u32 val;
 430
 431         /* Configure SDB/ODB extend mode */
 432         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
 433         roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
 434         roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
 435         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
 436 }
 437
 438 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
 439                              u32 sdb_alful)
 440 {
 441         u32 val;
 442
 443         /* Configure SDB */
 444         val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
 445         roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
 446                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
 447         roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
 448                        ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
 449         roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
 450 }
 451
 452 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
 453                              u32 odb_alful)
 454 {
 455         u32 val;
 456
 457         /* Configure ODB */
 458         val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
 459         roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
 460                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
 461         roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
 462                        ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
 463         roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
 464 }
 465
 466 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
 467                                  u32 ext_sdb_alful)
 468 {
 469         struct device *dev = &hr_dev->pdev->dev;
 470         struct hns_roce_v1_priv *priv;
 471         struct hns_roce_db_table *db;
 472         dma_addr_t sdb_dma_addr;
 473         u32 val;
 474
 475         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 476         db = &priv->db_table;
 477
 478         /* Configure extend SDB threshold */
 479         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
 480         roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
 481
 482         /* Configure extend SDB base addr */
 483         sdb_dma_addr = db->ext_db->sdb_buf_list->map;
 484         roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
 485
 486         /* Configure extend SDB depth */
 487         val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
 488         roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
 489                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
 490                        db->ext_db->esdb_dep);
 491         /*
 492          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
 493          * using 4K page, and shift more 32 because of
 494          * caculating the high 32 bit value evaluated to hardware.
 495          */
 496         roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
 497                        ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
 498         roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
 499
 500         dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
 501         dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
 502                 ext_sdb_alept, ext_sdb_alful);
 503 }
 504
 505 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
 506                                  u32 ext_odb_alful)
 507 {
 508         struct device *dev = &hr_dev->pdev->dev;
 509         struct hns_roce_v1_priv *priv;
 510         struct hns_roce_db_table *db;
 511         dma_addr_t odb_dma_addr;
 512         u32 val;
 513
 514         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 515         db = &priv->db_table;
 516
 517         /* Configure extend ODB threshold */
 518         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
 519         roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
 520
 521         /* Configure extend ODB base addr */
 522         odb_dma_addr = db->ext_db->odb_buf_list->map;
 523         roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
 524
 525         /* Configure extend ODB depth */
 526         val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
 527         roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
 528                        ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
 529                        db->ext_db->eodb_dep);
 530         roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
 531                        ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
 532                        db->ext_db->eodb_dep);
 533         roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
 534
 535         dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
 536         dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
 537                 ext_odb_alept, ext_odb_alful);
 538 }
 539
 540 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
 541                                 u32 odb_ext_mod)
 542 {
 543         struct device *dev = &hr_dev->pdev->dev;
 544         struct hns_roce_v1_priv *priv;
 545         struct hns_roce_db_table *db;
 546         dma_addr_t sdb_dma_addr;
 547         dma_addr_t odb_dma_addr;
 548         int ret = 0;
 549
 550         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 551         db = &priv->db_table;
 552
 553         db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
 554         if (!db->ext_db)
 555                 return -ENOMEM;
 556
 557         if (sdb_ext_mod) {
 558                 db->ext_db->sdb_buf_list = kmalloc(
 559                                 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
 560                 if (!db->ext_db->sdb_buf_list) {
 561                         ret = -ENOMEM;
 562                         goto ext_sdb_buf_fail_out;
 563                 }
 564
 565                 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
 566                                                      HNS_ROCE_V1_EXT_SDB_SIZE,
 567                                                      &sdb_dma_addr, GFP_KERNEL);
 568                 if (!db->ext_db->sdb_buf_list->buf) {
 569                         ret = -ENOMEM;
 570                         goto alloc_sq_db_buf_fail;
 571                 }
 572                 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
 573
 574                 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
 575                 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
 576                                      HNS_ROCE_V1_EXT_SDB_ALFUL);
 577         } else
 578                 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
 579                                  HNS_ROCE_V1_SDB_ALFUL);
 580
 581         if (odb_ext_mod) {
 582                 db->ext_db->odb_buf_list = kmalloc(
 583                                 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
 584                 if (!db->ext_db->odb_buf_list) {
 585                         ret = -ENOMEM;
 586                         goto ext_odb_buf_fail_out;
 587                 }
 588
 589                 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
 590                                                      HNS_ROCE_V1_EXT_ODB_SIZE,
 591                                                      &odb_dma_addr, GFP_KERNEL);
 592                 if (!db->ext_db->odb_buf_list->buf) {
 593                         ret = -ENOMEM;
 594                         goto alloc_otr_db_buf_fail;
 595                 }
 596                 db->ext_db->odb_buf_list->map = odb_dma_addr;
 597
 598                 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
 599                 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
 600                                      HNS_ROCE_V1_EXT_ODB_ALFUL);
 601         } else
 602                 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
 603                                  HNS_ROCE_V1_ODB_ALFUL);
 604
 605         hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
 606
 607         return 0;
 608
 609 alloc_otr_db_buf_fail:
 610         kfree(db->ext_db->odb_buf_list);
 611
 612 ext_odb_buf_fail_out:
 613         if (sdb_ext_mod) {
 614                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
 615                                   db->ext_db->sdb_buf_list->buf,
 616                                   db->ext_db->sdb_buf_list->map);
 617         }
 618
 619 alloc_sq_db_buf_fail:
 620         if (sdb_ext_mod)
 621                 kfree(db->ext_db->sdb_buf_list);
 622
 623 ext_sdb_buf_fail_out:
 624         kfree(db->ext_db);
 625         return ret;
 626 }
 627
 628 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
 629                                                     struct ib_pd *pd)
 630 {
 631         struct device *dev = &hr_dev->pdev->dev;
 632         struct ib_qp_init_attr init_attr;
 633         struct ib_qp *qp;
 634
 635         memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
 636         init_attr.qp_type               = IB_QPT_RC;
 637         init_attr.sq_sig_type           = IB_SIGNAL_ALL_WR;
 638         init_attr.cap.max_recv_wr       = HNS_ROCE_MIN_WQE_NUM;
 639         init_attr.cap.max_send_wr       = HNS_ROCE_MIN_WQE_NUM;
 640
 641         qp = hns_roce_create_qp(pd, &init_attr, NULL);
 642         if (IS_ERR(qp)) {
 643                 dev_err(dev, "Create loop qp for mr free failed!");
 644                 return NULL;
 645         }
 646
 647         return to_hr_qp(qp);
 648 }
 649
 650 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 651 {
 652         struct hns_roce_caps *caps = &hr_dev->caps;
 653         struct device *dev = &hr_dev->pdev->dev;
 654         struct ib_cq_init_attr cq_init_attr;
 655         struct hns_roce_free_mr *free_mr;
 656         struct ib_qp_attr attr = { 0 };
 657         struct hns_roce_v1_priv *priv;
 658         struct hns_roce_qp *hr_qp;
 659         struct ib_cq *cq;
 660         struct ib_pd *pd;
 661         u64 subnet_prefix;
 662         int attr_mask = 0;
 663         int i;
 664         int ret;
 665         u8 phy_port;
 666         u8 sl;
 667
 668         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 669         free_mr = &priv->free_mr;
 670
 671         /* Reserved cq for loop qp */
 672         cq_init_attr.cqe                = HNS_ROCE_MIN_WQE_NUM * 2;
 673         cq_init_attr.comp_vector        = 0;
 674         cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
 675         if (IS_ERR(cq)) {
 676                 dev_err(dev, "Create cq for reseved loop qp failed!");
 677                 return -ENOMEM;
 678         }
 679         free_mr->mr_free_cq = to_hr_cq(cq);
 680         free_mr->mr_free_cq->ib_cq.device               = &hr_dev->ib_dev;
 681         free_mr->mr_free_cq->ib_cq.uobject              = NULL;
 682         free_mr->mr_free_cq->ib_cq.comp_handler         = NULL;
 683         free_mr->mr_free_cq->ib_cq.event_handler        = NULL;
 684         free_mr->mr_free_cq->ib_cq.cq_context           = NULL;
 685         atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
 686
 687         pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
 688         if (IS_ERR(pd)) {
 689                 dev_err(dev, "Create pd for reseved loop qp failed!");
 690                 ret = -ENOMEM;
 691                 goto alloc_pd_failed;
 692         }
 693         free_mr->mr_free_pd = to_hr_pd(pd);
 694         free_mr->mr_free_pd->ibpd.device  = &hr_dev->ib_dev;
 695         free_mr->mr_free_pd->ibpd.uobject = NULL;
 696         atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
 697
 698         attr.qp_access_flags    = IB_ACCESS_REMOTE_WRITE;
 699         attr.pkey_index         = 0;
 700         attr.min_rnr_timer      = 0;
 701         /* Disable read ability */
 702         attr.max_dest_rd_atomic = 0;
 703         attr.max_rd_atomic      = 0;
 704         /* Use arbitrary values as rq_psn and sq_psn */
 705         attr.rq_psn             = 0x0808;
 706         attr.sq_psn             = 0x0808;
 707         attr.retry_cnt          = 7;
 708         attr.rnr_retry          = 7;
 709         attr.timeout            = 0x12;
 710         attr.path_mtu           = IB_MTU_256;
 711         attr.ah_attr.ah_flags           = 1;
 712         attr.ah_attr.static_rate        = 3;
 713         attr.ah_attr.grh.sgid_index     = 0;
 714         attr.ah_attr.grh.hop_limit      = 1;
 715         attr.ah_attr.grh.flow_label     = 0;
 716         attr.ah_attr.grh.traffic_class  = 0;
 717
 718         subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
 719         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 720                 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
 721                 if (IS_ERR(free_mr->mr_free_qp[i])) {
 722                         dev_err(dev, "Create loop qp failed!\n");
 723                         goto create_lp_qp_failed;
 724                 }
 725                 hr_qp = free_mr->mr_free_qp[i];
 726
 727                 sl = i / caps->num_ports;
 728
 729                 if (caps->num_ports == HNS_ROCE_MAX_PORTS)
 730                         phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
 731                                 (i % caps->num_ports);
 732                 else
 733                         phy_port = i % caps->num_ports;
 734
 735                 hr_qp->port             = phy_port + 1;
 736                 hr_qp->phy_port         = phy_port;
 737                 hr_qp->ibqp.qp_type     = IB_QPT_RC;
 738                 hr_qp->ibqp.device      = &hr_dev->ib_dev;
 739                 hr_qp->ibqp.uobject     = NULL;
 740                 atomic_set(&hr_qp->ibqp.usecnt, 0);
 741                 hr_qp->ibqp.pd          = pd;
 742                 hr_qp->ibqp.recv_cq     = cq;
 743                 hr_qp->ibqp.send_cq     = cq;
 744
 745                 attr.ah_attr.port_num   = phy_port + 1;
 746                 attr.ah_attr.sl         = sl;
 747                 attr.port_num           = phy_port + 1;
 748
 749                 attr.dest_qp_num        = hr_qp->qpn;
 750                 memcpy(attr.ah_attr.dmac, hr_dev->dev_addr[phy_port],
 751                        MAC_ADDR_OCTET_NUM);
 752
 753                 memcpy(attr.ah_attr.grh.dgid.raw,
 754                         &subnet_prefix, sizeof(u64));
 755                 memcpy(&attr.ah_attr.grh.dgid.raw[8],
 756                        hr_dev->dev_addr[phy_port], 3);
 757                 memcpy(&attr.ah_attr.grh.dgid.raw[13],
 758                        hr_dev->dev_addr[phy_port] + 3, 3);
 759                 attr.ah_attr.grh.dgid.raw[11] = 0xff;
 760                 attr.ah_attr.grh.dgid.raw[12] = 0xfe;
 761                 attr.ah_attr.grh.dgid.raw[8] ^= 2;
 762
 763                 attr_mask |= IB_QP_PORT;
 764
 765                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 766                                             IB_QPS_RESET, IB_QPS_INIT);
 767                 if (ret) {
 768                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 769                         goto create_lp_qp_failed;
 770                 }
 771
 772                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 773                                             IB_QPS_INIT, IB_QPS_RTR);
 774                 if (ret) {
 775                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 776                         goto create_lp_qp_failed;
 777                 }
 778
 779                 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
 780                                             IB_QPS_RTR, IB_QPS_RTS);
 781                 if (ret) {
 782                         dev_err(dev, "modify qp failed(%d)!\n", ret);
 783                         goto create_lp_qp_failed;
 784                 }
 785         }
 786
 787         return 0;
 788
 789 create_lp_qp_failed:
 790         for (i -= 1; i >= 0; i--) {
 791                 hr_qp = free_mr->mr_free_qp[i];
 792                 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
 793                         dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
 794         }
 795
 796         if (hns_roce_dealloc_pd(pd))
 797                 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
 798
 799 alloc_pd_failed:
 800         if (hns_roce_ib_destroy_cq(cq))
 801                 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
 802
 803         return -EINVAL;
 804 }
 805
 806 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
 807 {
 808         struct device *dev = &hr_dev->pdev->dev;
 809         struct hns_roce_free_mr *free_mr;
 810         struct hns_roce_v1_priv *priv;
 811         struct hns_roce_qp *hr_qp;
 812         int ret;
 813         int i;
 814
 815         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 816         free_mr = &priv->free_mr;
 817
 818         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 819                 hr_qp = free_mr->mr_free_qp[i];
 820                 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
 821                 if (ret)
 822                         dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
 823                                 i, ret);
 824         }
 825
 826         ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
 827         if (ret)
 828                 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
 829
 830         ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
 831         if (ret)
 832                 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
 833 }
 834
 835 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
 836 {
 837         struct device *dev = &hr_dev->pdev->dev;
 838         struct hns_roce_v1_priv *priv;
 839         struct hns_roce_db_table *db;
 840         u32 sdb_ext_mod;
 841         u32 odb_ext_mod;
 842         u32 sdb_evt_mod;
 843         u32 odb_evt_mod;
 844         int ret = 0;
 845
 846         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 847         db = &priv->db_table;
 848
 849         memset(db, 0, sizeof(*db));
 850
 851         /* Default DB mode */
 852         sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
 853         odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
 854         sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
 855         odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
 856
 857         db->sdb_ext_mod = sdb_ext_mod;
 858         db->odb_ext_mod = odb_ext_mod;
 859
 860         /* Init extend DB */
 861         ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
 862         if (ret) {
 863                 dev_err(dev, "Failed in extend DB configuration.\n");
 864                 return ret;
 865         }
 866
 867         hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
 868
 869         return 0;
 870 }
 871
 872 void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
 873 {
 874         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 875         struct hns_roce_dev *hr_dev;
 876
 877         lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
 878                                   work);
 879         hr_dev = to_hr_dev(lp_qp_work->ib_dev);
 880
 881         hns_roce_v1_release_lp_qp(hr_dev);
 882
 883         if (hns_roce_v1_rsv_lp_qp(hr_dev))
 884                 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
 885
 886         if (lp_qp_work->comp_flag)
 887                 complete(lp_qp_work->comp);
 888
 889         kfree(lp_qp_work);
 890 }
 891
 892 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
 893 {
 894         struct device *dev = &hr_dev->pdev->dev;
 895         struct hns_roce_recreate_lp_qp_work *lp_qp_work;
 896         struct hns_roce_free_mr *free_mr;
 897         struct hns_roce_v1_priv *priv;
 898         struct completion comp;
 899         unsigned long end =
 900           msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
 901
 902         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 903         free_mr = &priv->free_mr;
 904
 905         lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
 906                              GFP_KERNEL);
 907
 908         INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
 909
 910         lp_qp_work->ib_dev = &(hr_dev->ib_dev);
 911         lp_qp_work->comp = &comp;
 912         lp_qp_work->comp_flag = 1;
 913
 914         init_completion(lp_qp_work->comp);
 915
 916         queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
 917
 918         while (time_before_eq(jiffies, end)) {
 919                 if (try_wait_for_completion(&comp))
 920                         return 0;
 921                 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
 922         }
 923
 924         lp_qp_work->comp_flag = 0;
 925         if (try_wait_for_completion(&comp))
 926                 return 0;
 927
 928         dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
 929         return -ETIMEDOUT;
 930 }
 931
 932 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
 933 {
 934         struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
 935         struct device *dev = &hr_dev->pdev->dev;
 936         struct ib_send_wr send_wr, *bad_wr;
 937         int ret;
 938
 939         memset(&send_wr, 0, sizeof(send_wr));
 940         send_wr.next    = NULL;
 941         send_wr.num_sge = 0;
 942         send_wr.send_flags = 0;
 943         send_wr.sg_list = NULL;
 944         send_wr.wr_id   = (unsigned long long)&send_wr;
 945         send_wr.opcode  = IB_WR_RDMA_WRITE;
 946
 947         ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
 948         if (ret) {
 949                 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
 950                 return ret;
 951         }
 952
 953         return 0;
 954 }
 955
 956 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
 957 {
 958         struct hns_roce_mr_free_work *mr_work;
 959         struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
 960         struct hns_roce_free_mr *free_mr;
 961         struct hns_roce_cq *mr_free_cq;
 962         struct hns_roce_v1_priv *priv;
 963         struct hns_roce_dev *hr_dev;
 964         struct hns_roce_mr *hr_mr;
 965         struct hns_roce_qp *hr_qp;
 966         struct device *dev;
 967         unsigned long end =
 968                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
 969         int i;
 970         int ret;
 971         int ne;
 972
 973         mr_work = container_of(work, struct hns_roce_mr_free_work, work);
 974         hr_mr = (struct hns_roce_mr *)mr_work->mr;
 975         hr_dev = to_hr_dev(mr_work->ib_dev);
 976         dev = &hr_dev->pdev->dev;
 977
 978         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
 979         free_mr = &priv->free_mr;
 980         mr_free_cq = free_mr->mr_free_cq;
 981
 982         for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
 983                 hr_qp = free_mr->mr_free_qp[i];
 984                 ret = hns_roce_v1_send_lp_wqe(hr_qp);
 985                 if (ret) {
 986                         dev_err(dev,
 987                              "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
 988                              hr_qp->qpn, ret);
 989                         goto free_work;
 990                 }
 991         }
 992
 993         ne = HNS_ROCE_V1_RESV_QP;
 994         do {
 995                 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
 996                 if (ret < 0) {
 997                         dev_err(dev,
 998                            "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
 999                            hr_qp->qpn, ret, hr_mr->key, ne);
1000                         goto free_work;
1001                 }
1002                 ne -= ret;
1003                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1004         } while (ne && time_before_eq(jiffies, end));
1005
1006         if (ne != 0)
1007                 dev_err(dev,
1008                         "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1009                         hr_mr->key, ne);
1010
1011 free_work:
1012         if (mr_work->comp_flag)
1013                 complete(mr_work->comp);
1014         kfree(mr_work);
1015 }
1016
1017 int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
1018 {
1019         struct device *dev = &hr_dev->pdev->dev;
1020         struct hns_roce_mr_free_work *mr_work;
1021         struct hns_roce_free_mr *free_mr;
1022         struct hns_roce_v1_priv *priv;
1023         struct completion comp;
1024         unsigned long end =
1025                 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1026         unsigned long start = jiffies;
1027         int npages;
1028         int ret = 0;
1029
1030         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1031         free_mr = &priv->free_mr;
1032
1033         if (mr->enabled) {
1034                 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1035                                        & (hr_dev->caps.num_mtpts - 1)))
1036                         dev_warn(dev, "HW2SW_MPT failed!\n");
1037         }
1038
1039         mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1040         if (!mr_work) {
1041                 ret = -ENOMEM;
1042                 goto free_mr;
1043         }
1044
1045         INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1046
1047         mr_work->ib_dev = &(hr_dev->ib_dev);
1048         mr_work->comp = &comp;
1049         mr_work->comp_flag = 1;
1050         mr_work->mr = (void *)mr;
1051         init_completion(mr_work->comp);
1052
1053         queue_work(free_mr->free_mr_wq, &(mr_work->work));
1054
1055         while (time_before_eq(jiffies, end)) {
1056                 if (try_wait_for_completion(&comp))
1057                         goto free_mr;
1058                 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1059         }
1060
1061         mr_work->comp_flag = 0;
1062         if (try_wait_for_completion(&comp))
1063                 goto free_mr;
1064
1065         dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1066         ret = -ETIMEDOUT;
1067
1068 free_mr:
1069         dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1070                 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1071
1072         if (mr->size != ~0ULL) {
1073                 npages = ib_umem_page_count(mr->umem);
1074                 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1075                                   mr->pbl_dma_addr);
1076         }
1077
1078         hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1079                              key_to_hw_index(mr->key), 0);
1080
1081         if (mr->umem)
1082                 ib_umem_release(mr->umem);
1083
1084         kfree(mr);
1085
1086         return ret;
1087 }
1088
1089 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1090 {
1091         struct device *dev = &hr_dev->pdev->dev;
1092         struct hns_roce_v1_priv *priv;
1093         struct hns_roce_db_table *db;
1094
1095         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1096         db = &priv->db_table;
1097
1098         if (db->sdb_ext_mod) {
1099                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1100                                   db->ext_db->sdb_buf_list->buf,
1101                                   db->ext_db->sdb_buf_list->map);
1102                 kfree(db->ext_db->sdb_buf_list);
1103         }
1104
1105         if (db->odb_ext_mod) {
1106                 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1107                                   db->ext_db->odb_buf_list->buf,
1108                                   db->ext_db->odb_buf_list->map);
1109                 kfree(db->ext_db->odb_buf_list);
1110         }
1111
1112         kfree(db->ext_db);
1113 }
1114
1115 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1116 {
1117         int ret;
1118         int raq_shift = 0;
1119         dma_addr_t addr;
1120         u32 val;
1121         struct hns_roce_v1_priv *priv;
1122         struct hns_roce_raq_table *raq;
1123         struct device *dev = &hr_dev->pdev->dev;
1124
1125         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1126         raq = &priv->raq_table;
1127
1128         raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1129         if (!raq->e_raq_buf)
1130                 return -ENOMEM;
1131
1132         raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1133                                                  &addr, GFP_KERNEL);
1134         if (!raq->e_raq_buf->buf) {
1135                 ret = -ENOMEM;
1136                 goto err_dma_alloc_raq;
1137         }
1138         raq->e_raq_buf->map = addr;
1139
1140         /* Configure raq extended address. 48bit 4K align*/
1141         roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1142
1143         /* Configure raq_shift */
1144         raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1145         val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1146         roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1147                        ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1148         /*
1149          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1150          * using 4K page, and shift more 32 because of
1151          * caculating the high 32 bit value evaluated to hardware.
1152          */
1153         roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1154                        ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1155                        raq->e_raq_buf->map >> 44);
1156         roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1157         dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1158
1159         /* Configure raq threshold */
1160         val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1161         roce_set_field(val, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1162                        ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1163                        HNS_ROCE_V1_EXT_RAQ_WF);
1164         roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1165         dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1166
1167         /* Enable extend raq */
1168         val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1169         roce_set_field(val,
1170                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1171                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1172                        POL_TIME_INTERVAL_VAL);
1173         roce_set_bit(val, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1174         roce_set_field(val,
1175                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1176                        ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1177                        2);
1178         roce_set_bit(val,
1179                      ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1180         roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1181         dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1182
1183         /* Enable raq drop */
1184         val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1185         roce_set_bit(val, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1186         roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1187         dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1188
1189         return 0;
1190
1191 err_dma_alloc_raq:
1192         kfree(raq->e_raq_buf);
1193         return ret;
1194 }
1195
1196 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1197 {
1198         struct device *dev = &hr_dev->pdev->dev;
1199         struct hns_roce_v1_priv *priv;
1200         struct hns_roce_raq_table *raq;
1201
1202         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1203         raq = &priv->raq_table;
1204
1205         dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1206                           raq->e_raq_buf->map);
1207         kfree(raq->e_raq_buf);
1208 }
1209
1210 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1211 {
1212         u32 val;
1213
1214         if (enable_flag) {
1215                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1216                  /* Open all ports */
1217                 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1218                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1219                                ALL_PORT_VAL_OPEN);
1220                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1221         } else {
1222                 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1223                 /* Close all ports */
1224                 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1225                                ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1226                 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1227         }
1228 }
1229
1230 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1231 {
1232         struct device *dev = &hr_dev->pdev->dev;
1233         struct hns_roce_v1_priv *priv;
1234         int ret;
1235
1236         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1237
1238         priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1239                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1240                 GFP_KERNEL);
1241         if (!priv->bt_table.qpc_buf.buf)
1242                 return -ENOMEM;
1243
1244         priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1245                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1246                 GFP_KERNEL);
1247         if (!priv->bt_table.mtpt_buf.buf) {
1248                 ret = -ENOMEM;
1249                 goto err_failed_alloc_mtpt_buf;
1250         }
1251
1252         priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1253                 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1254                 GFP_KERNEL);
1255         if (!priv->bt_table.cqc_buf.buf) {
1256                 ret = -ENOMEM;
1257                 goto err_failed_alloc_cqc_buf;
1258         }
1259
1260         return 0;
1261
1262 err_failed_alloc_cqc_buf:
1263         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1264                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1265
1266 err_failed_alloc_mtpt_buf:
1267         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1268                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1269
1270         return ret;
1271 }
1272
1273 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1274 {
1275         struct device *dev = &hr_dev->pdev->dev;
1276         struct hns_roce_v1_priv *priv;
1277
1278         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1279
1280         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1281                 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1282
1283         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1284                 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1285
1286         dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1287                 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1288 }
1289
1290 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1291 {
1292         struct device *dev = &hr_dev->pdev->dev;
1293         struct hns_roce_buf_list *tptr_buf;
1294         struct hns_roce_v1_priv *priv;
1295
1296         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1297         tptr_buf = &priv->tptr_table.tptr_buf;
1298
1299         /*
1300          * This buffer will be used for CQ's tptr(tail pointer), also
1301          * named ci(customer index). Every CQ will use 2 bytes to save
1302          * cqe ci in hip06. Hardware will read this area to get new ci
1303          * when the queue is almost full.
1304          */
1305         tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1306                                            &tptr_buf->map, GFP_KERNEL);
1307         if (!tptr_buf->buf)
1308                 return -ENOMEM;
1309
1310         hr_dev->tptr_dma_addr = tptr_buf->map;
1311         hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1312
1313         return 0;
1314 }
1315
1316 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1317 {
1318         struct device *dev = &hr_dev->pdev->dev;
1319         struct hns_roce_buf_list *tptr_buf;
1320         struct hns_roce_v1_priv *priv;
1321
1322         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1323         tptr_buf = &priv->tptr_table.tptr_buf;
1324
1325         dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1326                           tptr_buf->buf, tptr_buf->map);
1327 }
1328
1329 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1330 {
1331         struct device *dev = &hr_dev->pdev->dev;
1332         struct hns_roce_free_mr *free_mr;
1333         struct hns_roce_v1_priv *priv;
1334         int ret = 0;
1335
1336         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1337         free_mr = &priv->free_mr;
1338
1339         free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1340         if (!free_mr->free_mr_wq) {
1341                 dev_err(dev, "Create free mr workqueue failed!\n");
1342                 return -ENOMEM;
1343         }
1344
1345         ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1346         if (ret) {
1347                 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1348                 flush_workqueue(free_mr->free_mr_wq);
1349                 destroy_workqueue(free_mr->free_mr_wq);
1350         }
1351
1352         return ret;
1353 }
1354
1355 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1356 {
1357         struct hns_roce_free_mr *free_mr;
1358         struct hns_roce_v1_priv *priv;
1359
1360         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1361         free_mr = &priv->free_mr;
1362
1363         flush_workqueue(free_mr->free_mr_wq);
1364         destroy_workqueue(free_mr->free_mr_wq);
1365
1366         hns_roce_v1_release_lp_qp(hr_dev);
1367 }
1368
1369 /**
1370  * hns_roce_v1_reset - reset RoCE
1371  * @hr_dev: RoCE device struct pointer
1372  * @enable: true -- drop reset, false -- reset
1373  * return 0 - success , negative --fail
1374  */
1375 int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1376 {
1377         struct device_node *dsaf_node;
1378         struct device *dev = &hr_dev->pdev->dev;
1379         struct device_node *np = dev->of_node;
1380         struct fwnode_handle *fwnode;
1381         int ret;
1382
1383         /* check if this is DT/ACPI case */
1384         if (dev_of_node(dev)) {
1385                 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1386                 if (!dsaf_node) {
1387                         dev_err(dev, "could not find dsaf-handle\n");
1388                         return -EINVAL;
1389                 }
1390                 fwnode = &dsaf_node->fwnode;
1391         } else if (is_acpi_device_node(dev->fwnode)) {
1392                 struct acpi_reference_args args;
1393
1394                 ret = acpi_node_get_property_reference(dev->fwnode,
1395                                                        "dsaf-handle", 0, &args);
1396                 if (ret) {
1397                         dev_err(dev, "could not find dsaf-handle\n");
1398                         return ret;
1399                 }
1400                 fwnode = acpi_fwnode_handle(args.adev);
1401         } else {
1402                 dev_err(dev, "cannot read data from DT or ACPI\n");
1403                 return -ENXIO;
1404         }
1405
1406         ret = hns_dsaf_roce_reset(fwnode, false);
1407         if (ret)
1408                 return ret;
1409
1410         if (dereset) {
1411                 msleep(SLEEP_TIME_INTERVAL);
1412                 ret = hns_dsaf_roce_reset(fwnode, true);
1413         }
1414
1415         return ret;
1416 }
1417
1418 static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1419 {
1420         struct device *dev = &hr_dev->pdev->dev;
1421         struct hns_roce_v1_priv *priv;
1422         struct hns_roce_des_qp *des_qp;
1423
1424         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1425         des_qp = &priv->des_qp;
1426
1427         des_qp->requeue_flag = 1;
1428         des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1429         if (!des_qp->qp_wq) {
1430                 dev_err(dev, "Create destroy qp workqueue failed!\n");
1431                 return -ENOMEM;
1432         }
1433
1434         return 0;
1435 }
1436
1437 static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1438 {
1439         struct hns_roce_v1_priv *priv;
1440         struct hns_roce_des_qp *des_qp;
1441
1442         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1443         des_qp = &priv->des_qp;
1444
1445         des_qp->requeue_flag = 0;
1446         flush_workqueue(des_qp->qp_wq);
1447         destroy_workqueue(des_qp->qp_wq);
1448 }
1449
1450 void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1451 {
1452         int i = 0;
1453         struct hns_roce_caps *caps = &hr_dev->caps;
1454
1455         hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG));
1456         hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev,
1457                                              ROCEE_VENDOR_PART_ID_REG));
1458         hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev,
1459                                              ROCEE_SYS_IMAGE_GUID_L_REG)) |
1460                                 ((u64)le32_to_cpu(roce_read(hr_dev,
1461                                             ROCEE_SYS_IMAGE_GUID_H_REG)) << 32);
1462         hr_dev->hw_rev          = HNS_ROCE_HW_VER1;
1463
1464         caps->num_qps           = HNS_ROCE_V1_MAX_QP_NUM;
1465         caps->max_wqes          = HNS_ROCE_V1_MAX_WQE_NUM;
1466         caps->num_cqs           = HNS_ROCE_V1_MAX_CQ_NUM;
1467         caps->max_cqes          = HNS_ROCE_V1_MAX_CQE_NUM;
1468         caps->max_sq_sg         = HNS_ROCE_V1_SG_NUM;
1469         caps->max_rq_sg         = HNS_ROCE_V1_SG_NUM;
1470         caps->max_sq_inline     = HNS_ROCE_V1_INLINE_SIZE;
1471         caps->num_uars          = HNS_ROCE_V1_UAR_NUM;
1472         caps->phy_num_uars      = HNS_ROCE_V1_PHY_UAR_NUM;
1473         caps->num_aeq_vectors   = HNS_ROCE_AEQE_VEC_NUM;
1474         caps->num_comp_vectors  = HNS_ROCE_COMP_VEC_NUM;
1475         caps->num_other_vectors = HNS_ROCE_AEQE_OF_VEC_NUM;
1476         caps->num_mtpts         = HNS_ROCE_V1_MAX_MTPT_NUM;
1477         caps->num_mtt_segs      = HNS_ROCE_V1_MAX_MTT_SEGS;
1478         caps->num_pds           = HNS_ROCE_V1_MAX_PD_NUM;
1479         caps->max_qp_init_rdma  = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1480         caps->max_qp_dest_rdma  = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1481         caps->max_sq_desc_sz    = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1482         caps->max_rq_desc_sz    = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1483         caps->qpc_entry_sz      = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1484         caps->irrl_entry_sz     = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1485         caps->cqc_entry_sz      = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1486         caps->mtpt_entry_sz     = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1487         caps->mtt_entry_sz      = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1488         caps->cq_entry_sz       = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1489         caps->page_size_cap     = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1490         caps->reserved_lkey     = 0;
1491         caps->reserved_pds      = 0;
1492         caps->reserved_mrws     = 1;
1493         caps->reserved_uars     = 0;
1494         caps->reserved_cqs      = 0;
1495
1496         for (i = 0; i < caps->num_ports; i++)
1497                 caps->pkey_table_len[i] = 1;
1498
1499         for (i = 0; i < caps->num_ports; i++) {
1500                 /* Six ports shared 16 GID in v1 engine */
1501                 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1502                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1503                                                  caps->num_ports;
1504                 else
1505                         caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1506                                                  caps->num_ports + 1;
1507         }
1508
1509         for (i = 0; i < caps->num_comp_vectors; i++)
1510                 caps->ceqe_depth[i] = HNS_ROCE_V1_NUM_COMP_EQE;
1511
1512         caps->aeqe_depth = HNS_ROCE_V1_NUM_ASYNC_EQE;
1513         caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev,
1514                                                          ROCEE_ACK_DELAY_REG));
1515         caps->max_mtu = IB_MTU_2048;
1516 }
1517
1518 int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1519 {
1520         int ret;
1521         u32 val;
1522         struct device *dev = &hr_dev->pdev->dev;
1523
1524         /* DMAE user config */
1525         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1526         roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1527                        ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1528         roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1529                        ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1530                        1 << PAGES_SHIFT_16);
1531         roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1532
1533         val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1534         roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1535                        ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1536         roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1537                        ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1538                        1 << PAGES_SHIFT_16);
1539
1540         ret = hns_roce_db_init(hr_dev);
1541         if (ret) {
1542                 dev_err(dev, "doorbell init failed!\n");
1543                 return ret;
1544         }
1545
1546         ret = hns_roce_raq_init(hr_dev);
1547         if (ret) {
1548                 dev_err(dev, "raq init failed!\n");
1549                 goto error_failed_raq_init;
1550         }
1551
1552         ret = hns_roce_bt_init(hr_dev);
1553         if (ret) {
1554                 dev_err(dev, "bt init failed!\n");
1555                 goto error_failed_bt_init;
1556         }
1557
1558         ret = hns_roce_tptr_init(hr_dev);
1559         if (ret) {
1560                 dev_err(dev, "tptr init failed!\n");
1561                 goto error_failed_tptr_init;
1562         }
1563
1564         ret = hns_roce_des_qp_init(hr_dev);
1565         if (ret) {
1566                 dev_err(dev, "des qp init failed!\n");
1567                 goto error_failed_des_qp_init;
1568         }
1569
1570         ret = hns_roce_free_mr_init(hr_dev);
1571         if (ret) {
1572                 dev_err(dev, "free mr init failed!\n");
1573                 goto error_failed_free_mr_init;
1574         }
1575
1576         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1577
1578         return 0;
1579
1580 error_failed_free_mr_init:
1581         hns_roce_des_qp_free(hr_dev);
1582
1583 error_failed_des_qp_init:
1584         hns_roce_tptr_free(hr_dev);
1585
1586 error_failed_tptr_init:
1587         hns_roce_bt_free(hr_dev);
1588
1589 error_failed_bt_init:
1590         hns_roce_raq_free(hr_dev);
1591
1592 error_failed_raq_init:
1593         hns_roce_db_free(hr_dev);
1594         return ret;
1595 }
1596
1597 void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1598 {
1599         hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1600         hns_roce_free_mr_free(hr_dev);
1601         hns_roce_des_qp_free(hr_dev);
1602         hns_roce_tptr_free(hr_dev);
1603         hns_roce_bt_free(hr_dev);
1604         hns_roce_raq_free(hr_dev);
1605         hns_roce_db_free(hr_dev);
1606 }
1607
1608 void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
1609                          union ib_gid *gid)
1610 {
1611         u32 *p = NULL;
1612         u8 gid_idx = 0;
1613
1614         gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1615
1616         p = (u32 *)&gid->raw[0];
1617         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1618                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1619
1620         p = (u32 *)&gid->raw[4];
1621         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1622                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1623
1624         p = (u32 *)&gid->raw[8];
1625         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1626                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1627
1628         p = (u32 *)&gid->raw[0xc];
1629         roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1630                        (HNS_ROCE_V1_GID_NUM * gid_idx));
1631 }
1632
1633 void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1634 {
1635         u32 reg_smac_l;
1636         u16 reg_smac_h;
1637         u16 *p_h;
1638         u32 *p;
1639         u32 val;
1640
1641         /*
1642          * When mac changed, loopback may fail
1643          * because of smac not equal to dmac.
1644          * We Need to release and create reserved qp again.
1645          */
1646         if (hr_dev->hw->dereg_mr && hns_roce_v1_recreate_lp_qp(hr_dev))
1647                 dev_warn(&hr_dev->pdev->dev, "recreate lp qp timeout!\n");
1648
1649         p = (u32 *)(&addr[0]);
1650         reg_smac_l = *p;
1651         roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1652                        PHY_PORT_OFFSET * phy_port);
1653
1654         val = roce_read(hr_dev,
1655                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1656         p_h = (u16 *)(&addr[4]);
1657         reg_smac_h  = *p_h;
1658         roce_set_field(val, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1659                        ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1660         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1661                    val);
1662 }
1663
1664 void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1665                          enum ib_mtu mtu)
1666 {
1667         u32 val;
1668
1669         val = roce_read(hr_dev,
1670                         ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1671         roce_set_field(val, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1672                        ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1673         roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1674                    val);
1675 }
1676
1677 int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1678                            unsigned long mtpt_idx)
1679 {
1680         struct hns_roce_v1_mpt_entry *mpt_entry;
1681         struct scatterlist *sg;
1682         u64 *pages;
1683         int entry;
1684         int i;
1685
1686         /* MPT filled into mailbox buf */
1687         mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1688         memset(mpt_entry, 0, sizeof(*mpt_entry));
1689
1690         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1691                        MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1692         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1693                        MPT_BYTE_4_KEY_S, mr->key);
1694         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1695                        MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1696         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1697         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1698                      (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1699         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1700         roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1701                        MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1702         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1703         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1704                      (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1705         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1706                      (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1707         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1708                      (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1709         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1710                      0);
1711         roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1712
1713         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1714                        MPT_BYTE_12_PBL_ADDR_H_S, 0);
1715         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1716                        MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1717
1718         mpt_entry->virt_addr_l = (u32)mr->iova;
1719         mpt_entry->virt_addr_h = (u32)(mr->iova >> 32);
1720         mpt_entry->length = (u32)mr->size;
1721
1722         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1723                        MPT_BYTE_28_PD_S, mr->pd);
1724         roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1725                        MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1726         roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1727                        MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1728
1729         /* DMA momery regsiter */
1730         if (mr->type == MR_TYPE_DMA)
1731                 return 0;
1732
1733         pages = (u64 *) __get_free_page(GFP_KERNEL);
1734         if (!pages)
1735                 return -ENOMEM;
1736
1737         i = 0;
1738         for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1739                 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1740
1741                 /* Directly record to MTPT table firstly 7 entry */
1742                 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1743                         break;
1744                 i++;
1745         }
1746
1747         /* Register user mr */
1748         for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1749                 switch (i) {
1750                 case 0:
1751                         mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1752                         roce_set_field(mpt_entry->mpt_byte_36,
1753                                 MPT_BYTE_36_PA0_H_M,
1754                                 MPT_BYTE_36_PA0_H_S,
1755                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1756                         break;
1757                 case 1:
1758                         roce_set_field(mpt_entry->mpt_byte_36,
1759                                        MPT_BYTE_36_PA1_L_M,
1760                                        MPT_BYTE_36_PA1_L_S,
1761                                        cpu_to_le32((u32)(pages[i])));
1762                         roce_set_field(mpt_entry->mpt_byte_40,
1763                                 MPT_BYTE_40_PA1_H_M,
1764                                 MPT_BYTE_40_PA1_H_S,
1765                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1766                         break;
1767                 case 2:
1768                         roce_set_field(mpt_entry->mpt_byte_40,
1769                                        MPT_BYTE_40_PA2_L_M,
1770                                        MPT_BYTE_40_PA2_L_S,
1771                                        cpu_to_le32((u32)(pages[i])));
1772                         roce_set_field(mpt_entry->mpt_byte_44,
1773                                 MPT_BYTE_44_PA2_H_M,
1774                                 MPT_BYTE_44_PA2_H_S,
1775                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1776                         break;
1777                 case 3:
1778                         roce_set_field(mpt_entry->mpt_byte_44,
1779                                        MPT_BYTE_44_PA3_L_M,
1780                                        MPT_BYTE_44_PA3_L_S,
1781                                        cpu_to_le32((u32)(pages[i])));
1782                         roce_set_field(mpt_entry->mpt_byte_48,
1783                                 MPT_BYTE_48_PA3_H_M,
1784                                 MPT_BYTE_48_PA3_H_S,
1785                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_8)));
1786                         break;
1787                 case 4:
1788                         mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1789                         roce_set_field(mpt_entry->mpt_byte_56,
1790                                 MPT_BYTE_56_PA4_H_M,
1791                                 MPT_BYTE_56_PA4_H_S,
1792                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1793                         break;
1794                 case 5:
1795                         roce_set_field(mpt_entry->mpt_byte_56,
1796                                        MPT_BYTE_56_PA5_L_M,
1797                                        MPT_BYTE_56_PA5_L_S,
1798                                        cpu_to_le32((u32)(pages[i])));
1799                         roce_set_field(mpt_entry->mpt_byte_60,
1800                                 MPT_BYTE_60_PA5_H_M,
1801                                 MPT_BYTE_60_PA5_H_S,
1802                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1803                         break;
1804                 case 6:
1805                         roce_set_field(mpt_entry->mpt_byte_60,
1806                                        MPT_BYTE_60_PA6_L_M,
1807                                        MPT_BYTE_60_PA6_L_S,
1808                                        cpu_to_le32((u32)(pages[i])));
1809                         roce_set_field(mpt_entry->mpt_byte_64,
1810                                 MPT_BYTE_64_PA6_H_M,
1811                                 MPT_BYTE_64_PA6_H_S,
1812                                 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1813                         break;
1814                 default:
1815                         break;
1816                 }
1817         }
1818
1819         free_page((unsigned long) pages);
1820
1821         mpt_entry->pbl_addr_l = (u32)(mr->pbl_dma_addr);
1822
1823         roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1824                        MPT_BYTE_12_PBL_ADDR_H_S,
1825                        ((u32)(mr->pbl_dma_addr >> 32)));
1826
1827         return 0;
1828 }
1829
1830 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1831 {
1832         return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1833                                    n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1834 }
1835
1836 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1837 {
1838         struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1839
1840         /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1841         return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1842                 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1843 }
1844
1845 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1846 {
1847         return get_sw_cqe(hr_cq, hr_cq->cons_index);
1848 }
1849
1850 void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1851 {
1852         u32 doorbell[2];
1853
1854         doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1);
1855         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1856         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1857                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1858         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1859                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1860         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1861                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1862
1863         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1864 }
1865
1866 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1867                                    struct hns_roce_srq *srq)
1868 {
1869         struct hns_roce_cqe *cqe, *dest;
1870         u32 prod_index;
1871         int nfreed = 0;
1872         u8 owner_bit;
1873
1874         for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1875              ++prod_index) {
1876                 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1877                         break;
1878         }
1879
1880         /*
1881          * Now backwards through the CQ, removing CQ entries
1882          * that match our QP by overwriting them with next entries.
1883          */
1884         while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1885                 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1886                 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1887                                      CQE_BYTE_16_LOCAL_QPN_S) &
1888                                      HNS_ROCE_CQE_QPN_MASK) == qpn) {
1889                         /* In v1 engine, not support SRQ */
1890                         ++nfreed;
1891                 } else if (nfreed) {
1892                         dest = get_cqe(hr_cq, (prod_index + nfreed) &
1893                                        hr_cq->ib_cq.cqe);
1894                         owner_bit = roce_get_bit(dest->cqe_byte_4,
1895                                                  CQE_BYTE_4_OWNER_S);
1896                         memcpy(dest, cqe, sizeof(*cqe));
1897                         roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1898                                      owner_bit);
1899                 }
1900         }
1901
1902         if (nfreed) {
1903                 hr_cq->cons_index += nfreed;
1904                 /*
1905                  * Make sure update of buffer contents is done before
1906                  * updating consumer index.
1907                  */
1908                 wmb();
1909
1910                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
1911         }
1912 }
1913
1914 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1915                                  struct hns_roce_srq *srq)
1916 {
1917         spin_lock_irq(&hr_cq->lock);
1918         __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1919         spin_unlock_irq(&hr_cq->lock);
1920 }
1921
1922 void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1923                            struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
1924                            dma_addr_t dma_handle, int nent, u32 vector)
1925 {
1926         struct hns_roce_cq_context *cq_context = NULL;
1927         struct hns_roce_buf_list *tptr_buf;
1928         struct hns_roce_v1_priv *priv;
1929         dma_addr_t tptr_dma_addr;
1930         int offset;
1931
1932         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1933         tptr_buf = &priv->tptr_table.tptr_buf;
1934
1935         cq_context = mb_buf;
1936         memset(cq_context, 0, sizeof(*cq_context));
1937
1938         /* Get the tptr for this CQ. */
1939         offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
1940         tptr_dma_addr = tptr_buf->map + offset;
1941         hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
1942
1943         /* Register cq_context members */
1944         roce_set_field(cq_context->cqc_byte_4,
1945                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
1946                        CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
1947         roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
1948                        CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
1949         cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4);
1950
1951         cq_context->cq_bt_l = (u32)dma_handle;
1952         cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l);
1953
1954         roce_set_field(cq_context->cqc_byte_12,
1955                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
1956                        CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
1957                        ((u64)dma_handle >> 32));
1958         roce_set_field(cq_context->cqc_byte_12,
1959                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
1960                        CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
1961                        ilog2((unsigned int)nent));
1962         roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
1963                        CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
1964         cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12);
1965
1966         cq_context->cur_cqe_ba0_l = (u32)(mtts[0]);
1967         cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l);
1968
1969         roce_set_field(cq_context->cqc_byte_20,
1970                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
1971                        CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S,
1972                        cpu_to_le32((mtts[0]) >> 32));
1973         /* Dedicated hardware, directly set 0 */
1974         roce_set_field(cq_context->cqc_byte_20,
1975                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
1976                        CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
1977         /**
1978          * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1979          * using 4K page, and shift more 32 because of
1980          * caculating the high 32 bit value evaluated to hardware.
1981          */
1982         roce_set_field(cq_context->cqc_byte_20,
1983                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
1984                        CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
1985                        tptr_dma_addr >> 44);
1986         cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
1987
1988         cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
1989
1990         roce_set_field(cq_context->cqc_byte_32,
1991                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
1992                        CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
1993         roce_set_bit(cq_context->cqc_byte_32,
1994                      CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
1995         roce_set_bit(cq_context->cqc_byte_32,
1996                      CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
1997         roce_set_bit(cq_context->cqc_byte_32,
1998                      CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
1999         roce_set_bit(cq_context->cqc_byte_32,
2000                      CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2001                      0);
2002         /* The initial value of cq's ci is 0 */
2003         roce_set_field(cq_context->cqc_byte_32,
2004                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2005                        CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2006         cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
2007 }
2008
2009 int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
2010 {
2011         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2012         u32 notification_flag;
2013         u32 doorbell[2];
2014         int ret = 0;
2015
2016         notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2017                             IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2018         /*
2019          * flags = 0; Notification Flag = 1, next
2020          * flags = 1; Notification Flag = 0, solocited
2021          */
2022         doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
2023         roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2024         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2025                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2026         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2027                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2028         roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2029                        ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2030                        hr_cq->cqn | notification_flag);
2031
2032         hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2033
2034         return ret;
2035 }
2036
2037 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2038                                 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2039 {
2040         int qpn;
2041         int is_send;
2042         u16 wqe_ctr;
2043         u32 status;
2044         u32 opcode;
2045         struct hns_roce_cqe *cqe;
2046         struct hns_roce_qp *hr_qp;
2047         struct hns_roce_wq *wq;
2048         struct hns_roce_wqe_ctrl_seg *sq_wqe;
2049         struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2050         struct device *dev = &hr_dev->pdev->dev;
2051
2052         /* Find cqe according consumer index */
2053         cqe = next_cqe_sw(hr_cq);
2054         if (!cqe)
2055                 return -EAGAIN;
2056
2057         ++hr_cq->cons_index;
2058         /* Memory barrier */
2059         rmb();
2060         /* 0->SQ, 1->RQ */
2061         is_send  = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2062
2063         /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2064         if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2065                            CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2066                 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2067                                      CQE_BYTE_20_PORT_NUM_S) +
2068                       roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2069                                      CQE_BYTE_16_LOCAL_QPN_S) *
2070                                      HNS_ROCE_MAX_PORTS;
2071         } else {
2072                 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2073                                      CQE_BYTE_16_LOCAL_QPN_S);
2074         }
2075
2076         if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2077                 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2078                 if (unlikely(!hr_qp)) {
2079                         dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2080                                 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2081                         return -EINVAL;
2082                 }
2083
2084                 *cur_qp = hr_qp;
2085         }
2086
2087         wc->qp = &(*cur_qp)->ibqp;
2088         wc->vendor_err = 0;
2089
2090         status = roce_get_field(cqe->cqe_byte_4,
2091                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2092                                 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2093                                 HNS_ROCE_CQE_STATUS_MASK;
2094         switch (status) {
2095         case HNS_ROCE_CQE_SUCCESS:
2096                 wc->status = IB_WC_SUCCESS;
2097                 break;
2098         case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2099                 wc->status = IB_WC_LOC_LEN_ERR;
2100                 break;
2101         case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2102                 wc->status = IB_WC_LOC_QP_OP_ERR;
2103                 break;
2104         case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2105                 wc->status = IB_WC_LOC_PROT_ERR;
2106                 break;
2107         case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2108                 wc->status = IB_WC_WR_FLUSH_ERR;
2109                 break;
2110         case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2111                 wc->status = IB_WC_MW_BIND_ERR;
2112                 break;
2113         case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2114                 wc->status = IB_WC_BAD_RESP_ERR;
2115                 break;
2116         case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2117                 wc->status = IB_WC_LOC_ACCESS_ERR;
2118                 break;
2119         case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2120                 wc->status = IB_WC_REM_INV_REQ_ERR;
2121                 break;
2122         case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2123                 wc->status = IB_WC_REM_ACCESS_ERR;
2124                 break;
2125         case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2126                 wc->status = IB_WC_REM_OP_ERR;
2127                 break;
2128         case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2129                 wc->status = IB_WC_RETRY_EXC_ERR;
2130                 break;
2131         case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2132                 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2133                 break;
2134         default:
2135                 wc->status = IB_WC_GENERAL_ERR;
2136                 break;
2137         }
2138
2139         /* CQE status error, directly return */
2140         if (wc->status != IB_WC_SUCCESS)
2141                 return 0;
2142
2143         if (is_send) {
2144                 /* SQ conrespond to CQE */
2145                 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2146                                                 CQE_BYTE_4_WQE_INDEX_M,
2147                                                 CQE_BYTE_4_WQE_INDEX_S)&
2148                                                 ((*cur_qp)->sq.wqe_cnt-1));
2149                 switch (sq_wqe->flag & HNS_ROCE_WQE_OPCODE_MASK) {
2150                 case HNS_ROCE_WQE_OPCODE_SEND:
2151                         wc->opcode = IB_WC_SEND;
2152                         break;
2153                 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2154                         wc->opcode = IB_WC_RDMA_READ;
2155                         wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2156                         break;
2157                 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2158                         wc->opcode = IB_WC_RDMA_WRITE;
2159                         break;
2160                 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2161                         wc->opcode = IB_WC_LOCAL_INV;
2162                         break;
2163                 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2164                         wc->opcode = IB_WC_SEND;
2165                         break;
2166                 default:
2167                         wc->status = IB_WC_GENERAL_ERR;
2168                         break;
2169                 }
2170                 wc->wc_flags = (sq_wqe->flag & HNS_ROCE_WQE_IMM ?
2171                                 IB_WC_WITH_IMM : 0);
2172
2173                 wq = &(*cur_qp)->sq;
2174                 if ((*cur_qp)->sq_signal_bits) {
2175                         /*
2176                          * If sg_signal_bit is 1,
2177                          * firstly tail pointer updated to wqe
2178                          * which current cqe correspond to
2179                          */
2180                         wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2181                                                       CQE_BYTE_4_WQE_INDEX_M,
2182                                                       CQE_BYTE_4_WQE_INDEX_S);
2183                         wq->tail += (wqe_ctr - (u16)wq->tail) &
2184                                     (wq->wqe_cnt - 1);
2185                 }
2186                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2187                 ++wq->tail;
2188                 } else {
2189                 /* RQ conrespond to CQE */
2190                 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2191                 opcode = roce_get_field(cqe->cqe_byte_4,
2192                                         CQE_BYTE_4_OPERATION_TYPE_M,
2193                                         CQE_BYTE_4_OPERATION_TYPE_S) &
2194                                         HNS_ROCE_CQE_OPCODE_MASK;
2195                 switch (opcode) {
2196                 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2197                         wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2198                         wc->wc_flags = IB_WC_WITH_IMM;
2199                         wc->ex.imm_data = le32_to_cpu(cqe->immediate_data);
2200                         break;
2201                 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2202                         if (roce_get_bit(cqe->cqe_byte_4,
2203                                          CQE_BYTE_4_IMM_INDICATOR_S)) {
2204                                 wc->opcode = IB_WC_RECV;
2205                                 wc->wc_flags = IB_WC_WITH_IMM;
2206                                 wc->ex.imm_data = le32_to_cpu(
2207                                                   cqe->immediate_data);
2208                         } else {
2209                                 wc->opcode = IB_WC_RECV;
2210                                 wc->wc_flags = 0;
2211                         }
2212                         break;
2213                 default:
2214                         wc->status = IB_WC_GENERAL_ERR;
2215                         break;
2216                 }
2217
2218                 /* Update tail pointer, record wr_id */
2219                 wq = &(*cur_qp)->rq;
2220                 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2221                 ++wq->tail;
2222                 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2223                                             CQE_BYTE_20_SL_S);
2224                 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2225                                                 CQE_BYTE_20_REMOTE_QPN_M,
2226                                                 CQE_BYTE_20_REMOTE_QPN_S);
2227                 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2228                                               CQE_BYTE_20_GRH_PRESENT_S) ?
2229                                               IB_WC_GRH : 0);
2230                 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2231                                                      CQE_BYTE_28_P_KEY_IDX_M,
2232                                                      CQE_BYTE_28_P_KEY_IDX_S);
2233         }
2234
2235         return 0;
2236 }
2237
2238 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2239 {
2240         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2241         struct hns_roce_qp *cur_qp = NULL;
2242         unsigned long flags;
2243         int npolled;
2244         int ret = 0;
2245
2246         spin_lock_irqsave(&hr_cq->lock, flags);
2247
2248         for (npolled = 0; npolled < num_entries; ++npolled) {
2249                 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2250                 if (ret)
2251                         break;
2252         }
2253
2254         if (npolled) {
2255                 *hr_cq->tptr_addr = hr_cq->cons_index &
2256                         ((hr_cq->cq_depth << 1) - 1);
2257
2258                 /* Memroy barrier */
2259                 wmb();
2260                 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2261         }
2262
2263         spin_unlock_irqrestore(&hr_cq->lock, flags);
2264
2265         if (ret == 0 || ret == -EAGAIN)
2266                 return npolled;
2267         else
2268                 return ret;
2269 }
2270
2271 int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2272                 struct hns_roce_hem_table *table, int obj)
2273 {
2274         struct device *dev = &hr_dev->pdev->dev;
2275         struct hns_roce_v1_priv *priv;
2276         unsigned long end = 0, flags = 0;
2277         uint32_t bt_cmd_val[2] = {0};
2278         void __iomem *bt_cmd;
2279         u64 bt_ba = 0;
2280
2281         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
2282
2283         switch (table->type) {
2284         case HEM_TYPE_QPC:
2285                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2286                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2287                 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2288                 break;
2289         case HEM_TYPE_MTPT:
2290                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2291                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2292                 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2293                 break;
2294         case HEM_TYPE_CQC:
2295                 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2296                         ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2297                 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2298                 break;
2299         case HEM_TYPE_SRQC:
2300                 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2301                 return -EINVAL;
2302         default:
2303                 return 0;
2304         }
2305         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2306                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2307         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2308         roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2309
2310         spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2311
2312         bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2313
2314         end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2315         while (1) {
2316                 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2317                         if (!(time_before(jiffies, end))) {
2318                                 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2319                                 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2320                                         flags);
2321                                 return -EBUSY;
2322                         }
2323                 } else {
2324                         break;
2325                 }
2326                 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2327         }
2328
2329         bt_cmd_val[0] = (uint32_t)bt_ba;
2330         roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2331                 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2332         hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2333
2334         spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2335
2336         return 0;
2337 }
2338
2339 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2340                                  struct hns_roce_mtt *mtt,
2341                                  enum hns_roce_qp_state cur_state,
2342                                  enum hns_roce_qp_state new_state,
2343                                  struct hns_roce_qp_context *context,
2344                                  struct hns_roce_qp *hr_qp)
2345 {
2346         static const u16
2347         op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2348                 [HNS_ROCE_QP_STATE_RST] = {
2349                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2350                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2351                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2352                 },
2353                 [HNS_ROCE_QP_STATE_INIT] = {
2354                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2355                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2356                 /* Note: In v1 engine, HW doesn't support RST2INIT.
2357                  * We use RST2INIT cmd instead of INIT2INIT.
2358                  */
2359                 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2360                 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2361                 },
2362                 [HNS_ROCE_QP_STATE_RTR] = {
2363                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2364                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2365                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2366                 },
2367                 [HNS_ROCE_QP_STATE_RTS] = {
2368                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2369                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2370                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2371                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2372                 },
2373                 [HNS_ROCE_QP_STATE_SQD] = {
2374                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2375                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2376                 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2377                 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2378                 },
2379                 [HNS_ROCE_QP_STATE_ERR] = {
2380                 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2381                 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2382                 }
2383         };
2384
2385         struct hns_roce_cmd_mailbox *mailbox;
2386         struct device *dev = &hr_dev->pdev->dev;
2387         int ret = 0;
2388
2389         if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2390             new_state >= HNS_ROCE_QP_NUM_STATE ||
2391             !op[cur_state][new_state]) {
2392                 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2393                         cur_state, new_state);
2394                 return -EINVAL;
2395         }
2396
2397         if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2398                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2399                                          HNS_ROCE_CMD_2RST_QP,
2400                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2401
2402         if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2403                 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2404                                          HNS_ROCE_CMD_2ERR_QP,
2405                                          HNS_ROCE_CMD_TIMEOUT_MSECS);
2406
2407         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2408         if (IS_ERR(mailbox))
2409                 return PTR_ERR(mailbox);
2410
2411         memcpy(mailbox->buf, context, sizeof(*context));
2412
2413         ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2414                                 op[cur_state][new_state],
2415                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
2416
2417         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2418         return ret;
2419 }
2420
2421 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2422                              int attr_mask, enum ib_qp_state cur_state,
2423                              enum ib_qp_state new_state)
2424 {
2425         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2426         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2427         struct hns_roce_sqp_context *context;
2428         struct device *dev = &hr_dev->pdev->dev;
2429         dma_addr_t dma_handle = 0;
2430         int rq_pa_start;
2431         u32 reg_val;
2432         u64 *mtts;
2433         u32 *addr;
2434
2435         context = kzalloc(sizeof(*context), GFP_KERNEL);
2436         if (!context)
2437                 return -ENOMEM;
2438
2439         /* Search QP buf's MTTs */
2440         mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2441                                    hr_qp->mtt.first_seg, &dma_handle);
2442         if (!mtts) {
2443                 dev_err(dev, "qp buf pa find failed\n");
2444                 goto out;
2445         }
2446
2447         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2448                 roce_set_field(context->qp1c_bytes_4,
2449                                QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2450                                QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2451                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2452                 roce_set_field(context->qp1c_bytes_4,
2453                                QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2454                                QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2455                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2456                 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2457                                QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2458
2459                 context->sq_rq_bt_l = (u32)(dma_handle);
2460                 roce_set_field(context->qp1c_bytes_12,
2461                                QP1C_BYTES_12_SQ_RQ_BT_H_M,
2462                                QP1C_BYTES_12_SQ_RQ_BT_H_S,
2463                                ((u32)(dma_handle >> 32)));
2464
2465                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2466                                QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2467                 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2468                                QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2469                 roce_set_bit(context->qp1c_bytes_16,
2470                              QP1C_BYTES_16_SIGNALING_TYPE_S,
2471                              hr_qp->sq_signal_bits);
2472                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2473                              1);
2474                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2475                              1);
2476                 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2477                              0);
2478
2479                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2480                                QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2481                 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2482                                QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2483
2484                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2485                 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2486
2487                 roce_set_field(context->qp1c_bytes_28,
2488                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2489                                QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2490                                (mtts[rq_pa_start]) >> 32);
2491                 roce_set_field(context->qp1c_bytes_28,
2492                                QP1C_BYTES_28_RQ_CUR_IDX_M,
2493                                QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2494
2495                 roce_set_field(context->qp1c_bytes_32,
2496                                QP1C_BYTES_32_RX_CQ_NUM_M,
2497                                QP1C_BYTES_32_RX_CQ_NUM_S,
2498                                to_hr_cq(ibqp->recv_cq)->cqn);
2499                 roce_set_field(context->qp1c_bytes_32,
2500                                QP1C_BYTES_32_TX_CQ_NUM_M,
2501                                QP1C_BYTES_32_TX_CQ_NUM_S,
2502                                to_hr_cq(ibqp->send_cq)->cqn);
2503
2504                 context->cur_sq_wqe_ba_l  = (u32)mtts[0];
2505
2506                 roce_set_field(context->qp1c_bytes_40,
2507                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2508                                QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2509                                (mtts[0]) >> 32);
2510                 roce_set_field(context->qp1c_bytes_40,
2511                                QP1C_BYTES_40_SQ_CUR_IDX_M,
2512                                QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2513
2514                 /* Copy context to QP1C register */
2515                 addr = (u32 *)(hr_dev->reg_base + ROCEE_QP1C_CFG0_0_REG +
2516                         hr_qp->phy_port * sizeof(*context));
2517
2518                 writel(context->qp1c_bytes_4, addr);
2519                 writel(context->sq_rq_bt_l, addr + 1);
2520                 writel(context->qp1c_bytes_12, addr + 2);
2521                 writel(context->qp1c_bytes_16, addr + 3);
2522                 writel(context->qp1c_bytes_20, addr + 4);
2523                 writel(context->cur_rq_wqe_ba_l, addr + 5);
2524                 writel(context->qp1c_bytes_28, addr + 6);
2525                 writel(context->qp1c_bytes_32, addr + 7);
2526                 writel(context->cur_sq_wqe_ba_l, addr + 8);
2527                 writel(context->qp1c_bytes_40, addr + 9);
2528         }
2529
2530         /* Modify QP1C status */
2531         reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2532                             hr_qp->phy_port * sizeof(*context));
2533         roce_set_field(reg_val, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2534                        ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2535         roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2536                     hr_qp->phy_port * sizeof(*context), reg_val);
2537
2538         hr_qp->state = new_state;
2539         if (new_state == IB_QPS_RESET) {
2540                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2541                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2542                 if (ibqp->send_cq != ibqp->recv_cq)
2543                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2544                                              hr_qp->qpn, NULL);
2545
2546                 hr_qp->rq.head = 0;
2547                 hr_qp->rq.tail = 0;
2548                 hr_qp->sq.head = 0;
2549                 hr_qp->sq.tail = 0;
2550                 hr_qp->sq_next_wqe = 0;
2551         }
2552
2553         kfree(context);
2554         return 0;
2555
2556 out:
2557         kfree(context);
2558         return -EINVAL;
2559 }
2560
2561 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2562                             int attr_mask, enum ib_qp_state cur_state,
2563                             enum ib_qp_state new_state)
2564 {
2565         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2566         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2567         struct device *dev = &hr_dev->pdev->dev;
2568         struct hns_roce_qp_context *context;
2569         dma_addr_t dma_handle_2 = 0;
2570         dma_addr_t dma_handle = 0;
2571         uint32_t doorbell[2] = {0};
2572         int rq_pa_start = 0;
2573         u64 *mtts_2 = NULL;
2574         int ret = -EINVAL;
2575         u64 *mtts = NULL;
2576         int port;
2577         u8 *dmac;
2578         u8 *smac;
2579
2580         context = kzalloc(sizeof(*context), GFP_KERNEL);
2581         if (!context)
2582                 return -ENOMEM;
2583
2584         /* Search qp buf's mtts */
2585         mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2586                                    hr_qp->mtt.first_seg, &dma_handle);
2587         if (mtts == NULL) {
2588                 dev_err(dev, "qp buf pa find failed\n");
2589                 goto out;
2590         }
2591
2592         /* Search IRRL's mtts */
2593         mtts_2 = hns_roce_table_find(&hr_dev->qp_table.irrl_table, hr_qp->qpn,
2594                                      &dma_handle_2);
2595         if (mtts_2 == NULL) {
2596                 dev_err(dev, "qp irrl_table find failed\n");
2597                 goto out;
2598         }
2599
2600         /*
2601          * Reset to init
2602          *      Mandatory param:
2603          *      IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2604          *      Optional param: NA
2605          */
2606         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2607                 roce_set_field(context->qpc_bytes_4,
2608                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2609                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2610                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2611
2612                 roce_set_bit(context->qpc_bytes_4,
2613                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2614                 roce_set_bit(context->qpc_bytes_4,
2615                              QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2616                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2617                 roce_set_bit(context->qpc_bytes_4,
2618                              QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2619                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2620                              );
2621                 roce_set_bit(context->qpc_bytes_4,
2622                              QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2623                              !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2624                              );
2625                 roce_set_bit(context->qpc_bytes_4,
2626                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2627                 roce_set_field(context->qpc_bytes_4,
2628                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2629                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2630                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2631                 roce_set_field(context->qpc_bytes_4,
2632                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2633                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2634                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2635                 roce_set_field(context->qpc_bytes_4,
2636                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2637                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2638                                to_hr_pd(ibqp->pd)->pdn);
2639                 hr_qp->access_flags = attr->qp_access_flags;
2640                 roce_set_field(context->qpc_bytes_8,
2641                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2642                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2643                                to_hr_cq(ibqp->send_cq)->cqn);
2644                 roce_set_field(context->qpc_bytes_8,
2645                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2646                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2647                                to_hr_cq(ibqp->recv_cq)->cqn);
2648
2649                 if (ibqp->srq)
2650                         roce_set_field(context->qpc_bytes_12,
2651                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2652                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2653                                        to_hr_srq(ibqp->srq)->srqn);
2654
2655                 roce_set_field(context->qpc_bytes_12,
2656                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2657                                QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2658                                attr->pkey_index);
2659                 hr_qp->pkey_index = attr->pkey_index;
2660                 roce_set_field(context->qpc_bytes_16,
2661                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2662                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2663
2664         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2665                 roce_set_field(context->qpc_bytes_4,
2666                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2667                                QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2668                                to_hr_qp_type(hr_qp->ibqp.qp_type));
2669                 roce_set_bit(context->qpc_bytes_4,
2670                              QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2671                 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2672                         roce_set_bit(context->qpc_bytes_4,
2673                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2674                                      !!(attr->qp_access_flags &
2675                                      IB_ACCESS_REMOTE_READ));
2676                         roce_set_bit(context->qpc_bytes_4,
2677                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2678                                      !!(attr->qp_access_flags &
2679                                      IB_ACCESS_REMOTE_WRITE));
2680                 } else {
2681                         roce_set_bit(context->qpc_bytes_4,
2682                                      QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2683                                      !!(hr_qp->access_flags &
2684                                      IB_ACCESS_REMOTE_READ));
2685                         roce_set_bit(context->qpc_bytes_4,
2686                                      QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2687                                      !!(hr_qp->access_flags &
2688                                      IB_ACCESS_REMOTE_WRITE));
2689                 }
2690
2691                 roce_set_bit(context->qpc_bytes_4,
2692                              QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2693                 roce_set_field(context->qpc_bytes_4,
2694                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2695                                QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2696                                ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2697                 roce_set_field(context->qpc_bytes_4,
2698                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2699                                QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2700                                ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2701                 roce_set_field(context->qpc_bytes_4,
2702                                QP_CONTEXT_QPC_BYTES_4_PD_M,
2703                                QP_CONTEXT_QPC_BYTES_4_PD_S,
2704                                to_hr_pd(ibqp->pd)->pdn);
2705
2706                 roce_set_field(context->qpc_bytes_8,
2707                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2708                                QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2709                                to_hr_cq(ibqp->send_cq)->cqn);
2710                 roce_set_field(context->qpc_bytes_8,
2711                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2712                                QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2713                                to_hr_cq(ibqp->recv_cq)->cqn);
2714
2715                 if (ibqp->srq)
2716                         roce_set_field(context->qpc_bytes_12,
2717                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2718                                        QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2719                                        to_hr_srq(ibqp->srq)->srqn);
2720                 if (attr_mask & IB_QP_PKEY_INDEX)
2721                         roce_set_field(context->qpc_bytes_12,
2722                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2723                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2724                                        attr->pkey_index);
2725                 else
2726                         roce_set_field(context->qpc_bytes_12,
2727                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2728                                        QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2729                                        hr_qp->pkey_index);
2730
2731                 roce_set_field(context->qpc_bytes_16,
2732                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2733                                QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2734         } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2735                 if ((attr_mask & IB_QP_ALT_PATH) ||
2736                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2737                     (attr_mask & IB_QP_PKEY_INDEX) ||
2738                     (attr_mask & IB_QP_QKEY)) {
2739                         dev_err(dev, "INIT2RTR attr_mask error\n");
2740                         goto out;
2741                 }
2742
2743                 dmac = (u8 *)attr->ah_attr.dmac;
2744
2745                 context->sq_rq_bt_l = (u32)(dma_handle);
2746                 roce_set_field(context->qpc_bytes_24,
2747                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2748                                QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2749                                ((u32)(dma_handle >> 32)));
2750                 roce_set_bit(context->qpc_bytes_24,
2751                              QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2752                              1);
2753                 roce_set_field(context->qpc_bytes_24,
2754                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2755                                QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2756                                attr->min_rnr_timer);
2757                 context->irrl_ba_l = (u32)(dma_handle_2);
2758                 roce_set_field(context->qpc_bytes_32,
2759                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2760                                QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2761                                ((u32)(dma_handle_2 >> 32)) &
2762                                 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2763                 roce_set_field(context->qpc_bytes_32,
2764                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2765                                QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2766                 roce_set_bit(context->qpc_bytes_32,
2767                              QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2768                              1);
2769                 roce_set_bit(context->qpc_bytes_32,
2770                              QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2771                              hr_qp->sq_signal_bits);
2772
2773                 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2774                         hr_qp->port;
2775                 smac = (u8 *)hr_dev->dev_addr[port];
2776                 /* when dmac equals smac or loop_idc is 1, it should loopback */
2777                 if (ether_addr_equal_unaligned(dmac, smac) ||
2778                     hr_dev->loop_idc == 0x1)
2779                         roce_set_bit(context->qpc_bytes_32,
2780                               QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2781
2782                 roce_set_bit(context->qpc_bytes_32,
2783                              QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2784                              attr->ah_attr.ah_flags);
2785                 roce_set_field(context->qpc_bytes_32,
2786                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2787                                QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2788                                ilog2((unsigned int)attr->max_dest_rd_atomic));
2789
2790                 roce_set_field(context->qpc_bytes_36,
2791                                QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2792                                QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2793                                attr->dest_qp_num);
2794
2795                 /* Configure GID index */
2796                 roce_set_field(context->qpc_bytes_36,
2797                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2798                                QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2799                                hns_get_gid_index(hr_dev,
2800                                                  attr->ah_attr.port_num - 1,
2801                                                  attr->ah_attr.grh.sgid_index));
2802
2803                 memcpy(&(context->dmac_l), dmac, 4);
2804
2805                 roce_set_field(context->qpc_bytes_44,
2806                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2807                                QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2808                                *((u16 *)(&dmac[4])));
2809                 roce_set_field(context->qpc_bytes_44,
2810                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2811                                QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2812                                attr->ah_attr.static_rate);
2813                 roce_set_field(context->qpc_bytes_44,
2814                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2815                                QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2816                                attr->ah_attr.grh.hop_limit);
2817
2818                 roce_set_field(context->qpc_bytes_48,
2819                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2820                                QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2821                                attr->ah_attr.grh.flow_label);
2822                 roce_set_field(context->qpc_bytes_48,
2823                                QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2824                                QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2825                                attr->ah_attr.grh.traffic_class);
2826                 roce_set_field(context->qpc_bytes_48,
2827                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
2828                                QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2829
2830                 memcpy(context->dgid, attr->ah_attr.grh.dgid.raw,
2831                        sizeof(attr->ah_attr.grh.dgid.raw));
2832
2833                 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2834                         roce_get_field(context->qpc_bytes_44,
2835                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2836                                        QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2837
2838                 roce_set_field(context->qpc_bytes_68,
2839                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2840                                QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2841                                hr_qp->rq.head);
2842                 roce_set_field(context->qpc_bytes_68,
2843                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2844                                QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2845
2846                 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2847                 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2848
2849                 roce_set_field(context->qpc_bytes_76,
2850                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2851                         QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2852                         mtts[rq_pa_start] >> 32);
2853                 roce_set_field(context->qpc_bytes_76,
2854                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2855                                QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2856
2857                 context->rx_rnr_time = 0;
2858
2859                 roce_set_field(context->qpc_bytes_84,
2860                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2861                                QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2862                                attr->rq_psn - 1);
2863                 roce_set_field(context->qpc_bytes_84,
2864                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2865                                QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2866
2867                 roce_set_field(context->qpc_bytes_88,
2868                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2869                                QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2870                                attr->rq_psn);
2871                 roce_set_bit(context->qpc_bytes_88,
2872                              QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2873                 roce_set_bit(context->qpc_bytes_88,
2874                              QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2875                 roce_set_field(context->qpc_bytes_88,
2876                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2877                         QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2878                         0);
2879                 roce_set_field(context->qpc_bytes_88,
2880                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2881                                QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2882                                0);
2883
2884                 context->dma_length = 0;
2885                 context->r_key = 0;
2886                 context->va_l = 0;
2887                 context->va_h = 0;
2888
2889                 roce_set_field(context->qpc_bytes_108,
2890                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2891                                QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2892                 roce_set_bit(context->qpc_bytes_108,
2893                              QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2894                 roce_set_bit(context->qpc_bytes_108,
2895                              QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
2896
2897                 roce_set_field(context->qpc_bytes_112,
2898                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
2899                                QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
2900                 roce_set_field(context->qpc_bytes_112,
2901                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
2902                                QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
2903
2904                 /* For chip resp ack */
2905                 roce_set_field(context->qpc_bytes_156,
2906                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2907                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
2908                                hr_qp->phy_port);
2909                 roce_set_field(context->qpc_bytes_156,
2910                                QP_CONTEXT_QPC_BYTES_156_SL_M,
2911                                QP_CONTEXT_QPC_BYTES_156_SL_S, attr->ah_attr.sl);
2912                 hr_qp->sl = attr->ah_attr.sl;
2913         } else if (cur_state == IB_QPS_RTR &&
2914                 new_state == IB_QPS_RTS) {
2915                 /* If exist optional param, return error */
2916                 if ((attr_mask & IB_QP_ALT_PATH) ||
2917                     (attr_mask & IB_QP_ACCESS_FLAGS) ||
2918                     (attr_mask & IB_QP_QKEY) ||
2919                     (attr_mask & IB_QP_PATH_MIG_STATE) ||
2920                     (attr_mask & IB_QP_CUR_STATE) ||
2921                     (attr_mask & IB_QP_MIN_RNR_TIMER)) {
2922                         dev_err(dev, "RTR2RTS attr_mask error\n");
2923                         goto out;
2924                 }
2925
2926                 context->rx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
2927
2928                 roce_set_field(context->qpc_bytes_120,
2929                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
2930                                QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
2931                                (mtts[0]) >> 32);
2932
2933                 roce_set_field(context->qpc_bytes_124,
2934                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
2935                                QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
2936                 roce_set_field(context->qpc_bytes_124,
2937                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
2938                                QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
2939
2940                 roce_set_field(context->qpc_bytes_128,
2941                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
2942                                QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
2943                                attr->sq_psn);
2944                 roce_set_bit(context->qpc_bytes_128,
2945                              QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
2946                 roce_set_field(context->qpc_bytes_128,
2947                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
2948                              QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
2949                              0);
2950                 roce_set_bit(context->qpc_bytes_128,
2951                              QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
2952
2953                 roce_set_field(context->qpc_bytes_132,
2954                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
2955                                QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
2956                 roce_set_field(context->qpc_bytes_132,
2957                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
2958                                QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
2959
2960                 roce_set_field(context->qpc_bytes_136,
2961                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
2962                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
2963                                attr->sq_psn);
2964                 roce_set_field(context->qpc_bytes_136,
2965                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
2966                                QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
2967                                attr->sq_psn);
2968
2969                 roce_set_field(context->qpc_bytes_140,
2970                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
2971                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
2972                                (attr->sq_psn >> SQ_PSN_SHIFT));
2973                 roce_set_field(context->qpc_bytes_140,
2974                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
2975                                QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
2976                 roce_set_bit(context->qpc_bytes_140,
2977                              QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
2978
2979                 roce_set_field(context->qpc_bytes_148,
2980                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
2981                                QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
2982                 roce_set_field(context->qpc_bytes_148,
2983                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
2984                                QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
2985                                attr->retry_cnt);
2986                 roce_set_field(context->qpc_bytes_148,
2987                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
2988                                QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
2989                                attr->rnr_retry);
2990                 roce_set_field(context->qpc_bytes_148,
2991                                QP_CONTEXT_QPC_BYTES_148_LSN_M,
2992                                QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
2993
2994                 context->rnr_retry = 0;
2995
2996                 roce_set_field(context->qpc_bytes_156,
2997                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
2998                                QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
2999                                attr->retry_cnt);
3000                 if (attr->timeout < 0x12) {
3001                         dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3002                                  attr->timeout);
3003                         roce_set_field(context->qpc_bytes_156,
3004                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3005                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3006                                        0x12);
3007                 } else {
3008                         roce_set_field(context->qpc_bytes_156,
3009                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3010                                        QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3011                                        attr->timeout);
3012                 }
3013                 roce_set_field(context->qpc_bytes_156,
3014                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3015                                QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3016                                attr->rnr_retry);
3017                 roce_set_field(context->qpc_bytes_156,
3018                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3019                                QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3020                                hr_qp->phy_port);
3021                 roce_set_field(context->qpc_bytes_156,
3022                                QP_CONTEXT_QPC_BYTES_156_SL_M,
3023                                QP_CONTEXT_QPC_BYTES_156_SL_S, attr->ah_attr.sl);
3024                 hr_qp->sl = attr->ah_attr.sl;
3025                 roce_set_field(context->qpc_bytes_156,
3026                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3027                                QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3028                                ilog2((unsigned int)attr->max_rd_atomic));
3029                 roce_set_field(context->qpc_bytes_156,
3030                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3031                                QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3032                 context->pkt_use_len = 0;
3033
3034                 roce_set_field(context->qpc_bytes_164,
3035                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3036                                QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3037                 roce_set_field(context->qpc_bytes_164,
3038                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3039                                QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3040
3041                 roce_set_field(context->qpc_bytes_168,
3042                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3043                                QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3044                                attr->sq_psn);
3045                 roce_set_field(context->qpc_bytes_168,
3046                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3047                                QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3048                 roce_set_field(context->qpc_bytes_168,
3049                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3050                                QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3051                 roce_set_bit(context->qpc_bytes_168,
3052                              QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3053                 roce_set_bit(context->qpc_bytes_168,
3054                              QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3055                 roce_set_bit(context->qpc_bytes_168,
3056                              QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3057                 context->sge_use_len = 0;
3058
3059                 roce_set_field(context->qpc_bytes_176,
3060                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3061                                QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3062                 roce_set_field(context->qpc_bytes_176,
3063                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3064                                QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3065                                0);
3066                 roce_set_field(context->qpc_bytes_180,
3067                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3068                                QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3069                 roce_set_field(context->qpc_bytes_180,
3070                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3071                                QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3072
3073                 context->tx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
3074
3075                 roce_set_field(context->qpc_bytes_188,
3076                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3077                                QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3078                                (mtts[0]) >> 32);
3079                 roce_set_bit(context->qpc_bytes_188,
3080                              QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3081                 roce_set_field(context->qpc_bytes_188,
3082                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3083                                QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3084                                0);
3085         } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3086                    (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3087                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3088                    (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3089                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3090                    (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3091                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3092                    (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3093                 dev_err(dev, "not support this status migration\n");
3094                 goto out;
3095         }
3096
3097         /* Every status migrate must change state */
3098         roce_set_field(context->qpc_bytes_144,
3099                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3100                        QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3101
3102         /* SW pass context to HW */
3103         ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3104                                     to_hns_roce_state(cur_state),
3105                                     to_hns_roce_state(new_state), context,
3106                                     hr_qp);
3107         if (ret) {
3108                 dev_err(dev, "hns_roce_qp_modify failed\n");
3109                 goto out;
3110         }
3111
3112         /*
3113          * Use rst2init to instead of init2init with drv,
3114          * need to hw to flash RQ HEAD by DB again
3115          */
3116         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3117                 /* Memory barrier */
3118                 wmb();
3119
3120                 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3121                                RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3122                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3123                                RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3124                 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3125                                RQ_DOORBELL_U32_8_CMD_S, 1);
3126                 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3127
3128                 if (ibqp->uobject) {
3129                         hr_qp->rq.db_reg_l = hr_dev->reg_base +
3130                                      ROCEE_DB_OTHERS_L_0_REG +
3131                                      DB_REG_OFFSET * hr_dev->priv_uar.index;
3132                 }
3133
3134                 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3135         }
3136
3137         hr_qp->state = new_state;
3138
3139         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3140                 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3141         if (attr_mask & IB_QP_PORT) {
3142                 hr_qp->port = attr->port_num - 1;
3143                 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3144         }
3145
3146         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3147                 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3148                                      ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3149                 if (ibqp->send_cq != ibqp->recv_cq)
3150                         hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3151                                              hr_qp->qpn, NULL);
3152
3153                 hr_qp->rq.head = 0;
3154                 hr_qp->rq.tail = 0;
3155                 hr_qp->sq.head = 0;
3156                 hr_qp->sq.tail = 0;
3157                 hr_qp->sq_next_wqe = 0;
3158         }
3159 out:
3160         kfree(context);
3161         return ret;
3162 }
3163
3164 int hns_roce_v1_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
3165                           int attr_mask, enum ib_qp_state cur_state,
3166                           enum ib_qp_state new_state)
3167 {
3168
3169         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3170                 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3171                                          new_state);
3172         else
3173                 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3174                                         new_state);
3175 }
3176
3177 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3178 {
3179         switch (state) {
3180         case HNS_ROCE_QP_STATE_RST:
3181                 return IB_QPS_RESET;
3182         case HNS_ROCE_QP_STATE_INIT:
3183                 return IB_QPS_INIT;
3184         case HNS_ROCE_QP_STATE_RTR:
3185                 return IB_QPS_RTR;
3186         case HNS_ROCE_QP_STATE_RTS:
3187                 return IB_QPS_RTS;
3188         case HNS_ROCE_QP_STATE_SQD:
3189                 return IB_QPS_SQD;
3190         case HNS_ROCE_QP_STATE_ERR:
3191                 return IB_QPS_ERR;
3192         default:
3193                 return IB_QPS_ERR;
3194         }
3195 }
3196
3197 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3198                                  struct hns_roce_qp *hr_qp,
3199                                  struct hns_roce_qp_context *hr_context)
3200 {
3201         struct hns_roce_cmd_mailbox *mailbox;
3202         int ret;
3203
3204         mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3205         if (IS_ERR(mailbox))
3206                 return PTR_ERR(mailbox);
3207
3208         ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3209                                 HNS_ROCE_CMD_QUERY_QP,
3210                                 HNS_ROCE_CMD_TIMEOUT_MSECS);
3211         if (!ret)
3212                 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3213         else
3214                 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3215
3216         hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3217
3218         return ret;
3219 }
3220
3221 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3222                              int qp_attr_mask,
3223                              struct ib_qp_init_attr *qp_init_attr)
3224 {
3225         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3226         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3227         struct hns_roce_sqp_context context;
3228         u32 addr;
3229
3230         mutex_lock(&hr_qp->mutex);
3231
3232         if (hr_qp->state == IB_QPS_RESET) {
3233                 qp_attr->qp_state = IB_QPS_RESET;
3234                 goto done;
3235         }
3236
3237         addr = ROCEE_QP1C_CFG0_0_REG +
3238                 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3239         context.qp1c_bytes_4 = roce_read(hr_dev, addr);
3240         context.sq_rq_bt_l = roce_read(hr_dev, addr + 1);
3241         context.qp1c_bytes_12 = roce_read(hr_dev, addr + 2);
3242         context.qp1c_bytes_16 = roce_read(hr_dev, addr + 3);
3243         context.qp1c_bytes_20 = roce_read(hr_dev, addr + 4);
3244         context.cur_rq_wqe_ba_l = roce_read(hr_dev, addr + 5);
3245         context.qp1c_bytes_28 = roce_read(hr_dev, addr + 6);
3246         context.qp1c_bytes_32 = roce_read(hr_dev, addr + 7);
3247         context.cur_sq_wqe_ba_l = roce_read(hr_dev, addr + 8);
3248         context.qp1c_bytes_40 = roce_read(hr_dev, addr + 9);
3249
3250         hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3251                                       QP1C_BYTES_4_QP_STATE_M,
3252                                       QP1C_BYTES_4_QP_STATE_S);
3253         qp_attr->qp_state       = hr_qp->state;
3254         qp_attr->path_mtu       = IB_MTU_256;
3255         qp_attr->path_mig_state = IB_MIG_ARMED;
3256         qp_attr->qkey           = QKEY_VAL;
3257         qp_attr->rq_psn         = 0;
3258         qp_attr->sq_psn         = 0;
3259         qp_attr->dest_qp_num    = 1;
3260         qp_attr->qp_access_flags = 6;
3261
3262         qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3263                                              QP1C_BYTES_20_PKEY_IDX_M,
3264                                              QP1C_BYTES_20_PKEY_IDX_S);
3265         qp_attr->port_num = hr_qp->port + 1;
3266         qp_attr->sq_draining = 0;
3267         qp_attr->max_rd_atomic = 0;
3268         qp_attr->max_dest_rd_atomic = 0;
3269         qp_attr->min_rnr_timer = 0;
3270         qp_attr->timeout = 0;
3271         qp_attr->retry_cnt = 0;
3272         qp_attr->rnr_retry = 0;
3273         qp_attr->alt_timeout = 0;
3274
3275 done:
3276         qp_attr->cur_qp_state = qp_attr->qp_state;
3277         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3278         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3279         qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3280         qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3281         qp_attr->cap.max_inline_data = 0;
3282         qp_init_attr->cap = qp_attr->cap;
3283         qp_init_attr->create_flags = 0;
3284
3285         mutex_unlock(&hr_qp->mutex);
3286
3287         return 0;
3288 }
3289
3290 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3291                             int qp_attr_mask,
3292                             struct ib_qp_init_attr *qp_init_attr)
3293 {
3294         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3295         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3296         struct device *dev = &hr_dev->pdev->dev;
3297         struct hns_roce_qp_context *context;
3298         int tmp_qp_state = 0;
3299         int ret = 0;
3300         int state;
3301
3302         context = kzalloc(sizeof(*context), GFP_KERNEL);
3303         if (!context)
3304                 return -ENOMEM;
3305
3306         memset(qp_attr, 0, sizeof(*qp_attr));
3307         memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3308
3309         mutex_lock(&hr_qp->mutex);
3310
3311         if (hr_qp->state == IB_QPS_RESET) {
3312                 qp_attr->qp_state = IB_QPS_RESET;
3313                 goto done;
3314         }
3315
3316         ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3317         if (ret) {
3318                 dev_err(dev, "query qpc error\n");
3319                 ret = -EINVAL;
3320                 goto out;
3321         }
3322
3323         state = roce_get_field(context->qpc_bytes_144,
3324                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3325                                QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3326         tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3327         if (tmp_qp_state == -1) {
3328                 dev_err(dev, "to_ib_qp_state error\n");
3329                 ret = -EINVAL;
3330                 goto out;
3331         }
3332         hr_qp->state = (u8)tmp_qp_state;
3333         qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3334         qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3335                                                QP_CONTEXT_QPC_BYTES_48_MTU_M,
3336                                                QP_CONTEXT_QPC_BYTES_48_MTU_S);
3337         qp_attr->path_mig_state = IB_MIG_ARMED;
3338         if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3339                 qp_attr->qkey = QKEY_VAL;
3340
3341         qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3342                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3343                                          QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3344         qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3345                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3346                                              QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3347         qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3348                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3349                                         QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3350         qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3351                         QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3352                                    ((roce_get_bit(context->qpc_bytes_4,
3353                         QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3354                                    ((roce_get_bit(context->qpc_bytes_4,
3355                         QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3356
3357         if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3358             hr_qp->ibqp.qp_type == IB_QPT_UC) {
3359                 qp_attr->ah_attr.sl = roce_get_field(context->qpc_bytes_156,
3360                                                 QP_CONTEXT_QPC_BYTES_156_SL_M,
3361                                                 QP_CONTEXT_QPC_BYTES_156_SL_S);
3362                 qp_attr->ah_attr.grh.flow_label = roce_get_field(
3363                                         context->qpc_bytes_48,
3364                                         QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3365                                         QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3366                 qp_attr->ah_attr.grh.sgid_index = roce_get_field(
3367                                         context->qpc_bytes_36,
3368                                         QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3369                                         QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3370                 qp_attr->ah_attr.grh.hop_limit = roce_get_field(
3371                                         context->qpc_bytes_44,
3372                                         QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3373                                         QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3374                 qp_attr->ah_attr.grh.traffic_class = roce_get_field(
3375                                         context->qpc_bytes_48,
3376                                         QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3377                                         QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3378
3379                 memcpy(qp_attr->ah_attr.grh.dgid.raw, context->dgid,
3380                        sizeof(qp_attr->ah_attr.grh.dgid.raw));
3381         }
3382
3383         qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3384                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3385                               QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3386         qp_attr->port_num = hr_qp->port + 1;
3387         qp_attr->sq_draining = 0;
3388         qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156,
3389                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3390                                  QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3391         qp_attr->max_dest_rd_atomic = roce_get_field(context->qpc_bytes_32,
3392                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3393                                  QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3394         qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3395                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3396                         QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3397         qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3398                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3399                             QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3400         qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3401                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3402                              QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3403         qp_attr->rnr_retry = context->rnr_retry;
3404
3405 done:
3406         qp_attr->cur_qp_state = qp_attr->qp_state;
3407         qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3408         qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3409
3410         if (!ibqp->uobject) {
3411                 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3412                 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3413         } else {
3414                 qp_attr->cap.max_send_wr = 0;
3415                 qp_attr->cap.max_send_sge = 0;
3416         }
3417
3418         qp_init_attr->cap = qp_attr->cap;
3419
3420 out:
3421         mutex_unlock(&hr_qp->mutex);
3422         kfree(context);
3423         return ret;
3424 }
3425
3426 int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3427                          int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3428 {
3429         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3430
3431         return hr_qp->doorbell_qpn <= 1 ?
3432                 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3433                 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3434 }
3435
3436 static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3437                                       struct hns_roce_qp *hr_qp,
3438                                       u32 sdb_issue_ptr,
3439                                       u32 *sdb_inv_cnt,
3440                                       u32 *wait_stage)
3441 {
3442         struct device *dev = &hr_dev->pdev->dev;
3443         u32 sdb_retry_cnt, old_retry;
3444         u32 sdb_send_ptr, old_send;
3445         u32 success_flags = 0;
3446         u32 cur_cnt, old_cnt;
3447         unsigned long end;
3448         u32 send_ptr;
3449         u32 inv_cnt;
3450         u32 tsp_st;
3451
3452         if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3453             *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3454                 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3455                         hr_qp->qpn, *wait_stage);
3456                 return -EINVAL;
3457         }
3458
3459         /* Calculate the total timeout for the entire verification process */
3460         end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3461
3462         if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3463                 /* Query db process status, until hw process completely */
3464                 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3465                 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3466                                             ROCEE_SDB_PTR_CMP_BITS)) {
3467                         if (!time_before(jiffies, end)) {
3468                                 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3469                                         hr_qp->qpn, sdb_issue_ptr,
3470                                         sdb_send_ptr);
3471                                 return 0;
3472                         }
3473
3474                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3475                         sdb_send_ptr = roce_read(hr_dev,
3476                                                  ROCEE_SDB_SEND_PTR_REG);
3477                 }
3478
3479                 if (roce_get_field(sdb_issue_ptr,
3480                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3481                                    ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3482                     roce_get_field(sdb_send_ptr,
3483                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3484                                    ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3485                         old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3486                         old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3487
3488                         do {
3489                                 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3490                                 if (roce_get_bit(tsp_st,
3491                                         ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3492                                         *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3493                                         return 0;
3494                                 }
3495
3496                                 if (!time_before(jiffies, end)) {
3497                                         dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3498                                                      "issue 0x%x send 0x%x.\n",
3499                                                 hr_qp->qpn, sdb_issue_ptr,
3500                                                 sdb_send_ptr);
3501                                         return 0;
3502                                 }
3503
3504                                 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3505
3506                                 sdb_send_ptr = roce_read(hr_dev,
3507                                                         ROCEE_SDB_SEND_PTR_REG);
3508                                 sdb_retry_cnt = roce_read(hr_dev,
3509                                                        ROCEE_SDB_RETRY_CNT_REG);
3510                                 cur_cnt = roce_get_field(sdb_send_ptr,
3511                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3512                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3513                                         roce_get_field(sdb_retry_cnt,
3514                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3515                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3516                                 if (!roce_get_bit(tsp_st,
3517                                         ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3518                                         old_cnt = roce_get_field(old_send,
3519                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3520                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3521                                         roce_get_field(old_retry,
3522                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3523                                         ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3524                                         if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3525                                                 success_flags = 1;
3526                                 } else {
3527                                         old_cnt = roce_get_field(old_send,
3528                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3529                                         ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3530                                         if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3531                                                 success_flags = 1;
3532                                         else {
3533                                             send_ptr = roce_get_field(old_send,
3534                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3535                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3536                                             roce_get_field(sdb_retry_cnt,
3537                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3538                                             ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3539                                             roce_set_field(old_send,
3540                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3541                                             ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3542                                                 send_ptr);
3543                                         }
3544                                 }
3545                         } while (!success_flags);
3546                 }
3547
3548                 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3549
3550                 /* Get list pointer */
3551                 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3552                 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3553                         hr_qp->qpn, *sdb_inv_cnt);
3554         }
3555
3556         if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3557                 /* Query db's list status, until hw reversal */
3558                 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3559                 while (roce_hw_index_cmp_lt(inv_cnt,
3560                                             *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3561                                             ROCEE_SDB_CNT_CMP_BITS)) {
3562                         if (!time_before(jiffies, end)) {
3563                                 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3564                                         hr_qp->qpn, inv_cnt);
3565                                 return 0;
3566                         }
3567
3568                         msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3569                         inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3570                 }
3571
3572                 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3573         }
3574
3575         return 0;
3576 }
3577
3578 static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3579                                 struct hns_roce_qp *hr_qp,
3580                                 struct hns_roce_qp_work *qp_work_entry,
3581                                 int *is_timeout)
3582 {
3583         struct device *dev = &hr_dev->pdev->dev;
3584         u32 sdb_issue_ptr;
3585         int ret;
3586
3587         if (hr_qp->state != IB_QPS_RESET) {
3588                 /* Set qp to ERR, waiting for hw complete processing all dbs */
3589                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3590                                             IB_QPS_ERR);
3591                 if (ret) {
3592                         dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3593                                 hr_qp->qpn);
3594                         return ret;
3595                 }
3596
3597                 /* Record issued doorbell */
3598                 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3599                 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3600                 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3601
3602                 /* Query db process status, until hw process completely */
3603                 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3604                                                  &qp_work_entry->sdb_inv_cnt,
3605                                                  &qp_work_entry->db_wait_stage);
3606                 if (ret) {
3607                         dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3608                                 hr_qp->qpn);
3609                         return ret;
3610                 }
3611
3612                 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3613                         qp_work_entry->sche_cnt = 0;
3614                         *is_timeout = 1;
3615                         return 0;
3616                 }
3617
3618                 /* Modify qp to reset before destroying qp */
3619                 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3620                                             IB_QPS_RESET);
3621                 if (ret) {
3622                         dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3623                                 hr_qp->qpn);
3624                         return ret;
3625                 }
3626         }
3627
3628         return 0;
3629 }
3630
3631 static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3632 {
3633         struct hns_roce_qp_work *qp_work_entry;
3634         struct hns_roce_v1_priv *priv;
3635         struct hns_roce_dev *hr_dev;
3636         struct hns_roce_qp *hr_qp;
3637         struct device *dev;
3638         int ret;
3639
3640         qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3641         hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3642         dev = &hr_dev->pdev->dev;
3643         priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3644         hr_qp = qp_work_entry->qp;
3645
3646         dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", hr_qp->qpn);
3647
3648         qp_work_entry->sche_cnt++;
3649
3650         /* Query db process status, until hw process completely */
3651         ret = check_qp_db_process_status(hr_dev, hr_qp,
3652                                          qp_work_entry->sdb_issue_ptr,
3653                                          &qp_work_entry->sdb_inv_cnt,
3654                                          &qp_work_entry->db_wait_stage);
3655         if (ret) {
3656                 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3657                         hr_qp->qpn);
3658                 return;
3659         }
3660
3661         if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3662             priv->des_qp.requeue_flag) {
3663                 queue_work(priv->des_qp.qp_wq, work);
3664                 return;
3665         }
3666
3667         /* Modify qp to reset before destroying qp */
3668         ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3669                                     IB_QPS_RESET);
3670         if (ret) {
3671                 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", hr_qp->qpn);
3672                 return;
3673         }
3674
3675         hns_roce_qp_remove(hr_dev, hr_qp);
3676         hns_roce_qp_free(hr_dev, hr_qp);
3677
3678         if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3679                 /* RC QP, release QPN */
3680                 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3681                 kfree(hr_qp);
3682         } else
3683                 kfree(hr_to_hr_sqp(hr_qp));
3684
3685         kfree(qp_work_entry);
3686
3687         dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", hr_qp->qpn);
3688 }
3689
3690 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3691 {
3692         struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3693         struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3694         struct device *dev = &hr_dev->pdev->dev;
3695         struct hns_roce_qp_work qp_work_entry;
3696         struct hns_roce_qp_work *qp_work;
3697         struct hns_roce_v1_priv *priv;
3698         struct hns_roce_cq *send_cq, *recv_cq;
3699         int is_user = !!ibqp->pd->uobject;
3700         int is_timeout = 0;
3701         int ret;
3702
3703         ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3704         if (ret) {
3705                 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3706                 return ret;
3707         }
3708
3709         send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3710         recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3711
3712         hns_roce_lock_cqs(send_cq, recv_cq);
3713         if (!is_user) {
3714                 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3715                                        to_hr_srq(hr_qp->ibqp.srq) : NULL);
3716                 if (send_cq != recv_cq)
3717                         __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3718         }
3719         hns_roce_unlock_cqs(send_cq, recv_cq);
3720
3721         if (!is_timeout) {
3722                 hns_roce_qp_remove(hr_dev, hr_qp);
3723                 hns_roce_qp_free(hr_dev, hr_qp);
3724
3725                 /* RC QP, release QPN */
3726                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3727                         hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3728         }
3729
3730         hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3731
3732         if (is_user)
3733                 ib_umem_release(hr_qp->umem);
3734         else {
3735                 kfree(hr_qp->sq.wrid);
3736                 kfree(hr_qp->rq.wrid);
3737
3738                 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3739         }
3740
3741         if (!is_timeout) {
3742                 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3743                         kfree(hr_qp);
3744                 else
3745                         kfree(hr_to_hr_sqp(hr_qp));
3746         } else {
3747                 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3748                 if (!qp_work)
3749                         return -ENOMEM;
3750
3751                 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3752                 qp_work->ib_dev = &hr_dev->ib_dev;
3753                 qp_work->qp             = hr_qp;
3754                 qp_work->db_wait_stage  = qp_work_entry.db_wait_stage;
3755                 qp_work->sdb_issue_ptr  = qp_work_entry.sdb_issue_ptr;
3756                 qp_work->sdb_inv_cnt    = qp_work_entry.sdb_inv_cnt;
3757                 qp_work->sche_cnt       = qp_work_entry.sche_cnt;
3758
3759                 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3760                 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3761                 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3762         }
3763
3764         return 0;
3765 }
3766
3767 int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3768 {
3769         struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3770         struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3771         struct device *dev = &hr_dev->pdev->dev;
3772         u32 cqe_cnt_ori;
3773         u32 cqe_cnt_cur;
3774         u32 cq_buf_size;
3775         int wait_time = 0;
3776         int ret = 0;
3777
3778         hns_roce_free_cq(hr_dev, hr_cq);
3779
3780         /*
3781          * Before freeing cq buffer, we need to ensure that the outstanding CQE
3782          * have been written by checking the CQE counter.
3783          */
3784         cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3785         while (1) {
3786                 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3787                     HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3788                         break;
3789
3790                 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3791                 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3792                         break;
3793
3794                 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3795                 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3796                         dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3797                                 hr_cq->cqn);
3798                         ret = -ETIMEDOUT;
3799                         break;
3800                 }
3801                 wait_time++;
3802         }
3803
3804         hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3805
3806         if (ibcq->uobject)
3807                 ib_umem_release(hr_cq->umem);
3808         else {
3809                 /* Free the buff of stored cq */
3810                 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3811                 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3812         }
3813
3814         kfree(hr_cq);
3815
3816         return ret;
3817 }
3818
3819 struct hns_roce_v1_priv hr_v1_priv;
3820
3821 struct hns_roce_hw hns_roce_hw_v1 = {
3822         .reset = hns_roce_v1_reset,
3823         .hw_profile = hns_roce_v1_profile,
3824         .hw_init = hns_roce_v1_init,
3825         .hw_exit = hns_roce_v1_exit,
3826         .set_gid = hns_roce_v1_set_gid,
3827         .set_mac = hns_roce_v1_set_mac,
3828         .set_mtu = hns_roce_v1_set_mtu,
3829         .write_mtpt = hns_roce_v1_write_mtpt,
3830         .write_cqc = hns_roce_v1_write_cqc,
3831         .clear_hem = hns_roce_v1_clear_hem,
3832         .modify_qp = hns_roce_v1_modify_qp,
3833         .query_qp = hns_roce_v1_query_qp,
3834         .destroy_qp = hns_roce_v1_destroy_qp,
3835         .post_send = hns_roce_v1_post_send,
3836         .post_recv = hns_roce_v1_post_recv,
3837         .req_notify_cq = hns_roce_v1_req_notify_cq,
3838         .poll_cq = hns_roce_v1_poll_cq,
3839         .dereg_mr = hns_roce_v1_dereg_mr,
3840         .destroy_cq = hns_roce_v1_destroy_cq,
3841         .priv = &hr_v1_priv,
3842 };