2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/platform_device.h>
34 #include <linux/acpi.h>
35 #include <linux/etherdevice.h>
37 #include <rdma/ib_umem.h>
38 #include "hns_roce_common.h"
39 #include "hns_roce_device.h"
40 #include "hns_roce_cmd.h"
41 #include "hns_roce_hem.h"
42 #include "hns_roce_hw_v1.h"
44 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
46 dseg->lkey = cpu_to_le32(sg->lkey);
47 dseg->addr = cpu_to_le64(sg->addr);
48 dseg->len = cpu_to_le32(sg->length);
51 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
54 rseg->raddr = cpu_to_le64(remote_addr);
55 rseg->rkey = cpu_to_le32(rkey);
59 int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
60 struct ib_send_wr **bad_wr)
62 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
63 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
64 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
65 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
66 struct hns_roce_wqe_data_seg *dseg = NULL;
67 struct hns_roce_qp *qp = to_hr_qp(ibqp);
68 struct device *dev = &hr_dev->pdev->dev;
69 struct hns_roce_sq_db sq_db;
70 int ps_opcode = 0, i = 0;
71 unsigned long flags = 0;
80 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
81 ibqp->qp_type != IB_QPT_RC)) {
82 dev_err(dev, "un-supported QP type\n");
87 spin_lock_irqsave(&qp->sq.lock, flags);
88 ind = qp->sq_next_wqe;
89 for (nreq = 0; wr; ++nreq, wr = wr->next) {
90 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
96 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
97 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
98 wr->num_sge, qp->sq.max_gs);
104 wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
105 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] =
108 /* Corresponding to the RC and RD type wqe process separately */
109 if (ibqp->qp_type == IB_QPT_GSI) {
111 roce_set_field(ud_sq_wqe->dmac_h,
112 UD_SEND_WQE_U32_4_DMAC_0_M,
113 UD_SEND_WQE_U32_4_DMAC_0_S,
115 roce_set_field(ud_sq_wqe->dmac_h,
116 UD_SEND_WQE_U32_4_DMAC_1_M,
117 UD_SEND_WQE_U32_4_DMAC_1_S,
119 roce_set_field(ud_sq_wqe->dmac_h,
120 UD_SEND_WQE_U32_4_DMAC_2_M,
121 UD_SEND_WQE_U32_4_DMAC_2_S,
123 roce_set_field(ud_sq_wqe->dmac_h,
124 UD_SEND_WQE_U32_4_DMAC_3_M,
125 UD_SEND_WQE_U32_4_DMAC_3_S,
128 roce_set_field(ud_sq_wqe->u32_8,
129 UD_SEND_WQE_U32_8_DMAC_4_M,
130 UD_SEND_WQE_U32_8_DMAC_4_S,
132 roce_set_field(ud_sq_wqe->u32_8,
133 UD_SEND_WQE_U32_8_DMAC_5_M,
134 UD_SEND_WQE_U32_8_DMAC_5_S,
137 smac = (u8 *)hr_dev->dev_addr[qp->port];
138 loopback = ether_addr_equal_unaligned(ah->av.mac,
140 roce_set_bit(ud_sq_wqe->u32_8,
141 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
144 roce_set_field(ud_sq_wqe->u32_8,
145 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
146 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
147 HNS_ROCE_WQE_OPCODE_SEND);
148 roce_set_field(ud_sq_wqe->u32_8,
149 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
150 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
152 roce_set_bit(ud_sq_wqe->u32_8,
153 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
156 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
157 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
158 (wr->send_flags & IB_SEND_SOLICITED ?
159 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
160 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
161 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
163 roce_set_field(ud_sq_wqe->u32_16,
164 UD_SEND_WQE_U32_16_DEST_QP_M,
165 UD_SEND_WQE_U32_16_DEST_QP_S,
166 ud_wr(wr)->remote_qpn);
167 roce_set_field(ud_sq_wqe->u32_16,
168 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
169 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
172 roce_set_field(ud_sq_wqe->u32_36,
173 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
174 UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0);
175 roce_set_field(ud_sq_wqe->u32_36,
176 UD_SEND_WQE_U32_36_PRIORITY_M,
177 UD_SEND_WQE_U32_36_PRIORITY_S,
178 ah->av.sl_tclass_flowlabel >>
180 roce_set_field(ud_sq_wqe->u32_36,
181 UD_SEND_WQE_U32_36_SGID_INDEX_M,
182 UD_SEND_WQE_U32_36_SGID_INDEX_S,
183 hns_get_gid_index(hr_dev, qp->phy_port,
186 roce_set_field(ud_sq_wqe->u32_40,
187 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
188 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
190 roce_set_field(ud_sq_wqe->u32_40,
191 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
192 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S, 0);
194 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
196 ud_sq_wqe->va0_l = (u32)wr->sg_list[0].addr;
197 ud_sq_wqe->va0_h = (wr->sg_list[0].addr) >> 32;
198 ud_sq_wqe->l_key0 = wr->sg_list[0].lkey;
200 ud_sq_wqe->va1_l = (u32)wr->sg_list[1].addr;
201 ud_sq_wqe->va1_h = (wr->sg_list[1].addr) >> 32;
202 ud_sq_wqe->l_key1 = wr->sg_list[1].lkey;
204 } else if (ibqp->qp_type == IB_QPT_RC) {
206 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
207 for (i = 0; i < wr->num_sge; i++)
208 ctrl->msg_length += wr->sg_list[i].length;
212 ctrl->imm_data = send_ieth(wr);
214 /*Ctrl field, ctrl set type: sig, solic, imm, fence */
215 /* SO wait for conforming application scenarios */
216 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
217 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
218 (wr->send_flags & IB_SEND_SOLICITED ?
219 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
220 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
221 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
222 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
223 (wr->send_flags & IB_SEND_FENCE ?
224 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
226 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
228 switch (wr->opcode) {
229 case IB_WR_RDMA_READ:
230 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
231 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
232 atomic_wr(wr)->rkey);
234 case IB_WR_RDMA_WRITE:
235 case IB_WR_RDMA_WRITE_WITH_IMM:
236 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
237 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
238 atomic_wr(wr)->rkey);
241 case IB_WR_SEND_WITH_INV:
242 case IB_WR_SEND_WITH_IMM:
243 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
245 case IB_WR_LOCAL_INV:
247 case IB_WR_ATOMIC_CMP_AND_SWP:
248 case IB_WR_ATOMIC_FETCH_AND_ADD:
251 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
254 ctrl->flag |= cpu_to_le32(ps_opcode);
255 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
258 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
259 if (ctrl->msg_length >
260 hr_dev->caps.max_sq_inline) {
263 dev_err(dev, "inline len(1-%d)=%d, illegal",
265 hr_dev->caps.max_sq_inline);
268 for (i = 0; i < wr->num_sge; i++) {
269 memcpy(wqe, ((void *) (uintptr_t)
270 wr->sg_list[i].addr),
271 wr->sg_list[i].length);
272 wqe += wr->sg_list[i].length;
274 ctrl->flag |= HNS_ROCE_WQE_INLINE;
277 for (i = 0; i < wr->num_sge; i++)
278 set_data_seg(dseg + i, wr->sg_list + i);
280 ctrl->flag |= cpu_to_le32(wr->num_sge <<
281 HNS_ROCE_WQE_SGE_NUM_BIT);
296 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
297 SQ_DOORBELL_U32_4_SQ_HEAD_S,
298 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
299 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
300 SQ_DOORBELL_U32_4_SL_S, qp->sl);
301 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
302 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
303 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
304 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
305 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
307 doorbell[0] = sq_db.u32_4;
308 doorbell[1] = sq_db.u32_8;
310 hns_roce_write64_k(doorbell, qp->sq.db_reg_l);
311 qp->sq_next_wqe = ind;
314 spin_unlock_irqrestore(&qp->sq.lock, flags);
319 int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
320 struct ib_recv_wr **bad_wr)
327 unsigned long flags = 0;
328 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
329 struct hns_roce_wqe_data_seg *scat = NULL;
330 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
331 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
332 struct device *dev = &hr_dev->pdev->dev;
333 struct hns_roce_rq_db rq_db;
334 uint32_t doorbell[2] = {0};
336 spin_lock_irqsave(&hr_qp->rq.lock, flags);
337 ind = hr_qp->rq.head & (hr_qp->rq.wqe_cnt - 1);
339 for (nreq = 0; wr; ++nreq, wr = wr->next) {
340 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
341 hr_qp->ibqp.recv_cq)) {
347 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
348 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
349 wr->num_sge, hr_qp->rq.max_gs);
355 ctrl = get_recv_wqe(hr_qp, ind);
357 roce_set_field(ctrl->rwqe_byte_12,
358 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
359 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
362 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
364 for (i = 0; i < wr->num_sge; i++)
365 set_data_seg(scat + i, wr->sg_list + i);
367 hr_qp->rq.wrid[ind] = wr->wr_id;
369 ind = (ind + 1) & (hr_qp->rq.wqe_cnt - 1);
374 hr_qp->rq.head += nreq;
378 if (ibqp->qp_type == IB_QPT_GSI) {
379 /* SW update GSI rq header */
380 reg_val = roce_read(to_hr_dev(ibqp->device),
381 ROCEE_QP1C_CFG3_0_REG +
382 QP1C_CFGN_OFFSET * hr_qp->phy_port);
383 roce_set_field(reg_val,
384 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
385 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
387 roce_write(to_hr_dev(ibqp->device),
388 ROCEE_QP1C_CFG3_0_REG +
389 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
394 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
395 RQ_DOORBELL_U32_4_RQ_HEAD_S,
397 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
398 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
399 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
400 RQ_DOORBELL_U32_8_CMD_S, 1);
401 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
404 doorbell[0] = rq_db.u32_4;
405 doorbell[1] = rq_db.u32_8;
407 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
410 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
415 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
416 int sdb_mode, int odb_mode)
420 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
421 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
422 roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
423 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
426 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
431 /* Configure SDB/ODB extend mode */
432 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
433 roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
434 roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
435 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
438 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
444 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
445 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
446 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
447 roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
448 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
449 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
452 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
458 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
459 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
460 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
461 roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
462 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
463 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
466 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
469 struct device *dev = &hr_dev->pdev->dev;
470 struct hns_roce_v1_priv *priv;
471 struct hns_roce_db_table *db;
472 dma_addr_t sdb_dma_addr;
475 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
476 db = &priv->db_table;
478 /* Configure extend SDB threshold */
479 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
480 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
482 /* Configure extend SDB base addr */
483 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
484 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
486 /* Configure extend SDB depth */
487 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
488 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
489 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
490 db->ext_db->esdb_dep);
492 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
493 * using 4K page, and shift more 32 because of
494 * caculating the high 32 bit value evaluated to hardware.
496 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
497 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
498 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
500 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
501 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",
502 ext_sdb_alept, ext_sdb_alful);
505 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
508 struct device *dev = &hr_dev->pdev->dev;
509 struct hns_roce_v1_priv *priv;
510 struct hns_roce_db_table *db;
511 dma_addr_t odb_dma_addr;
514 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
515 db = &priv->db_table;
517 /* Configure extend ODB threshold */
518 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
519 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
521 /* Configure extend ODB base addr */
522 odb_dma_addr = db->ext_db->odb_buf_list->map;
523 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
525 /* Configure extend ODB depth */
526 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
527 roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
528 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
529 db->ext_db->eodb_dep);
530 roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
531 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
532 db->ext_db->eodb_dep);
533 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
535 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
536 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
537 ext_odb_alept, ext_odb_alful);
540 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
543 struct device *dev = &hr_dev->pdev->dev;
544 struct hns_roce_v1_priv *priv;
545 struct hns_roce_db_table *db;
546 dma_addr_t sdb_dma_addr;
547 dma_addr_t odb_dma_addr;
550 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
551 db = &priv->db_table;
553 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
558 db->ext_db->sdb_buf_list = kmalloc(
559 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
560 if (!db->ext_db->sdb_buf_list) {
562 goto ext_sdb_buf_fail_out;
565 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
566 HNS_ROCE_V1_EXT_SDB_SIZE,
567 &sdb_dma_addr, GFP_KERNEL);
568 if (!db->ext_db->sdb_buf_list->buf) {
570 goto alloc_sq_db_buf_fail;
572 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
574 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
575 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
576 HNS_ROCE_V1_EXT_SDB_ALFUL);
578 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
579 HNS_ROCE_V1_SDB_ALFUL);
582 db->ext_db->odb_buf_list = kmalloc(
583 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
584 if (!db->ext_db->odb_buf_list) {
586 goto ext_odb_buf_fail_out;
589 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
590 HNS_ROCE_V1_EXT_ODB_SIZE,
591 &odb_dma_addr, GFP_KERNEL);
592 if (!db->ext_db->odb_buf_list->buf) {
594 goto alloc_otr_db_buf_fail;
596 db->ext_db->odb_buf_list->map = odb_dma_addr;
598 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
599 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
600 HNS_ROCE_V1_EXT_ODB_ALFUL);
602 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
603 HNS_ROCE_V1_ODB_ALFUL);
605 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
609 alloc_otr_db_buf_fail:
610 kfree(db->ext_db->odb_buf_list);
612 ext_odb_buf_fail_out:
614 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
615 db->ext_db->sdb_buf_list->buf,
616 db->ext_db->sdb_buf_list->map);
619 alloc_sq_db_buf_fail:
621 kfree(db->ext_db->sdb_buf_list);
623 ext_sdb_buf_fail_out:
628 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
631 struct device *dev = &hr_dev->pdev->dev;
632 struct ib_qp_init_attr init_attr;
635 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
636 init_attr.qp_type = IB_QPT_RC;
637 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
638 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
639 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
641 qp = hns_roce_create_qp(pd, &init_attr, NULL);
643 dev_err(dev, "Create loop qp for mr free failed!");
650 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
652 struct hns_roce_caps *caps = &hr_dev->caps;
653 struct device *dev = &hr_dev->pdev->dev;
654 struct ib_cq_init_attr cq_init_attr;
655 struct hns_roce_free_mr *free_mr;
656 struct ib_qp_attr attr = { 0 };
657 struct hns_roce_v1_priv *priv;
658 struct hns_roce_qp *hr_qp;
668 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
669 free_mr = &priv->free_mr;
671 /* Reserved cq for loop qp */
672 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
673 cq_init_attr.comp_vector = 0;
674 cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
676 dev_err(dev, "Create cq for reseved loop qp failed!");
679 free_mr->mr_free_cq = to_hr_cq(cq);
680 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
681 free_mr->mr_free_cq->ib_cq.uobject = NULL;
682 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
683 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
684 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
685 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
687 pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
689 dev_err(dev, "Create pd for reseved loop qp failed!");
691 goto alloc_pd_failed;
693 free_mr->mr_free_pd = to_hr_pd(pd);
694 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
695 free_mr->mr_free_pd->ibpd.uobject = NULL;
696 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
698 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
700 attr.min_rnr_timer = 0;
701 /* Disable read ability */
702 attr.max_dest_rd_atomic = 0;
703 attr.max_rd_atomic = 0;
704 /* Use arbitrary values as rq_psn and sq_psn */
705 attr.rq_psn = 0x0808;
706 attr.sq_psn = 0x0808;
710 attr.path_mtu = IB_MTU_256;
711 attr.ah_attr.ah_flags = 1;
712 attr.ah_attr.static_rate = 3;
713 attr.ah_attr.grh.sgid_index = 0;
714 attr.ah_attr.grh.hop_limit = 1;
715 attr.ah_attr.grh.flow_label = 0;
716 attr.ah_attr.grh.traffic_class = 0;
718 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
719 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
720 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
721 if (IS_ERR(free_mr->mr_free_qp[i])) {
722 dev_err(dev, "Create loop qp failed!\n");
723 goto create_lp_qp_failed;
725 hr_qp = free_mr->mr_free_qp[i];
727 sl = i / caps->num_ports;
729 if (caps->num_ports == HNS_ROCE_MAX_PORTS)
730 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
731 (i % caps->num_ports);
733 phy_port = i % caps->num_ports;
735 hr_qp->port = phy_port + 1;
736 hr_qp->phy_port = phy_port;
737 hr_qp->ibqp.qp_type = IB_QPT_RC;
738 hr_qp->ibqp.device = &hr_dev->ib_dev;
739 hr_qp->ibqp.uobject = NULL;
740 atomic_set(&hr_qp->ibqp.usecnt, 0);
742 hr_qp->ibqp.recv_cq = cq;
743 hr_qp->ibqp.send_cq = cq;
745 attr.ah_attr.port_num = phy_port + 1;
746 attr.ah_attr.sl = sl;
747 attr.port_num = phy_port + 1;
749 attr.dest_qp_num = hr_qp->qpn;
750 memcpy(attr.ah_attr.dmac, hr_dev->dev_addr[phy_port],
753 memcpy(attr.ah_attr.grh.dgid.raw,
754 &subnet_prefix, sizeof(u64));
755 memcpy(&attr.ah_attr.grh.dgid.raw[8],
756 hr_dev->dev_addr[phy_port], 3);
757 memcpy(&attr.ah_attr.grh.dgid.raw[13],
758 hr_dev->dev_addr[phy_port] + 3, 3);
759 attr.ah_attr.grh.dgid.raw[11] = 0xff;
760 attr.ah_attr.grh.dgid.raw[12] = 0xfe;
761 attr.ah_attr.grh.dgid.raw[8] ^= 2;
763 attr_mask |= IB_QP_PORT;
765 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
766 IB_QPS_RESET, IB_QPS_INIT);
768 dev_err(dev, "modify qp failed(%d)!\n", ret);
769 goto create_lp_qp_failed;
772 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
773 IB_QPS_INIT, IB_QPS_RTR);
775 dev_err(dev, "modify qp failed(%d)!\n", ret);
776 goto create_lp_qp_failed;
779 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
780 IB_QPS_RTR, IB_QPS_RTS);
782 dev_err(dev, "modify qp failed(%d)!\n", ret);
783 goto create_lp_qp_failed;
790 for (i -= 1; i >= 0; i--) {
791 hr_qp = free_mr->mr_free_qp[i];
792 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
793 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
796 if (hns_roce_dealloc_pd(pd))
797 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
800 if (hns_roce_ib_destroy_cq(cq))
801 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
806 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
808 struct device *dev = &hr_dev->pdev->dev;
809 struct hns_roce_free_mr *free_mr;
810 struct hns_roce_v1_priv *priv;
811 struct hns_roce_qp *hr_qp;
815 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
816 free_mr = &priv->free_mr;
818 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
819 hr_qp = free_mr->mr_free_qp[i];
820 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
822 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
826 ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
828 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
830 ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
832 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
835 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
837 struct device *dev = &hr_dev->pdev->dev;
838 struct hns_roce_v1_priv *priv;
839 struct hns_roce_db_table *db;
846 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
847 db = &priv->db_table;
849 memset(db, 0, sizeof(*db));
851 /* Default DB mode */
852 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
853 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
854 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
855 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
857 db->sdb_ext_mod = sdb_ext_mod;
858 db->odb_ext_mod = odb_ext_mod;
861 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
863 dev_err(dev, "Failed in extend DB configuration.\n");
867 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
872 void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
874 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
875 struct hns_roce_dev *hr_dev;
877 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
879 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
881 hns_roce_v1_release_lp_qp(hr_dev);
883 if (hns_roce_v1_rsv_lp_qp(hr_dev))
884 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
886 if (lp_qp_work->comp_flag)
887 complete(lp_qp_work->comp);
892 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
894 struct device *dev = &hr_dev->pdev->dev;
895 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
896 struct hns_roce_free_mr *free_mr;
897 struct hns_roce_v1_priv *priv;
898 struct completion comp;
900 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
902 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
903 free_mr = &priv->free_mr;
905 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
908 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
910 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
911 lp_qp_work->comp = ∁
912 lp_qp_work->comp_flag = 1;
914 init_completion(lp_qp_work->comp);
916 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
918 while (time_before_eq(jiffies, end)) {
919 if (try_wait_for_completion(&comp))
921 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
924 lp_qp_work->comp_flag = 0;
925 if (try_wait_for_completion(&comp))
928 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
932 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
934 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
935 struct device *dev = &hr_dev->pdev->dev;
936 struct ib_send_wr send_wr, *bad_wr;
939 memset(&send_wr, 0, sizeof(send_wr));
942 send_wr.send_flags = 0;
943 send_wr.sg_list = NULL;
944 send_wr.wr_id = (unsigned long long)&send_wr;
945 send_wr.opcode = IB_WR_RDMA_WRITE;
947 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
949 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
956 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
958 struct hns_roce_mr_free_work *mr_work;
959 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
960 struct hns_roce_free_mr *free_mr;
961 struct hns_roce_cq *mr_free_cq;
962 struct hns_roce_v1_priv *priv;
963 struct hns_roce_dev *hr_dev;
964 struct hns_roce_mr *hr_mr;
965 struct hns_roce_qp *hr_qp;
968 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
973 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
974 hr_mr = (struct hns_roce_mr *)mr_work->mr;
975 hr_dev = to_hr_dev(mr_work->ib_dev);
976 dev = &hr_dev->pdev->dev;
978 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
979 free_mr = &priv->free_mr;
980 mr_free_cq = free_mr->mr_free_cq;
982 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
983 hr_qp = free_mr->mr_free_qp[i];
984 ret = hns_roce_v1_send_lp_wqe(hr_qp);
987 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
993 ne = HNS_ROCE_V1_RESV_QP;
995 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
998 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
999 hr_qp->qpn, ret, hr_mr->key, ne);
1003 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1004 } while (ne && time_before_eq(jiffies, end));
1008 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1012 if (mr_work->comp_flag)
1013 complete(mr_work->comp);
1017 int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
1019 struct device *dev = &hr_dev->pdev->dev;
1020 struct hns_roce_mr_free_work *mr_work;
1021 struct hns_roce_free_mr *free_mr;
1022 struct hns_roce_v1_priv *priv;
1023 struct completion comp;
1025 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1026 unsigned long start = jiffies;
1030 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1031 free_mr = &priv->free_mr;
1034 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1035 & (hr_dev->caps.num_mtpts - 1)))
1036 dev_warn(dev, "HW2SW_MPT failed!\n");
1039 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1045 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1047 mr_work->ib_dev = &(hr_dev->ib_dev);
1048 mr_work->comp = ∁
1049 mr_work->comp_flag = 1;
1050 mr_work->mr = (void *)mr;
1051 init_completion(mr_work->comp);
1053 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1055 while (time_before_eq(jiffies, end)) {
1056 if (try_wait_for_completion(&comp))
1058 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1061 mr_work->comp_flag = 0;
1062 if (try_wait_for_completion(&comp))
1065 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1069 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1070 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1072 if (mr->size != ~0ULL) {
1073 npages = ib_umem_page_count(mr->umem);
1074 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1078 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1079 key_to_hw_index(mr->key), 0);
1082 ib_umem_release(mr->umem);
1089 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1091 struct device *dev = &hr_dev->pdev->dev;
1092 struct hns_roce_v1_priv *priv;
1093 struct hns_roce_db_table *db;
1095 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1096 db = &priv->db_table;
1098 if (db->sdb_ext_mod) {
1099 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1100 db->ext_db->sdb_buf_list->buf,
1101 db->ext_db->sdb_buf_list->map);
1102 kfree(db->ext_db->sdb_buf_list);
1105 if (db->odb_ext_mod) {
1106 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1107 db->ext_db->odb_buf_list->buf,
1108 db->ext_db->odb_buf_list->map);
1109 kfree(db->ext_db->odb_buf_list);
1115 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1121 struct hns_roce_v1_priv *priv;
1122 struct hns_roce_raq_table *raq;
1123 struct device *dev = &hr_dev->pdev->dev;
1125 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1126 raq = &priv->raq_table;
1128 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1129 if (!raq->e_raq_buf)
1132 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1134 if (!raq->e_raq_buf->buf) {
1136 goto err_dma_alloc_raq;
1138 raq->e_raq_buf->map = addr;
1140 /* Configure raq extended address. 48bit 4K align*/
1141 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1143 /* Configure raq_shift */
1144 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1145 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1146 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1147 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1149 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1150 * using 4K page, and shift more 32 because of
1151 * caculating the high 32 bit value evaluated to hardware.
1153 roce_set_field(val, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1154 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1155 raq->e_raq_buf->map >> 44);
1156 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1157 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1159 /* Configure raq threshold */
1160 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1161 roce_set_field(val, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1162 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1163 HNS_ROCE_V1_EXT_RAQ_WF);
1164 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1165 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1167 /* Enable extend raq */
1168 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1170 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1171 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1172 POL_TIME_INTERVAL_VAL);
1173 roce_set_bit(val, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1175 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1176 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1179 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1180 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1181 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1183 /* Enable raq drop */
1184 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1185 roce_set_bit(val, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1186 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1187 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1192 kfree(raq->e_raq_buf);
1196 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1198 struct device *dev = &hr_dev->pdev->dev;
1199 struct hns_roce_v1_priv *priv;
1200 struct hns_roce_raq_table *raq;
1202 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1203 raq = &priv->raq_table;
1205 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1206 raq->e_raq_buf->map);
1207 kfree(raq->e_raq_buf);
1210 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1215 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1216 /* Open all ports */
1217 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1218 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1220 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1222 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1223 /* Close all ports */
1224 roce_set_field(val, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1225 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1226 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1230 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1232 struct device *dev = &hr_dev->pdev->dev;
1233 struct hns_roce_v1_priv *priv;
1236 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1238 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1239 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1241 if (!priv->bt_table.qpc_buf.buf)
1244 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1245 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1247 if (!priv->bt_table.mtpt_buf.buf) {
1249 goto err_failed_alloc_mtpt_buf;
1252 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1253 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1255 if (!priv->bt_table.cqc_buf.buf) {
1257 goto err_failed_alloc_cqc_buf;
1262 err_failed_alloc_cqc_buf:
1263 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1264 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1266 err_failed_alloc_mtpt_buf:
1267 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1268 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1273 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1275 struct device *dev = &hr_dev->pdev->dev;
1276 struct hns_roce_v1_priv *priv;
1278 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1280 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1281 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1283 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1284 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1286 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1287 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1290 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1292 struct device *dev = &hr_dev->pdev->dev;
1293 struct hns_roce_buf_list *tptr_buf;
1294 struct hns_roce_v1_priv *priv;
1296 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1297 tptr_buf = &priv->tptr_table.tptr_buf;
1300 * This buffer will be used for CQ's tptr(tail pointer), also
1301 * named ci(customer index). Every CQ will use 2 bytes to save
1302 * cqe ci in hip06. Hardware will read this area to get new ci
1303 * when the queue is almost full.
1305 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1306 &tptr_buf->map, GFP_KERNEL);
1310 hr_dev->tptr_dma_addr = tptr_buf->map;
1311 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1316 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1318 struct device *dev = &hr_dev->pdev->dev;
1319 struct hns_roce_buf_list *tptr_buf;
1320 struct hns_roce_v1_priv *priv;
1322 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1323 tptr_buf = &priv->tptr_table.tptr_buf;
1325 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1326 tptr_buf->buf, tptr_buf->map);
1329 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1331 struct device *dev = &hr_dev->pdev->dev;
1332 struct hns_roce_free_mr *free_mr;
1333 struct hns_roce_v1_priv *priv;
1336 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1337 free_mr = &priv->free_mr;
1339 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1340 if (!free_mr->free_mr_wq) {
1341 dev_err(dev, "Create free mr workqueue failed!\n");
1345 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1347 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1348 flush_workqueue(free_mr->free_mr_wq);
1349 destroy_workqueue(free_mr->free_mr_wq);
1355 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1357 struct hns_roce_free_mr *free_mr;
1358 struct hns_roce_v1_priv *priv;
1360 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1361 free_mr = &priv->free_mr;
1363 flush_workqueue(free_mr->free_mr_wq);
1364 destroy_workqueue(free_mr->free_mr_wq);
1366 hns_roce_v1_release_lp_qp(hr_dev);
1370 * hns_roce_v1_reset - reset RoCE
1371 * @hr_dev: RoCE device struct pointer
1372 * @enable: true -- drop reset, false -- reset
1373 * return 0 - success , negative --fail
1375 int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1377 struct device_node *dsaf_node;
1378 struct device *dev = &hr_dev->pdev->dev;
1379 struct device_node *np = dev->of_node;
1380 struct fwnode_handle *fwnode;
1383 /* check if this is DT/ACPI case */
1384 if (dev_of_node(dev)) {
1385 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1387 dev_err(dev, "could not find dsaf-handle\n");
1390 fwnode = &dsaf_node->fwnode;
1391 } else if (is_acpi_device_node(dev->fwnode)) {
1392 struct acpi_reference_args args;
1394 ret = acpi_node_get_property_reference(dev->fwnode,
1395 "dsaf-handle", 0, &args);
1397 dev_err(dev, "could not find dsaf-handle\n");
1400 fwnode = acpi_fwnode_handle(args.adev);
1402 dev_err(dev, "cannot read data from DT or ACPI\n");
1406 ret = hns_dsaf_roce_reset(fwnode, false);
1411 msleep(SLEEP_TIME_INTERVAL);
1412 ret = hns_dsaf_roce_reset(fwnode, true);
1418 static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1420 struct device *dev = &hr_dev->pdev->dev;
1421 struct hns_roce_v1_priv *priv;
1422 struct hns_roce_des_qp *des_qp;
1424 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1425 des_qp = &priv->des_qp;
1427 des_qp->requeue_flag = 1;
1428 des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1429 if (!des_qp->qp_wq) {
1430 dev_err(dev, "Create destroy qp workqueue failed!\n");
1437 static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1439 struct hns_roce_v1_priv *priv;
1440 struct hns_roce_des_qp *des_qp;
1442 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1443 des_qp = &priv->des_qp;
1445 des_qp->requeue_flag = 0;
1446 flush_workqueue(des_qp->qp_wq);
1447 destroy_workqueue(des_qp->qp_wq);
1450 void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1453 struct hns_roce_caps *caps = &hr_dev->caps;
1455 hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG));
1456 hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev,
1457 ROCEE_VENDOR_PART_ID_REG));
1458 hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev,
1459 ROCEE_SYS_IMAGE_GUID_L_REG)) |
1460 ((u64)le32_to_cpu(roce_read(hr_dev,
1461 ROCEE_SYS_IMAGE_GUID_H_REG)) << 32);
1462 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
1464 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1465 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1466 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1467 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1468 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1469 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1470 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1471 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1472 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1473 caps->num_aeq_vectors = HNS_ROCE_AEQE_VEC_NUM;
1474 caps->num_comp_vectors = HNS_ROCE_COMP_VEC_NUM;
1475 caps->num_other_vectors = HNS_ROCE_AEQE_OF_VEC_NUM;
1476 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1477 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1478 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1479 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1480 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1481 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1482 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1483 caps->qpc_entry_sz = HNS_ROCE_V1_QPC_ENTRY_SIZE;
1484 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1485 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1486 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1487 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1488 caps->cq_entry_sz = HNS_ROCE_V1_CQE_ENTRY_SIZE;
1489 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1490 caps->reserved_lkey = 0;
1491 caps->reserved_pds = 0;
1492 caps->reserved_mrws = 1;
1493 caps->reserved_uars = 0;
1494 caps->reserved_cqs = 0;
1496 for (i = 0; i < caps->num_ports; i++)
1497 caps->pkey_table_len[i] = 1;
1499 for (i = 0; i < caps->num_ports; i++) {
1500 /* Six ports shared 16 GID in v1 engine */
1501 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1502 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1505 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1506 caps->num_ports + 1;
1509 for (i = 0; i < caps->num_comp_vectors; i++)
1510 caps->ceqe_depth[i] = HNS_ROCE_V1_NUM_COMP_EQE;
1512 caps->aeqe_depth = HNS_ROCE_V1_NUM_ASYNC_EQE;
1513 caps->local_ca_ack_delay = le32_to_cpu(roce_read(hr_dev,
1514 ROCEE_ACK_DELAY_REG));
1515 caps->max_mtu = IB_MTU_2048;
1518 int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1522 struct device *dev = &hr_dev->pdev->dev;
1524 /* DMAE user config */
1525 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1526 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1527 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1528 roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1529 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1530 1 << PAGES_SHIFT_16);
1531 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1533 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1534 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1535 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1536 roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1537 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1538 1 << PAGES_SHIFT_16);
1540 ret = hns_roce_db_init(hr_dev);
1542 dev_err(dev, "doorbell init failed!\n");
1546 ret = hns_roce_raq_init(hr_dev);
1548 dev_err(dev, "raq init failed!\n");
1549 goto error_failed_raq_init;
1552 ret = hns_roce_bt_init(hr_dev);
1554 dev_err(dev, "bt init failed!\n");
1555 goto error_failed_bt_init;
1558 ret = hns_roce_tptr_init(hr_dev);
1560 dev_err(dev, "tptr init failed!\n");
1561 goto error_failed_tptr_init;
1564 ret = hns_roce_des_qp_init(hr_dev);
1566 dev_err(dev, "des qp init failed!\n");
1567 goto error_failed_des_qp_init;
1570 ret = hns_roce_free_mr_init(hr_dev);
1572 dev_err(dev, "free mr init failed!\n");
1573 goto error_failed_free_mr_init;
1576 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1580 error_failed_free_mr_init:
1581 hns_roce_des_qp_free(hr_dev);
1583 error_failed_des_qp_init:
1584 hns_roce_tptr_free(hr_dev);
1586 error_failed_tptr_init:
1587 hns_roce_bt_free(hr_dev);
1589 error_failed_bt_init:
1590 hns_roce_raq_free(hr_dev);
1592 error_failed_raq_init:
1593 hns_roce_db_free(hr_dev);
1597 void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1599 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1600 hns_roce_free_mr_free(hr_dev);
1601 hns_roce_des_qp_free(hr_dev);
1602 hns_roce_tptr_free(hr_dev);
1603 hns_roce_bt_free(hr_dev);
1604 hns_roce_raq_free(hr_dev);
1605 hns_roce_db_free(hr_dev);
1608 void hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
1614 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1616 p = (u32 *)&gid->raw[0];
1617 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1618 (HNS_ROCE_V1_GID_NUM * gid_idx));
1620 p = (u32 *)&gid->raw[4];
1621 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1622 (HNS_ROCE_V1_GID_NUM * gid_idx));
1624 p = (u32 *)&gid->raw[8];
1625 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1626 (HNS_ROCE_V1_GID_NUM * gid_idx));
1628 p = (u32 *)&gid->raw[0xc];
1629 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1630 (HNS_ROCE_V1_GID_NUM * gid_idx));
1633 void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1642 * When mac changed, loopback may fail
1643 * because of smac not equal to dmac.
1644 * We Need to release and create reserved qp again.
1646 if (hr_dev->hw->dereg_mr && hns_roce_v1_recreate_lp_qp(hr_dev))
1647 dev_warn(&hr_dev->pdev->dev, "recreate lp qp timeout!\n");
1649 p = (u32 *)(&addr[0]);
1651 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1652 PHY_PORT_OFFSET * phy_port);
1654 val = roce_read(hr_dev,
1655 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1656 p_h = (u16 *)(&addr[4]);
1658 roce_set_field(val, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1659 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1660 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1664 void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1669 val = roce_read(hr_dev,
1670 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1671 roce_set_field(val, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1672 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1673 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1677 int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr,
1678 unsigned long mtpt_idx)
1680 struct hns_roce_v1_mpt_entry *mpt_entry;
1681 struct scatterlist *sg;
1686 /* MPT filled into mailbox buf */
1687 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1688 memset(mpt_entry, 0, sizeof(*mpt_entry));
1690 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1691 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1692 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1693 MPT_BYTE_4_KEY_S, mr->key);
1694 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1695 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1696 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1697 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1698 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1699 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1700 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1701 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1702 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1703 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1704 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1705 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1706 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1707 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1708 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1709 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1711 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1713 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1714 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1715 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1716 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1718 mpt_entry->virt_addr_l = (u32)mr->iova;
1719 mpt_entry->virt_addr_h = (u32)(mr->iova >> 32);
1720 mpt_entry->length = (u32)mr->size;
1722 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1723 MPT_BYTE_28_PD_S, mr->pd);
1724 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1725 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1726 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1727 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1729 /* DMA momery regsiter */
1730 if (mr->type == MR_TYPE_DMA)
1733 pages = (u64 *) __get_free_page(GFP_KERNEL);
1738 for_each_sg(mr->umem->sg_head.sgl, sg, mr->umem->nmap, entry) {
1739 pages[i] = ((u64)sg_dma_address(sg)) >> 12;
1741 /* Directly record to MTPT table firstly 7 entry */
1742 if (i >= HNS_ROCE_MAX_INNER_MTPT_NUM)
1747 /* Register user mr */
1748 for (i = 0; i < HNS_ROCE_MAX_INNER_MTPT_NUM; i++) {
1751 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1752 roce_set_field(mpt_entry->mpt_byte_36,
1753 MPT_BYTE_36_PA0_H_M,
1754 MPT_BYTE_36_PA0_H_S,
1755 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1758 roce_set_field(mpt_entry->mpt_byte_36,
1759 MPT_BYTE_36_PA1_L_M,
1760 MPT_BYTE_36_PA1_L_S,
1761 cpu_to_le32((u32)(pages[i])));
1762 roce_set_field(mpt_entry->mpt_byte_40,
1763 MPT_BYTE_40_PA1_H_M,
1764 MPT_BYTE_40_PA1_H_S,
1765 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1768 roce_set_field(mpt_entry->mpt_byte_40,
1769 MPT_BYTE_40_PA2_L_M,
1770 MPT_BYTE_40_PA2_L_S,
1771 cpu_to_le32((u32)(pages[i])));
1772 roce_set_field(mpt_entry->mpt_byte_44,
1773 MPT_BYTE_44_PA2_H_M,
1774 MPT_BYTE_44_PA2_H_S,
1775 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1778 roce_set_field(mpt_entry->mpt_byte_44,
1779 MPT_BYTE_44_PA3_L_M,
1780 MPT_BYTE_44_PA3_L_S,
1781 cpu_to_le32((u32)(pages[i])));
1782 roce_set_field(mpt_entry->mpt_byte_48,
1783 MPT_BYTE_48_PA3_H_M,
1784 MPT_BYTE_48_PA3_H_S,
1785 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_8)));
1788 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1789 roce_set_field(mpt_entry->mpt_byte_56,
1790 MPT_BYTE_56_PA4_H_M,
1791 MPT_BYTE_56_PA4_H_S,
1792 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32)));
1795 roce_set_field(mpt_entry->mpt_byte_56,
1796 MPT_BYTE_56_PA5_L_M,
1797 MPT_BYTE_56_PA5_L_S,
1798 cpu_to_le32((u32)(pages[i])));
1799 roce_set_field(mpt_entry->mpt_byte_60,
1800 MPT_BYTE_60_PA5_H_M,
1801 MPT_BYTE_60_PA5_H_S,
1802 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24)));
1805 roce_set_field(mpt_entry->mpt_byte_60,
1806 MPT_BYTE_60_PA6_L_M,
1807 MPT_BYTE_60_PA6_L_S,
1808 cpu_to_le32((u32)(pages[i])));
1809 roce_set_field(mpt_entry->mpt_byte_64,
1810 MPT_BYTE_64_PA6_H_M,
1811 MPT_BYTE_64_PA6_H_S,
1812 cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16)));
1819 free_page((unsigned long) pages);
1821 mpt_entry->pbl_addr_l = (u32)(mr->pbl_dma_addr);
1823 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1824 MPT_BYTE_12_PBL_ADDR_H_S,
1825 ((u32)(mr->pbl_dma_addr >> 32)));
1830 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1832 return hns_roce_buf_offset(&hr_cq->hr_buf.hr_buf,
1833 n * HNS_ROCE_V1_CQE_ENTRY_SIZE);
1836 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1838 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1840 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1841 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1842 !!(n & (hr_cq->ib_cq.cqe + 1))) ? hr_cqe : NULL;
1845 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1847 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1850 void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
1854 doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1);
1856 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1857 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
1858 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
1859 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
1860 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
1861 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
1862 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
1864 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
1867 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1868 struct hns_roce_srq *srq)
1870 struct hns_roce_cqe *cqe, *dest;
1875 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
1877 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
1882 * Now backwards through the CQ, removing CQ entries
1883 * that match our QP by overwriting them with next entries.
1885 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1886 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1887 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
1888 CQE_BYTE_16_LOCAL_QPN_S) &
1889 HNS_ROCE_CQE_QPN_MASK) == qpn) {
1890 /* In v1 engine, not support SRQ */
1892 } else if (nfreed) {
1893 dest = get_cqe(hr_cq, (prod_index + nfreed) &
1895 owner_bit = roce_get_bit(dest->cqe_byte_4,
1896 CQE_BYTE_4_OWNER_S);
1897 memcpy(dest, cqe, sizeof(*cqe));
1898 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
1904 hr_cq->cons_index += nfreed;
1906 * Make sure update of buffer contents is done before
1907 * updating consumer index.
1911 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
1915 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1916 struct hns_roce_srq *srq)
1918 spin_lock_irq(&hr_cq->lock);
1919 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
1920 spin_unlock_irq(&hr_cq->lock);
1923 void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1924 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
1925 dma_addr_t dma_handle, int nent, u32 vector)
1927 struct hns_roce_cq_context *cq_context = NULL;
1928 struct hns_roce_buf_list *tptr_buf;
1929 struct hns_roce_v1_priv *priv;
1930 dma_addr_t tptr_dma_addr;
1933 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1934 tptr_buf = &priv->tptr_table.tptr_buf;
1936 cq_context = mb_buf;
1937 memset(cq_context, 0, sizeof(*cq_context));
1939 /* Get the tptr for this CQ. */
1940 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
1941 tptr_dma_addr = tptr_buf->map + offset;
1942 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
1944 /* Register cq_context members */
1945 roce_set_field(cq_context->cqc_byte_4,
1946 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
1947 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
1948 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
1949 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
1950 cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4);
1952 cq_context->cq_bt_l = (u32)dma_handle;
1953 cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l);
1955 roce_set_field(cq_context->cqc_byte_12,
1956 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
1957 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
1958 ((u64)dma_handle >> 32));
1959 roce_set_field(cq_context->cqc_byte_12,
1960 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
1961 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
1962 ilog2((unsigned int)nent));
1963 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
1964 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector);
1965 cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12);
1967 cq_context->cur_cqe_ba0_l = (u32)(mtts[0]);
1968 cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l);
1970 roce_set_field(cq_context->cqc_byte_20,
1971 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
1972 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S,
1973 cpu_to_le32((mtts[0]) >> 32));
1974 /* Dedicated hardware, directly set 0 */
1975 roce_set_field(cq_context->cqc_byte_20,
1976 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
1977 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
1979 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1980 * using 4K page, and shift more 32 because of
1981 * caculating the high 32 bit value evaluated to hardware.
1983 roce_set_field(cq_context->cqc_byte_20,
1984 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
1985 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
1986 tptr_dma_addr >> 44);
1987 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
1989 cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
1991 roce_set_field(cq_context->cqc_byte_32,
1992 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
1993 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
1994 roce_set_bit(cq_context->cqc_byte_32,
1995 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
1996 roce_set_bit(cq_context->cqc_byte_32,
1997 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
1998 roce_set_bit(cq_context->cqc_byte_32,
1999 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2000 roce_set_bit(cq_context->cqc_byte_32,
2001 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2003 /* The initial value of cq's ci is 0 */
2004 roce_set_field(cq_context->cqc_byte_32,
2005 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2006 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2007 cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32);
2010 int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
2012 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2013 u32 notification_flag;
2017 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2018 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2020 * flags = 0; Notification Flag = 1, next
2021 * flags = 1; Notification Flag = 0, solocited
2023 doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
2024 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2025 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2026 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2027 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2028 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2029 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2030 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2031 hr_cq->cqn | notification_flag);
2033 hns_roce_write64_k(doorbell, hr_cq->cq_db_l);
2038 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2039 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2046 struct hns_roce_cqe *cqe;
2047 struct hns_roce_qp *hr_qp;
2048 struct hns_roce_wq *wq;
2049 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2050 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2051 struct device *dev = &hr_dev->pdev->dev;
2053 /* Find cqe according consumer index */
2054 cqe = next_cqe_sw(hr_cq);
2058 ++hr_cq->cons_index;
2059 /* Memory barrier */
2062 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2064 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2065 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2066 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2067 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2068 CQE_BYTE_20_PORT_NUM_S) +
2069 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2070 CQE_BYTE_16_LOCAL_QPN_S) *
2073 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2074 CQE_BYTE_16_LOCAL_QPN_S);
2077 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2078 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2079 if (unlikely(!hr_qp)) {
2080 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2081 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2088 wc->qp = &(*cur_qp)->ibqp;
2091 status = roce_get_field(cqe->cqe_byte_4,
2092 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2093 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2094 HNS_ROCE_CQE_STATUS_MASK;
2096 case HNS_ROCE_CQE_SUCCESS:
2097 wc->status = IB_WC_SUCCESS;
2099 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2100 wc->status = IB_WC_LOC_LEN_ERR;
2102 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2103 wc->status = IB_WC_LOC_QP_OP_ERR;
2105 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2106 wc->status = IB_WC_LOC_PROT_ERR;
2108 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2109 wc->status = IB_WC_WR_FLUSH_ERR;
2111 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2112 wc->status = IB_WC_MW_BIND_ERR;
2114 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2115 wc->status = IB_WC_BAD_RESP_ERR;
2117 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2118 wc->status = IB_WC_LOC_ACCESS_ERR;
2120 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2121 wc->status = IB_WC_REM_INV_REQ_ERR;
2123 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2124 wc->status = IB_WC_REM_ACCESS_ERR;
2126 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2127 wc->status = IB_WC_REM_OP_ERR;
2129 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2130 wc->status = IB_WC_RETRY_EXC_ERR;
2132 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2133 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2136 wc->status = IB_WC_GENERAL_ERR;
2140 /* CQE status error, directly return */
2141 if (wc->status != IB_WC_SUCCESS)
2145 /* SQ conrespond to CQE */
2146 sq_wqe = get_send_wqe(*cur_qp, roce_get_field(cqe->cqe_byte_4,
2147 CQE_BYTE_4_WQE_INDEX_M,
2148 CQE_BYTE_4_WQE_INDEX_S)&
2149 ((*cur_qp)->sq.wqe_cnt-1));
2150 switch (sq_wqe->flag & HNS_ROCE_WQE_OPCODE_MASK) {
2151 case HNS_ROCE_WQE_OPCODE_SEND:
2152 wc->opcode = IB_WC_SEND;
2154 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2155 wc->opcode = IB_WC_RDMA_READ;
2156 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2158 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2159 wc->opcode = IB_WC_RDMA_WRITE;
2161 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2162 wc->opcode = IB_WC_LOCAL_INV;
2164 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2165 wc->opcode = IB_WC_SEND;
2168 wc->status = IB_WC_GENERAL_ERR;
2171 wc->wc_flags = (sq_wqe->flag & HNS_ROCE_WQE_IMM ?
2172 IB_WC_WITH_IMM : 0);
2174 wq = &(*cur_qp)->sq;
2175 if ((*cur_qp)->sq_signal_bits) {
2177 * If sg_signal_bit is 1,
2178 * firstly tail pointer updated to wqe
2179 * which current cqe correspond to
2181 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2182 CQE_BYTE_4_WQE_INDEX_M,
2183 CQE_BYTE_4_WQE_INDEX_S);
2184 wq->tail += (wqe_ctr - (u16)wq->tail) &
2187 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2190 /* RQ conrespond to CQE */
2191 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2192 opcode = roce_get_field(cqe->cqe_byte_4,
2193 CQE_BYTE_4_OPERATION_TYPE_M,
2194 CQE_BYTE_4_OPERATION_TYPE_S) &
2195 HNS_ROCE_CQE_OPCODE_MASK;
2197 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2198 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2199 wc->wc_flags = IB_WC_WITH_IMM;
2200 wc->ex.imm_data = le32_to_cpu(cqe->immediate_data);
2202 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2203 if (roce_get_bit(cqe->cqe_byte_4,
2204 CQE_BYTE_4_IMM_INDICATOR_S)) {
2205 wc->opcode = IB_WC_RECV;
2206 wc->wc_flags = IB_WC_WITH_IMM;
2207 wc->ex.imm_data = le32_to_cpu(
2208 cqe->immediate_data);
2210 wc->opcode = IB_WC_RECV;
2215 wc->status = IB_WC_GENERAL_ERR;
2219 /* Update tail pointer, record wr_id */
2220 wq = &(*cur_qp)->rq;
2221 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2223 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2225 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2226 CQE_BYTE_20_REMOTE_QPN_M,
2227 CQE_BYTE_20_REMOTE_QPN_S);
2228 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2229 CQE_BYTE_20_GRH_PRESENT_S) ?
2231 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2232 CQE_BYTE_28_P_KEY_IDX_M,
2233 CQE_BYTE_28_P_KEY_IDX_S);
2239 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2241 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2242 struct hns_roce_qp *cur_qp = NULL;
2243 unsigned long flags;
2247 spin_lock_irqsave(&hr_cq->lock, flags);
2249 for (npolled = 0; npolled < num_entries; ++npolled) {
2250 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2256 *hr_cq->tptr_addr = hr_cq->cons_index &
2257 ((hr_cq->cq_depth << 1) - 1);
2259 /* Memroy barrier */
2261 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2264 spin_unlock_irqrestore(&hr_cq->lock, flags);
2266 if (ret == 0 || ret == -EAGAIN)
2272 int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2273 struct hns_roce_hem_table *table, int obj)
2275 struct device *dev = &hr_dev->pdev->dev;
2276 struct hns_roce_v1_priv *priv;
2277 unsigned long end = 0, flags = 0;
2278 uint32_t bt_cmd_val[2] = {0};
2279 void __iomem *bt_cmd;
2282 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
2284 switch (table->type) {
2286 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2287 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC);
2288 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2291 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2292 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT);
2293 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2296 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2297 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC);
2298 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2301 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2306 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2307 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2308 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2309 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2311 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2313 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2315 end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies;
2317 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2318 if (!(time_before(jiffies, end))) {
2319 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2320 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2327 msleep(HW_SYNC_SLEEP_TIME_INTERVAL);
2330 bt_cmd_val[0] = (uint32_t)bt_ba;
2331 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2332 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2333 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2335 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2340 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2341 struct hns_roce_mtt *mtt,
2342 enum hns_roce_qp_state cur_state,
2343 enum hns_roce_qp_state new_state,
2344 struct hns_roce_qp_context *context,
2345 struct hns_roce_qp *hr_qp)
2348 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2349 [HNS_ROCE_QP_STATE_RST] = {
2350 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2351 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2352 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2354 [HNS_ROCE_QP_STATE_INIT] = {
2355 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2356 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2357 /* Note: In v1 engine, HW doesn't support RST2INIT.
2358 * We use RST2INIT cmd instead of INIT2INIT.
2360 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2361 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2363 [HNS_ROCE_QP_STATE_RTR] = {
2364 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2365 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2366 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2368 [HNS_ROCE_QP_STATE_RTS] = {
2369 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2370 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2371 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2372 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2374 [HNS_ROCE_QP_STATE_SQD] = {
2375 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2376 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2377 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2378 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2380 [HNS_ROCE_QP_STATE_ERR] = {
2381 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2382 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2386 struct hns_roce_cmd_mailbox *mailbox;
2387 struct device *dev = &hr_dev->pdev->dev;
2390 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2391 new_state >= HNS_ROCE_QP_NUM_STATE ||
2392 !op[cur_state][new_state]) {
2393 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2394 cur_state, new_state);
2398 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2399 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2400 HNS_ROCE_CMD_2RST_QP,
2401 HNS_ROCE_CMD_TIMEOUT_MSECS);
2403 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2404 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2405 HNS_ROCE_CMD_2ERR_QP,
2406 HNS_ROCE_CMD_TIMEOUT_MSECS);
2408 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2409 if (IS_ERR(mailbox))
2410 return PTR_ERR(mailbox);
2412 memcpy(mailbox->buf, context, sizeof(*context));
2414 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2415 op[cur_state][new_state],
2416 HNS_ROCE_CMD_TIMEOUT_MSECS);
2418 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2422 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2423 int attr_mask, enum ib_qp_state cur_state,
2424 enum ib_qp_state new_state)
2426 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2427 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2428 struct hns_roce_sqp_context *context;
2429 struct device *dev = &hr_dev->pdev->dev;
2430 dma_addr_t dma_handle = 0;
2436 context = kzalloc(sizeof(*context), GFP_KERNEL);
2440 /* Search QP buf's MTTs */
2441 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2442 hr_qp->mtt.first_seg, &dma_handle);
2444 dev_err(dev, "qp buf pa find failed\n");
2448 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2449 roce_set_field(context->qp1c_bytes_4,
2450 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2451 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2452 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2453 roce_set_field(context->qp1c_bytes_4,
2454 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2455 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2456 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2457 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2458 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2460 context->sq_rq_bt_l = (u32)(dma_handle);
2461 roce_set_field(context->qp1c_bytes_12,
2462 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2463 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2464 ((u32)(dma_handle >> 32)));
2466 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2467 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2468 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2469 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2470 roce_set_bit(context->qp1c_bytes_16,
2471 QP1C_BYTES_16_SIGNALING_TYPE_S,
2472 hr_qp->sq_signal_bits);
2473 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2475 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2477 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2480 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2481 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2482 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2483 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2485 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2486 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2488 roce_set_field(context->qp1c_bytes_28,
2489 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2490 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2491 (mtts[rq_pa_start]) >> 32);
2492 roce_set_field(context->qp1c_bytes_28,
2493 QP1C_BYTES_28_RQ_CUR_IDX_M,
2494 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2496 roce_set_field(context->qp1c_bytes_32,
2497 QP1C_BYTES_32_RX_CQ_NUM_M,
2498 QP1C_BYTES_32_RX_CQ_NUM_S,
2499 to_hr_cq(ibqp->recv_cq)->cqn);
2500 roce_set_field(context->qp1c_bytes_32,
2501 QP1C_BYTES_32_TX_CQ_NUM_M,
2502 QP1C_BYTES_32_TX_CQ_NUM_S,
2503 to_hr_cq(ibqp->send_cq)->cqn);
2505 context->cur_sq_wqe_ba_l = (u32)mtts[0];
2507 roce_set_field(context->qp1c_bytes_40,
2508 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2509 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2511 roce_set_field(context->qp1c_bytes_40,
2512 QP1C_BYTES_40_SQ_CUR_IDX_M,
2513 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2515 /* Copy context to QP1C register */
2516 addr = (u32 *)(hr_dev->reg_base + ROCEE_QP1C_CFG0_0_REG +
2517 hr_qp->phy_port * sizeof(*context));
2519 writel(context->qp1c_bytes_4, addr);
2520 writel(context->sq_rq_bt_l, addr + 1);
2521 writel(context->qp1c_bytes_12, addr + 2);
2522 writel(context->qp1c_bytes_16, addr + 3);
2523 writel(context->qp1c_bytes_20, addr + 4);
2524 writel(context->cur_rq_wqe_ba_l, addr + 5);
2525 writel(context->qp1c_bytes_28, addr + 6);
2526 writel(context->qp1c_bytes_32, addr + 7);
2527 writel(context->cur_sq_wqe_ba_l, addr + 8);
2528 writel(context->qp1c_bytes_40, addr + 9);
2531 /* Modify QP1C status */
2532 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2533 hr_qp->phy_port * sizeof(*context));
2534 roce_set_field(reg_val, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2535 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2536 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2537 hr_qp->phy_port * sizeof(*context), reg_val);
2539 hr_qp->state = new_state;
2540 if (new_state == IB_QPS_RESET) {
2541 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2542 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2543 if (ibqp->send_cq != ibqp->recv_cq)
2544 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2551 hr_qp->sq_next_wqe = 0;
2562 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2563 int attr_mask, enum ib_qp_state cur_state,
2564 enum ib_qp_state new_state)
2566 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2567 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2568 struct device *dev = &hr_dev->pdev->dev;
2569 struct hns_roce_qp_context *context;
2570 dma_addr_t dma_handle_2 = 0;
2571 dma_addr_t dma_handle = 0;
2572 uint32_t doorbell[2] = {0};
2573 int rq_pa_start = 0;
2581 context = kzalloc(sizeof(*context), GFP_KERNEL);
2585 /* Search qp buf's mtts */
2586 mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
2587 hr_qp->mtt.first_seg, &dma_handle);
2589 dev_err(dev, "qp buf pa find failed\n");
2593 /* Search IRRL's mtts */
2594 mtts_2 = hns_roce_table_find(&hr_dev->qp_table.irrl_table, hr_qp->qpn,
2596 if (mtts_2 == NULL) {
2597 dev_err(dev, "qp irrl_table find failed\n");
2604 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2605 * Optional param: NA
2607 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2608 roce_set_field(context->qpc_bytes_4,
2609 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2610 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2611 to_hr_qp_type(hr_qp->ibqp.qp_type));
2613 roce_set_bit(context->qpc_bytes_4,
2614 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2615 roce_set_bit(context->qpc_bytes_4,
2616 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2617 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2618 roce_set_bit(context->qpc_bytes_4,
2619 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2620 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2622 roce_set_bit(context->qpc_bytes_4,
2623 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2624 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2626 roce_set_bit(context->qpc_bytes_4,
2627 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2628 roce_set_field(context->qpc_bytes_4,
2629 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2630 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2631 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2632 roce_set_field(context->qpc_bytes_4,
2633 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2634 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2635 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2636 roce_set_field(context->qpc_bytes_4,
2637 QP_CONTEXT_QPC_BYTES_4_PD_M,
2638 QP_CONTEXT_QPC_BYTES_4_PD_S,
2639 to_hr_pd(ibqp->pd)->pdn);
2640 hr_qp->access_flags = attr->qp_access_flags;
2641 roce_set_field(context->qpc_bytes_8,
2642 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2643 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2644 to_hr_cq(ibqp->send_cq)->cqn);
2645 roce_set_field(context->qpc_bytes_8,
2646 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2647 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2648 to_hr_cq(ibqp->recv_cq)->cqn);
2651 roce_set_field(context->qpc_bytes_12,
2652 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2653 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2654 to_hr_srq(ibqp->srq)->srqn);
2656 roce_set_field(context->qpc_bytes_12,
2657 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2658 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2660 hr_qp->pkey_index = attr->pkey_index;
2661 roce_set_field(context->qpc_bytes_16,
2662 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2663 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2665 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2666 roce_set_field(context->qpc_bytes_4,
2667 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2668 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2669 to_hr_qp_type(hr_qp->ibqp.qp_type));
2670 roce_set_bit(context->qpc_bytes_4,
2671 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2672 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2673 roce_set_bit(context->qpc_bytes_4,
2674 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2675 !!(attr->qp_access_flags &
2676 IB_ACCESS_REMOTE_READ));
2677 roce_set_bit(context->qpc_bytes_4,
2678 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2679 !!(attr->qp_access_flags &
2680 IB_ACCESS_REMOTE_WRITE));
2682 roce_set_bit(context->qpc_bytes_4,
2683 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2684 !!(hr_qp->access_flags &
2685 IB_ACCESS_REMOTE_READ));
2686 roce_set_bit(context->qpc_bytes_4,
2687 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2688 !!(hr_qp->access_flags &
2689 IB_ACCESS_REMOTE_WRITE));
2692 roce_set_bit(context->qpc_bytes_4,
2693 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2694 roce_set_field(context->qpc_bytes_4,
2695 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2696 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2697 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2698 roce_set_field(context->qpc_bytes_4,
2699 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2700 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2701 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2702 roce_set_field(context->qpc_bytes_4,
2703 QP_CONTEXT_QPC_BYTES_4_PD_M,
2704 QP_CONTEXT_QPC_BYTES_4_PD_S,
2705 to_hr_pd(ibqp->pd)->pdn);
2707 roce_set_field(context->qpc_bytes_8,
2708 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2709 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2710 to_hr_cq(ibqp->send_cq)->cqn);
2711 roce_set_field(context->qpc_bytes_8,
2712 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2713 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2714 to_hr_cq(ibqp->recv_cq)->cqn);
2717 roce_set_field(context->qpc_bytes_12,
2718 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2719 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2720 to_hr_srq(ibqp->srq)->srqn);
2721 if (attr_mask & IB_QP_PKEY_INDEX)
2722 roce_set_field(context->qpc_bytes_12,
2723 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2724 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2727 roce_set_field(context->qpc_bytes_12,
2728 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2729 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2732 roce_set_field(context->qpc_bytes_16,
2733 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2734 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2735 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2736 if ((attr_mask & IB_QP_ALT_PATH) ||
2737 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2738 (attr_mask & IB_QP_PKEY_INDEX) ||
2739 (attr_mask & IB_QP_QKEY)) {
2740 dev_err(dev, "INIT2RTR attr_mask error\n");
2744 dmac = (u8 *)attr->ah_attr.dmac;
2746 context->sq_rq_bt_l = (u32)(dma_handle);
2747 roce_set_field(context->qpc_bytes_24,
2748 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2749 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2750 ((u32)(dma_handle >> 32)));
2751 roce_set_bit(context->qpc_bytes_24,
2752 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2754 roce_set_field(context->qpc_bytes_24,
2755 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2756 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2757 attr->min_rnr_timer);
2758 context->irrl_ba_l = (u32)(dma_handle_2);
2759 roce_set_field(context->qpc_bytes_32,
2760 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2761 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2762 ((u32)(dma_handle_2 >> 32)) &
2763 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2764 roce_set_field(context->qpc_bytes_32,
2765 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2766 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2767 roce_set_bit(context->qpc_bytes_32,
2768 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2770 roce_set_bit(context->qpc_bytes_32,
2771 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2772 hr_qp->sq_signal_bits);
2774 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2776 smac = (u8 *)hr_dev->dev_addr[port];
2777 /* when dmac equals smac or loop_idc is 1, it should loopback */
2778 if (ether_addr_equal_unaligned(dmac, smac) ||
2779 hr_dev->loop_idc == 0x1)
2780 roce_set_bit(context->qpc_bytes_32,
2781 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2783 roce_set_bit(context->qpc_bytes_32,
2784 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2785 attr->ah_attr.ah_flags);
2786 roce_set_field(context->qpc_bytes_32,
2787 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2788 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2789 ilog2((unsigned int)attr->max_dest_rd_atomic));
2791 roce_set_field(context->qpc_bytes_36,
2792 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2793 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2796 /* Configure GID index */
2797 roce_set_field(context->qpc_bytes_36,
2798 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2799 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2800 hns_get_gid_index(hr_dev,
2801 attr->ah_attr.port_num - 1,
2802 attr->ah_attr.grh.sgid_index));
2804 memcpy(&(context->dmac_l), dmac, 4);
2806 roce_set_field(context->qpc_bytes_44,
2807 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2808 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2809 *((u16 *)(&dmac[4])));
2810 roce_set_field(context->qpc_bytes_44,
2811 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2812 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2813 attr->ah_attr.static_rate);
2814 roce_set_field(context->qpc_bytes_44,
2815 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2816 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2817 attr->ah_attr.grh.hop_limit);
2819 roce_set_field(context->qpc_bytes_48,
2820 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2821 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2822 attr->ah_attr.grh.flow_label);
2823 roce_set_field(context->qpc_bytes_48,
2824 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
2825 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
2826 attr->ah_attr.grh.traffic_class);
2827 roce_set_field(context->qpc_bytes_48,
2828 QP_CONTEXT_QPC_BYTES_48_MTU_M,
2829 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
2831 memcpy(context->dgid, attr->ah_attr.grh.dgid.raw,
2832 sizeof(attr->ah_attr.grh.dgid.raw));
2834 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
2835 roce_get_field(context->qpc_bytes_44,
2836 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2837 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
2839 roce_set_field(context->qpc_bytes_68,
2840 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
2841 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
2843 roce_set_field(context->qpc_bytes_68,
2844 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
2845 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
2847 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE;
2848 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]);
2850 roce_set_field(context->qpc_bytes_76,
2851 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
2852 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
2853 mtts[rq_pa_start] >> 32);
2854 roce_set_field(context->qpc_bytes_76,
2855 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
2856 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
2858 context->rx_rnr_time = 0;
2860 roce_set_field(context->qpc_bytes_84,
2861 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
2862 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
2864 roce_set_field(context->qpc_bytes_84,
2865 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
2866 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
2868 roce_set_field(context->qpc_bytes_88,
2869 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
2870 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
2872 roce_set_bit(context->qpc_bytes_88,
2873 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
2874 roce_set_bit(context->qpc_bytes_88,
2875 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
2876 roce_set_field(context->qpc_bytes_88,
2877 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
2878 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
2880 roce_set_field(context->qpc_bytes_88,
2881 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
2882 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
2885 context->dma_length = 0;
2890 roce_set_field(context->qpc_bytes_108,
2891 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
2892 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
2893 roce_set_bit(context->qpc_bytes_108,
2894 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
2895 roce_set_bit(context->qpc_bytes_108,
2896 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
2898 roce_set_field(context->qpc_bytes_112,
2899 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
2900 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
2901 roce_set_field(context->qpc_bytes_112,
2902 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
2903 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
2905 /* For chip resp ack */
2906 roce_set_field(context->qpc_bytes_156,
2907 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2908 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
2910 roce_set_field(context->qpc_bytes_156,
2911 QP_CONTEXT_QPC_BYTES_156_SL_M,
2912 QP_CONTEXT_QPC_BYTES_156_SL_S, attr->ah_attr.sl);
2913 hr_qp->sl = attr->ah_attr.sl;
2914 } else if (cur_state == IB_QPS_RTR &&
2915 new_state == IB_QPS_RTS) {
2916 /* If exist optional param, return error */
2917 if ((attr_mask & IB_QP_ALT_PATH) ||
2918 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2919 (attr_mask & IB_QP_QKEY) ||
2920 (attr_mask & IB_QP_PATH_MIG_STATE) ||
2921 (attr_mask & IB_QP_CUR_STATE) ||
2922 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
2923 dev_err(dev, "RTR2RTS attr_mask error\n");
2927 context->rx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
2929 roce_set_field(context->qpc_bytes_120,
2930 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
2931 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
2934 roce_set_field(context->qpc_bytes_124,
2935 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
2936 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
2937 roce_set_field(context->qpc_bytes_124,
2938 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
2939 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
2941 roce_set_field(context->qpc_bytes_128,
2942 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
2943 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
2945 roce_set_bit(context->qpc_bytes_128,
2946 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
2947 roce_set_field(context->qpc_bytes_128,
2948 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
2949 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
2951 roce_set_bit(context->qpc_bytes_128,
2952 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
2954 roce_set_field(context->qpc_bytes_132,
2955 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
2956 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
2957 roce_set_field(context->qpc_bytes_132,
2958 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
2959 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
2961 roce_set_field(context->qpc_bytes_136,
2962 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
2963 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
2965 roce_set_field(context->qpc_bytes_136,
2966 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
2967 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
2970 roce_set_field(context->qpc_bytes_140,
2971 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
2972 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
2973 (attr->sq_psn >> SQ_PSN_SHIFT));
2974 roce_set_field(context->qpc_bytes_140,
2975 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
2976 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
2977 roce_set_bit(context->qpc_bytes_140,
2978 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
2980 roce_set_field(context->qpc_bytes_148,
2981 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
2982 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
2983 roce_set_field(context->qpc_bytes_148,
2984 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
2985 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
2987 roce_set_field(context->qpc_bytes_148,
2988 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
2989 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
2991 roce_set_field(context->qpc_bytes_148,
2992 QP_CONTEXT_QPC_BYTES_148_LSN_M,
2993 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
2995 context->rnr_retry = 0;
2997 roce_set_field(context->qpc_bytes_156,
2998 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
2999 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3001 if (attr->timeout < 0x12) {
3002 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3004 roce_set_field(context->qpc_bytes_156,
3005 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3006 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3009 roce_set_field(context->qpc_bytes_156,
3010 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3011 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3014 roce_set_field(context->qpc_bytes_156,
3015 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3016 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3018 roce_set_field(context->qpc_bytes_156,
3019 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3020 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3022 roce_set_field(context->qpc_bytes_156,
3023 QP_CONTEXT_QPC_BYTES_156_SL_M,
3024 QP_CONTEXT_QPC_BYTES_156_SL_S, attr->ah_attr.sl);
3025 hr_qp->sl = attr->ah_attr.sl;
3026 roce_set_field(context->qpc_bytes_156,
3027 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3028 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3029 ilog2((unsigned int)attr->max_rd_atomic));
3030 roce_set_field(context->qpc_bytes_156,
3031 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3032 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3033 context->pkt_use_len = 0;
3035 roce_set_field(context->qpc_bytes_164,
3036 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3037 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3038 roce_set_field(context->qpc_bytes_164,
3039 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3040 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3042 roce_set_field(context->qpc_bytes_168,
3043 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3044 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3046 roce_set_field(context->qpc_bytes_168,
3047 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3048 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3049 roce_set_field(context->qpc_bytes_168,
3050 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3051 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3052 roce_set_bit(context->qpc_bytes_168,
3053 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3054 roce_set_bit(context->qpc_bytes_168,
3055 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3056 roce_set_bit(context->qpc_bytes_168,
3057 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3058 context->sge_use_len = 0;
3060 roce_set_field(context->qpc_bytes_176,
3061 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3062 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3063 roce_set_field(context->qpc_bytes_176,
3064 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3065 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3067 roce_set_field(context->qpc_bytes_180,
3068 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3069 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3070 roce_set_field(context->qpc_bytes_180,
3071 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3072 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3074 context->tx_cur_sq_wqe_ba_l = (u32)(mtts[0]);
3076 roce_set_field(context->qpc_bytes_188,
3077 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3078 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3080 roce_set_bit(context->qpc_bytes_188,
3081 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3082 roce_set_field(context->qpc_bytes_188,
3083 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3084 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3086 } else if (!((cur_state == IB_QPS_INIT && new_state == IB_QPS_RESET) ||
3087 (cur_state == IB_QPS_INIT && new_state == IB_QPS_ERR) ||
3088 (cur_state == IB_QPS_RTR && new_state == IB_QPS_RESET) ||
3089 (cur_state == IB_QPS_RTR && new_state == IB_QPS_ERR) ||
3090 (cur_state == IB_QPS_RTS && new_state == IB_QPS_RESET) ||
3091 (cur_state == IB_QPS_RTS && new_state == IB_QPS_ERR) ||
3092 (cur_state == IB_QPS_ERR && new_state == IB_QPS_RESET) ||
3093 (cur_state == IB_QPS_ERR && new_state == IB_QPS_ERR))) {
3094 dev_err(dev, "not support this status migration\n");
3098 /* Every status migrate must change state */
3099 roce_set_field(context->qpc_bytes_144,
3100 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3101 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3103 /* SW pass context to HW */
3104 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
3105 to_hns_roce_state(cur_state),
3106 to_hns_roce_state(new_state), context,
3109 dev_err(dev, "hns_roce_qp_modify failed\n");
3114 * Use rst2init to instead of init2init with drv,
3115 * need to hw to flash RQ HEAD by DB again
3117 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3118 /* Memory barrier */
3121 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3122 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3123 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3124 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3125 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3126 RQ_DOORBELL_U32_8_CMD_S, 1);
3127 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3129 if (ibqp->uobject) {
3130 hr_qp->rq.db_reg_l = hr_dev->reg_base +
3131 ROCEE_DB_OTHERS_L_0_REG +
3132 DB_REG_OFFSET * hr_dev->priv_uar.index;
3135 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l);
3138 hr_qp->state = new_state;
3140 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3141 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3142 if (attr_mask & IB_QP_PORT) {
3143 hr_qp->port = attr->port_num - 1;
3144 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3147 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3148 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3149 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3150 if (ibqp->send_cq != ibqp->recv_cq)
3151 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3158 hr_qp->sq_next_wqe = 0;
3165 int hns_roce_v1_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
3166 int attr_mask, enum ib_qp_state cur_state,
3167 enum ib_qp_state new_state)
3170 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3171 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3174 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3178 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3181 case HNS_ROCE_QP_STATE_RST:
3182 return IB_QPS_RESET;
3183 case HNS_ROCE_QP_STATE_INIT:
3185 case HNS_ROCE_QP_STATE_RTR:
3187 case HNS_ROCE_QP_STATE_RTS:
3189 case HNS_ROCE_QP_STATE_SQD:
3191 case HNS_ROCE_QP_STATE_ERR:
3198 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3199 struct hns_roce_qp *hr_qp,
3200 struct hns_roce_qp_context *hr_context)
3202 struct hns_roce_cmd_mailbox *mailbox;
3205 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3206 if (IS_ERR(mailbox))
3207 return PTR_ERR(mailbox);
3209 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3210 HNS_ROCE_CMD_QUERY_QP,
3211 HNS_ROCE_CMD_TIMEOUT_MSECS);
3213 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3215 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3217 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3222 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3224 struct ib_qp_init_attr *qp_init_attr)
3226 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3227 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3228 struct hns_roce_sqp_context context;
3231 mutex_lock(&hr_qp->mutex);
3233 if (hr_qp->state == IB_QPS_RESET) {
3234 qp_attr->qp_state = IB_QPS_RESET;
3238 addr = ROCEE_QP1C_CFG0_0_REG +
3239 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3240 context.qp1c_bytes_4 = roce_read(hr_dev, addr);
3241 context.sq_rq_bt_l = roce_read(hr_dev, addr + 1);
3242 context.qp1c_bytes_12 = roce_read(hr_dev, addr + 2);
3243 context.qp1c_bytes_16 = roce_read(hr_dev, addr + 3);
3244 context.qp1c_bytes_20 = roce_read(hr_dev, addr + 4);
3245 context.cur_rq_wqe_ba_l = roce_read(hr_dev, addr + 5);
3246 context.qp1c_bytes_28 = roce_read(hr_dev, addr + 6);
3247 context.qp1c_bytes_32 = roce_read(hr_dev, addr + 7);
3248 context.cur_sq_wqe_ba_l = roce_read(hr_dev, addr + 8);
3249 context.qp1c_bytes_40 = roce_read(hr_dev, addr + 9);
3251 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3252 QP1C_BYTES_4_QP_STATE_M,
3253 QP1C_BYTES_4_QP_STATE_S);
3254 qp_attr->qp_state = hr_qp->state;
3255 qp_attr->path_mtu = IB_MTU_256;
3256 qp_attr->path_mig_state = IB_MIG_ARMED;
3257 qp_attr->qkey = QKEY_VAL;
3258 qp_attr->rq_psn = 0;
3259 qp_attr->sq_psn = 0;
3260 qp_attr->dest_qp_num = 1;
3261 qp_attr->qp_access_flags = 6;
3263 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3264 QP1C_BYTES_20_PKEY_IDX_M,
3265 QP1C_BYTES_20_PKEY_IDX_S);
3266 qp_attr->port_num = hr_qp->port + 1;
3267 qp_attr->sq_draining = 0;
3268 qp_attr->max_rd_atomic = 0;
3269 qp_attr->max_dest_rd_atomic = 0;
3270 qp_attr->min_rnr_timer = 0;
3271 qp_attr->timeout = 0;
3272 qp_attr->retry_cnt = 0;
3273 qp_attr->rnr_retry = 0;
3274 qp_attr->alt_timeout = 0;
3277 qp_attr->cur_qp_state = qp_attr->qp_state;
3278 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3279 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3280 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3281 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3282 qp_attr->cap.max_inline_data = 0;
3283 qp_init_attr->cap = qp_attr->cap;
3284 qp_init_attr->create_flags = 0;
3286 mutex_unlock(&hr_qp->mutex);
3291 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3293 struct ib_qp_init_attr *qp_init_attr)
3295 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3296 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3297 struct device *dev = &hr_dev->pdev->dev;
3298 struct hns_roce_qp_context *context;
3299 int tmp_qp_state = 0;
3303 context = kzalloc(sizeof(*context), GFP_KERNEL);
3307 memset(qp_attr, 0, sizeof(*qp_attr));
3308 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3310 mutex_lock(&hr_qp->mutex);
3312 if (hr_qp->state == IB_QPS_RESET) {
3313 qp_attr->qp_state = IB_QPS_RESET;
3317 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3319 dev_err(dev, "query qpc error\n");
3324 state = roce_get_field(context->qpc_bytes_144,
3325 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3326 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3327 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3328 if (tmp_qp_state == -1) {
3329 dev_err(dev, "to_ib_qp_state error\n");
3333 hr_qp->state = (u8)tmp_qp_state;
3334 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3335 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3336 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3337 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3338 qp_attr->path_mig_state = IB_MIG_ARMED;
3339 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3340 qp_attr->qkey = QKEY_VAL;
3342 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3343 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3344 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3345 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3346 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3347 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3348 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3349 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3350 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3351 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3352 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3353 ((roce_get_bit(context->qpc_bytes_4,
3354 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3355 ((roce_get_bit(context->qpc_bytes_4,
3356 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3358 if (hr_qp->ibqp.qp_type == IB_QPT_RC ||
3359 hr_qp->ibqp.qp_type == IB_QPT_UC) {
3360 qp_attr->ah_attr.sl = roce_get_field(context->qpc_bytes_156,
3361 QP_CONTEXT_QPC_BYTES_156_SL_M,
3362 QP_CONTEXT_QPC_BYTES_156_SL_S);
3363 qp_attr->ah_attr.grh.flow_label = roce_get_field(
3364 context->qpc_bytes_48,
3365 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3366 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3367 qp_attr->ah_attr.grh.sgid_index = roce_get_field(
3368 context->qpc_bytes_36,
3369 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3370 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3371 qp_attr->ah_attr.grh.hop_limit = roce_get_field(
3372 context->qpc_bytes_44,
3373 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3374 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3375 qp_attr->ah_attr.grh.traffic_class = roce_get_field(
3376 context->qpc_bytes_48,
3377 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3378 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3380 memcpy(qp_attr->ah_attr.grh.dgid.raw, context->dgid,
3381 sizeof(qp_attr->ah_attr.grh.dgid.raw));
3384 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3385 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3386 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3387 qp_attr->port_num = hr_qp->port + 1;
3388 qp_attr->sq_draining = 0;
3389 qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156,
3390 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3391 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3392 qp_attr->max_dest_rd_atomic = roce_get_field(context->qpc_bytes_32,
3393 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3394 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3395 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3396 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3397 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3398 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3399 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3400 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3401 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3402 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3403 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3404 qp_attr->rnr_retry = context->rnr_retry;
3407 qp_attr->cur_qp_state = qp_attr->qp_state;
3408 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3409 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3411 if (!ibqp->uobject) {
3412 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3413 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3415 qp_attr->cap.max_send_wr = 0;
3416 qp_attr->cap.max_send_sge = 0;
3419 qp_init_attr->cap = qp_attr->cap;
3422 mutex_unlock(&hr_qp->mutex);
3427 int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3428 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3430 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3432 return hr_qp->doorbell_qpn <= 1 ?
3433 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3434 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3437 static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3438 struct hns_roce_qp *hr_qp,
3443 struct device *dev = &hr_dev->pdev->dev;
3444 u32 sdb_retry_cnt, old_retry;
3445 u32 sdb_send_ptr, old_send;
3446 u32 success_flags = 0;
3447 u32 cur_cnt, old_cnt;
3453 if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3454 *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3455 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3456 hr_qp->qpn, *wait_stage);
3460 /* Calculate the total timeout for the entire verification process */
3461 end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
3463 if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
3464 /* Query db process status, until hw process completely */
3465 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3466 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
3467 ROCEE_SDB_PTR_CMP_BITS)) {
3468 if (!time_before(jiffies, end)) {
3469 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
3470 hr_qp->qpn, sdb_issue_ptr,
3475 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3476 sdb_send_ptr = roce_read(hr_dev,
3477 ROCEE_SDB_SEND_PTR_REG);
3480 if (roce_get_field(sdb_issue_ptr,
3481 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3482 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3483 roce_get_field(sdb_send_ptr,
3484 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3485 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3486 old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3487 old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
3490 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
3491 if (roce_get_bit(tsp_st,
3492 ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3493 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3497 if (!time_before(jiffies, end)) {
3498 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
3499 "issue 0x%x send 0x%x.\n",
3500 hr_qp->qpn, sdb_issue_ptr,
3505 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3507 sdb_send_ptr = roce_read(hr_dev,
3508 ROCEE_SDB_SEND_PTR_REG);
3509 sdb_retry_cnt = roce_read(hr_dev,
3510 ROCEE_SDB_RETRY_CNT_REG);
3511 cur_cnt = roce_get_field(sdb_send_ptr,
3512 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3513 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3514 roce_get_field(sdb_retry_cnt,
3515 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3516 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3517 if (!roce_get_bit(tsp_st,
3518 ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3519 old_cnt = roce_get_field(old_send,
3520 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3521 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3522 roce_get_field(old_retry,
3523 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3524 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3525 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3528 old_cnt = roce_get_field(old_send,
3529 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3530 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3531 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3534 send_ptr = roce_get_field(old_send,
3535 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3536 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3537 roce_get_field(sdb_retry_cnt,
3538 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3539 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3540 roce_set_field(old_send,
3541 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3542 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3546 } while (!success_flags);
3549 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3551 /* Get list pointer */
3552 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3553 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3554 hr_qp->qpn, *sdb_inv_cnt);
3557 if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3558 /* Query db's list status, until hw reversal */
3559 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3560 while (roce_hw_index_cmp_lt(inv_cnt,
3561 *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3562 ROCEE_SDB_CNT_CMP_BITS)) {
3563 if (!time_before(jiffies, end)) {
3564 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3565 hr_qp->qpn, inv_cnt);
3569 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3570 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3573 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3579 static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3580 struct hns_roce_qp *hr_qp,
3581 struct hns_roce_qp_work *qp_work_entry,
3584 struct device *dev = &hr_dev->pdev->dev;
3588 if (hr_qp->state != IB_QPS_RESET) {
3589 /* Set qp to ERR, waiting for hw complete processing all dbs */
3590 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3593 dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3598 /* Record issued doorbell */
3599 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3600 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3601 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3603 /* Query db process status, until hw process completely */
3604 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3605 &qp_work_entry->sdb_inv_cnt,
3606 &qp_work_entry->db_wait_stage);
3608 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3613 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3614 qp_work_entry->sche_cnt = 0;
3619 /* Modify qp to reset before destroying qp */
3620 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3623 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3632 static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3634 struct hns_roce_qp_work *qp_work_entry;
3635 struct hns_roce_v1_priv *priv;
3636 struct hns_roce_dev *hr_dev;
3637 struct hns_roce_qp *hr_qp;
3641 qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3642 hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3643 dev = &hr_dev->pdev->dev;
3644 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3645 hr_qp = qp_work_entry->qp;
3647 dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", hr_qp->qpn);
3649 qp_work_entry->sche_cnt++;
3651 /* Query db process status, until hw process completely */
3652 ret = check_qp_db_process_status(hr_dev, hr_qp,
3653 qp_work_entry->sdb_issue_ptr,
3654 &qp_work_entry->sdb_inv_cnt,
3655 &qp_work_entry->db_wait_stage);
3657 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3662 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3663 priv->des_qp.requeue_flag) {
3664 queue_work(priv->des_qp.qp_wq, work);
3668 /* Modify qp to reset before destroying qp */
3669 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3672 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", hr_qp->qpn);
3676 hns_roce_qp_remove(hr_dev, hr_qp);
3677 hns_roce_qp_free(hr_dev, hr_qp);
3679 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3680 /* RC QP, release QPN */
3681 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3684 kfree(hr_to_hr_sqp(hr_qp));
3686 kfree(qp_work_entry);
3688 dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", hr_qp->qpn);
3691 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3693 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3694 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3695 struct device *dev = &hr_dev->pdev->dev;
3696 struct hns_roce_qp_work qp_work_entry;
3697 struct hns_roce_qp_work *qp_work;
3698 struct hns_roce_v1_priv *priv;
3699 struct hns_roce_cq *send_cq, *recv_cq;
3700 int is_user = !!ibqp->pd->uobject;
3704 ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3706 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3710 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
3711 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
3713 hns_roce_lock_cqs(send_cq, recv_cq);
3715 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
3716 to_hr_srq(hr_qp->ibqp.srq) : NULL);
3717 if (send_cq != recv_cq)
3718 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3720 hns_roce_unlock_cqs(send_cq, recv_cq);
3723 hns_roce_qp_remove(hr_dev, hr_qp);
3724 hns_roce_qp_free(hr_dev, hr_qp);
3726 /* RC QP, release QPN */
3727 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3728 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3731 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
3734 ib_umem_release(hr_qp->umem);
3736 kfree(hr_qp->sq.wrid);
3737 kfree(hr_qp->rq.wrid);
3739 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
3743 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3746 kfree(hr_to_hr_sqp(hr_qp));
3748 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3752 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3753 qp_work->ib_dev = &hr_dev->ib_dev;
3754 qp_work->qp = hr_qp;
3755 qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3756 qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3757 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3758 qp_work->sche_cnt = qp_work_entry.sche_cnt;
3760 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3761 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3762 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3768 int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
3770 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3771 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3772 struct device *dev = &hr_dev->pdev->dev;
3779 hns_roce_free_cq(hr_dev, hr_cq);
3782 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3783 * have been written by checking the CQE counter.
3785 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3787 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3788 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3791 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3792 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3795 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3796 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3797 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3805 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3808 ib_umem_release(hr_cq->umem);
3810 /* Free the buff of stored cq */
3811 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3812 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3820 struct hns_roce_v1_priv hr_v1_priv;
3822 struct hns_roce_hw hns_roce_hw_v1 = {
3823 .reset = hns_roce_v1_reset,
3824 .hw_profile = hns_roce_v1_profile,
3825 .hw_init = hns_roce_v1_init,
3826 .hw_exit = hns_roce_v1_exit,
3827 .set_gid = hns_roce_v1_set_gid,
3828 .set_mac = hns_roce_v1_set_mac,
3829 .set_mtu = hns_roce_v1_set_mtu,
3830 .write_mtpt = hns_roce_v1_write_mtpt,
3831 .write_cqc = hns_roce_v1_write_cqc,
3832 .clear_hem = hns_roce_v1_clear_hem,
3833 .modify_qp = hns_roce_v1_modify_qp,
3834 .query_qp = hns_roce_v1_query_qp,
3835 .destroy_qp = hns_roce_v1_destroy_qp,
3836 .post_send = hns_roce_v1_post_send,
3837 .post_recv = hns_roce_v1_post_recv,
3838 .req_notify_cq = hns_roce_v1_req_notify_cq,
3839 .poll_cq = hns_roce_v1_poll_cq,
3840 .dereg_mr = hns_roce_v1_dereg_mr,
3841 .destroy_cq = hns_roce_v1_destroy_cq,
3842 .priv = &hr_v1_priv,