drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #if defined(CONFIG_X86)
  41 #include <asm/pat.h>
  42 #endif
  43 #include <linux/sched.h>
  44 #include <linux/delay.h>
  45 #include <rdma/ib_user_verbs.h>
  46 #include <rdma/ib_addr.h>
  47 #include <rdma/ib_cache.h>
  48 #include <linux/mlx5/port.h>
  49 #include <linux/mlx5/vport.h>
  50 #include <linux/list.h>
  51 #include <rdma/ib_smi.h>
  52 #include <rdma/ib_umem.h>
  53 #include <linux/in.h>
  54 #include <linux/etherdevice.h>
  55 #include <linux/mlx5/fs.h>
  56 #include "mlx5_ib.h"
  57
  58 #define DRIVER_NAME "mlx5_ib"
  59 #define DRIVER_VERSION "2.2-1"
  60 #define DRIVER_RELDATE  "Feb 2014"
  61
  62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  64 MODULE_LICENSE("Dual BSD/GPL");
  65 MODULE_VERSION(DRIVER_VERSION);
  66
  67 static int deprecated_prof_sel = 2;
  68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  70
  71 static char mlx5_version[] =
  72         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  73         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  74
  75 enum {
  76         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  77 };
  78
  79 static enum rdma_link_layer
  80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  81 {
  82         switch (port_type_cap) {
  83         case MLX5_CAP_PORT_TYPE_IB:
  84                 return IB_LINK_LAYER_INFINIBAND;
  85         case MLX5_CAP_PORT_TYPE_ETH:
  86                 return IB_LINK_LAYER_ETHERNET;
  87         default:
  88                 return IB_LINK_LAYER_UNSPECIFIED;
  89         }
  90 }
  91
  92 static enum rdma_link_layer
  93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  94 {
  95         struct mlx5_ib_dev *dev = to_mdev(device);
  96         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  97
  98         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  99 }
 100
 101 static int mlx5_netdev_event(struct notifier_block *this,
 102                              unsigned long event, void *ptr)
 103 {
 104         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 105         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 106                                                  roce.nb);
 107
 108         switch (event) {
 109         case NETDEV_REGISTER:
 110         case NETDEV_UNREGISTER:
 111                 write_lock(&ibdev->roce.netdev_lock);
 112                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 113                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 114                                              NULL : ndev;
 115                 write_unlock(&ibdev->roce.netdev_lock);
 116                 break;
 117
 118         case NETDEV_UP:
 119         case NETDEV_DOWN: {
 120                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 121                 struct net_device *upper = NULL;
 122
 123                 if (lag_ndev) {
 124                         upper = netdev_master_upper_dev_get(lag_ndev);
 125                         dev_put(lag_ndev);
 126                 }
 127
 128                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 129                     && ibdev->ib_active) {
 130                         struct ib_event ibev = { };
 131
 132                         ibev.device = &ibdev->ib_dev;
 133                         ibev.event = (event == NETDEV_UP) ?
 134                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 135                         ibev.element.port_num = 1;
 136                         ib_dispatch_event(&ibev);
 137                 }
 138                 break;
 139         }
 140
 141         default:
 142                 break;
 143         }
 144
 145         return NOTIFY_DONE;
 146 }
 147
 148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 149                                              u8 port_num)
 150 {
 151         struct mlx5_ib_dev *ibdev = to_mdev(device);
 152         struct net_device *ndev;
 153
 154         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 155         if (ndev)
 156                 return ndev;
 157
 158         /* Ensure ndev does not disappear before we invoke dev_hold()
 159          */
 160         read_lock(&ibdev->roce.netdev_lock);
 161         ndev = ibdev->roce.netdev;
 162         if (ndev)
 163                 dev_hold(ndev);
 164         read_unlock(&ibdev->roce.netdev_lock);
 165
 166         return ndev;
 167 }
 168
 169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 170                                 struct ib_port_attr *props)
 171 {
 172         struct mlx5_ib_dev *dev = to_mdev(device);
 173         struct net_device *ndev, *upper;
 174         enum ib_mtu ndev_ib_mtu;
 175         u16 qkey_viol_cntr;
 176
 177         memset(props, 0, sizeof(*props));
 178
 179         props->port_cap_flags  |= IB_PORT_CM_SUP;
 180         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 181
 182         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 183                                                 roce_address_table_size);
 184         props->max_mtu          = IB_MTU_4096;
 185         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 186         props->pkey_tbl_len     = 1;
 187         props->state            = IB_PORT_DOWN;
 188         props->phys_state       = 3;
 189
 190         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 191         props->qkey_viol_cntr = qkey_viol_cntr;
 192
 193         ndev = mlx5_ib_get_netdev(device, port_num);
 194         if (!ndev)
 195                 return 0;
 196
 197         if (mlx5_lag_is_active(dev->mdev)) {
 198                 rcu_read_lock();
 199                 upper = netdev_master_upper_dev_get_rcu(ndev);
 200                 if (upper) {
 201                         dev_put(ndev);
 202                         ndev = upper;
 203                         dev_hold(ndev);
 204                 }
 205                 rcu_read_unlock();
 206         }
 207
 208         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 209                 props->state      = IB_PORT_ACTIVE;
 210                 props->phys_state = 5;
 211         }
 212
 213         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 214
 215         dev_put(ndev);
 216
 217         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 218
 219         props->active_width     = IB_WIDTH_4X;  /* TODO */
 220         props->active_speed     = IB_SPEED_QDR; /* TODO */
 221
 222         return 0;
 223 }
 224
 225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 226                                      const struct ib_gid_attr *attr,
 227                                      void *mlx5_addr)
 228 {
 229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 230         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 231                                                source_l3_address);
 232         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 233                                                source_mac_47_32);
 234
 235         if (!gid)
 236                 return;
 237
 238         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 239
 240         if (is_vlan_dev(attr->ndev)) {
 241                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 242                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 243         }
 244
 245         switch (attr->gid_type) {
 246         case IB_GID_TYPE_IB:
 247                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 248                 break;
 249         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 250                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 251                 break;
 252
 253         default:
 254                 WARN_ON(true);
 255         }
 256
 257         if (attr->gid_type != IB_GID_TYPE_IB) {
 258                 if (ipv6_addr_v4mapped((void *)gid))
 259                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 260                                     MLX5_ROCE_L3_TYPE_IPV4);
 261                 else
 262                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 263                                     MLX5_ROCE_L3_TYPE_IPV6);
 264         }
 265
 266         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 267             !ipv6_addr_v4mapped((void *)gid))
 268                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 269         else
 270                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 271 }
 272
 273 static int set_roce_addr(struct ib_device *device, u8 port_num,
 274                          unsigned int index,
 275                          const union ib_gid *gid,
 276                          const struct ib_gid_attr *attr)
 277 {
 278         struct mlx5_ib_dev *dev = to_mdev(device);
 279         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 280         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 281         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 282         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 283
 284         if (ll != IB_LINK_LAYER_ETHERNET)
 285                 return -EINVAL;
 286
 287         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 288
 289         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 290         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 291         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 292 }
 293
 294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 295                            unsigned int index, const union ib_gid *gid,
 296                            const struct ib_gid_attr *attr,
 297                            __always_unused void **context)
 298 {
 299         return set_roce_addr(device, port_num, index, gid, attr);
 300 }
 301
 302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 303                            unsigned int index, __always_unused void **context)
 304 {
 305         return set_roce_addr(device, port_num, index, NULL, NULL);
 306 }
 307
 308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 309                                int index)
 310 {
 311         struct ib_gid_attr attr;
 312         union ib_gid gid;
 313
 314         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 315                 return 0;
 316
 317         if (!attr.ndev)
 318                 return 0;
 319
 320         dev_put(attr.ndev);
 321
 322         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 323                 return 0;
 324
 325         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 326 }
 327
 328 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 329 {
 330         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 331                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 332         return 0;
 333 }
 334
 335 enum {
 336         MLX5_VPORT_ACCESS_METHOD_MAD,
 337         MLX5_VPORT_ACCESS_METHOD_HCA,
 338         MLX5_VPORT_ACCESS_METHOD_NIC,
 339 };
 340
 341 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 342 {
 343         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 344                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 345
 346         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 347             IB_LINK_LAYER_ETHERNET)
 348                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 349
 350         return MLX5_VPORT_ACCESS_METHOD_HCA;
 351 }
 352
 353 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 354                             struct ib_device_attr *props)
 355 {
 356         u8 tmp;
 357         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 358         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 359         u8 atomic_req_8B_endianness_mode =
 360                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 361
 362         /* Check if HW supports 8 bytes standard atomic operations and capable
 363          * of host endianness respond
 364          */
 365         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 366         if (((atomic_operations & tmp) == tmp) &&
 367             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 368             (atomic_req_8B_endianness_mode)) {
 369                 props->atomic_cap = IB_ATOMIC_HCA;
 370         } else {
 371                 props->atomic_cap = IB_ATOMIC_NONE;
 372         }
 373 }
 374
 375 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 376                                         __be64 *sys_image_guid)
 377 {
 378         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 379         struct mlx5_core_dev *mdev = dev->mdev;
 380         u64 tmp;
 381         int err;
 382
 383         switch (mlx5_get_vport_access_method(ibdev)) {
 384         case MLX5_VPORT_ACCESS_METHOD_MAD:
 385                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 386                                                             sys_image_guid);
 387
 388         case MLX5_VPORT_ACCESS_METHOD_HCA:
 389                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 390                 break;
 391
 392         case MLX5_VPORT_ACCESS_METHOD_NIC:
 393                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 394                 break;
 395
 396         default:
 397                 return -EINVAL;
 398         }
 399
 400         if (!err)
 401                 *sys_image_guid = cpu_to_be64(tmp);
 402
 403         return err;
 404
 405 }
 406
 407 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 408                                 u16 *max_pkeys)
 409 {
 410         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 411         struct mlx5_core_dev *mdev = dev->mdev;
 412
 413         switch (mlx5_get_vport_access_method(ibdev)) {
 414         case MLX5_VPORT_ACCESS_METHOD_MAD:
 415                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 416
 417         case MLX5_VPORT_ACCESS_METHOD_HCA:
 418         case MLX5_VPORT_ACCESS_METHOD_NIC:
 419                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 420                                                 pkey_table_size));
 421                 return 0;
 422
 423         default:
 424                 return -EINVAL;
 425         }
 426 }
 427
 428 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 429                                 u32 *vendor_id)
 430 {
 431         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 432
 433         switch (mlx5_get_vport_access_method(ibdev)) {
 434         case MLX5_VPORT_ACCESS_METHOD_MAD:
 435                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 436
 437         case MLX5_VPORT_ACCESS_METHOD_HCA:
 438         case MLX5_VPORT_ACCESS_METHOD_NIC:
 439                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 440
 441         default:
 442                 return -EINVAL;
 443         }
 444 }
 445
 446 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 447                                 __be64 *node_guid)
 448 {
 449         u64 tmp;
 450         int err;
 451
 452         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 453         case MLX5_VPORT_ACCESS_METHOD_MAD:
 454                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 455
 456         case MLX5_VPORT_ACCESS_METHOD_HCA:
 457                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 458                 break;
 459
 460         case MLX5_VPORT_ACCESS_METHOD_NIC:
 461                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 462                 break;
 463
 464         default:
 465                 return -EINVAL;
 466         }
 467
 468         if (!err)
 469                 *node_guid = cpu_to_be64(tmp);
 470
 471         return err;
 472 }
 473
 474 struct mlx5_reg_node_desc {
 475         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 476 };
 477
 478 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 479 {
 480         struct mlx5_reg_node_desc in;
 481
 482         if (mlx5_use_mad_ifc(dev))
 483                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 484
 485         memset(&in, 0, sizeof(in));
 486
 487         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 488                                     sizeof(struct mlx5_reg_node_desc),
 489                                     MLX5_REG_NODE_DESC, 0, 0);
 490 }
 491
 492 static int mlx5_ib_query_device(struct ib_device *ibdev,
 493                                 struct ib_device_attr *props,
 494                                 struct ib_udata *uhw)
 495 {
 496         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 497         struct mlx5_core_dev *mdev = dev->mdev;
 498         int err = -ENOMEM;
 499         int max_sq_desc;
 500         int max_rq_sg;
 501         int max_sq_sg;
 502         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 503         struct mlx5_ib_query_device_resp resp = {};
 504         size_t resp_len;
 505         u64 max_tso;
 506
 507         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 508         if (uhw->outlen && uhw->outlen < resp_len)
 509                 return -EINVAL;
 510         else
 511                 resp.response_length = resp_len;
 512
 513         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 514                 return -EINVAL;
 515
 516         memset(props, 0, sizeof(*props));
 517         err = mlx5_query_system_image_guid(ibdev,
 518                                            &props->sys_image_guid);
 519         if (err)
 520                 return err;
 521
 522         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 523         if (err)
 524                 return err;
 525
 526         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 527         if (err)
 528                 return err;
 529
 530         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 531                 (fw_rev_min(dev->mdev) << 16) |
 532                 fw_rev_sub(dev->mdev);
 533         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 534                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 535                 IB_DEVICE_SYS_IMAGE_GUID                |
 536                 IB_DEVICE_RC_RNR_NAK_GEN;
 537
 538         if (MLX5_CAP_GEN(mdev, pkv))
 539                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 540         if (MLX5_CAP_GEN(mdev, qkv))
 541                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 542         if (MLX5_CAP_GEN(mdev, apm))
 543                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 544         if (MLX5_CAP_GEN(mdev, xrc))
 545                 props->device_cap_flags |= IB_DEVICE_XRC;
 546         if (MLX5_CAP_GEN(mdev, imaicl)) {
 547                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 548                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 549                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 550                 /* We support 'Gappy' memory registration too */
 551                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 552         }
 553         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 554         if (MLX5_CAP_GEN(mdev, sho)) {
 555                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 556                 /* At this stage no support for signature handover */
 557                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 558                                       IB_PROT_T10DIF_TYPE_2 |
 559                                       IB_PROT_T10DIF_TYPE_3;
 560                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 561                                        IB_GUARD_T10DIF_CSUM;
 562         }
 563         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 564                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 565
 566         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 567                 if (MLX5_CAP_ETH(mdev, csum_cap))
 568                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 569
 570                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 571                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 572                         if (max_tso) {
 573                                 resp.tso_caps.max_tso = 1 << max_tso;
 574                                 resp.tso_caps.supported_qpts |=
 575                                         1 << IB_QPT_RAW_PACKET;
 576                                 resp.response_length += sizeof(resp.tso_caps);
 577                         }
 578                 }
 579
 580                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 581                         resp.rss_caps.rx_hash_function =
 582                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 583                         resp.rss_caps.rx_hash_fields_mask =
 584                                                 MLX5_RX_HASH_SRC_IPV4 |
 585                                                 MLX5_RX_HASH_DST_IPV4 |
 586                                                 MLX5_RX_HASH_SRC_IPV6 |
 587                                                 MLX5_RX_HASH_DST_IPV6 |
 588                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 589                                                 MLX5_RX_HASH_DST_PORT_TCP |
 590                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 591                                                 MLX5_RX_HASH_DST_PORT_UDP;
 592                         resp.response_length += sizeof(resp.rss_caps);
 593                 }
 594         } else {
 595                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 596                         resp.response_length += sizeof(resp.tso_caps);
 597                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 598                         resp.response_length += sizeof(resp.rss_caps);
 599         }
 600
 601         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 602                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 603                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 604         }
 605
 606         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 607             MLX5_CAP_ETH(dev->mdev, scatter_fcs))
 608                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 609
 610         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 611                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 612
 613         props->vendor_part_id      = mdev->pdev->device;
 614         props->hw_ver              = mdev->pdev->revision;
 615
 616         props->max_mr_size         = ~0ull;
 617         props->page_size_cap       = ~(min_page_size - 1);
 618         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 619         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 620         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 621                      sizeof(struct mlx5_wqe_data_seg);
 622         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 623         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 624                      sizeof(struct mlx5_wqe_raddr_seg)) /
 625                 sizeof(struct mlx5_wqe_data_seg);
 626         props->max_sge = min(max_rq_sg, max_sq_sg);
 627         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 628         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 629         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 630         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 631         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 632         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 633         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 634         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 635         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 636         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 637         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 638         props->max_srq_sge         = max_rq_sg - 1;
 639         props->max_fast_reg_page_list_len =
 640                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 641         get_atomic_caps(dev, props);
 642         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 643         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 644         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 645         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 646                                            props->max_mcast_grp;
 647         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 648         props->max_ah = INT_MAX;
 649         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 650         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 651
 652 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 653         if (MLX5_CAP_GEN(mdev, pg))
 654                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 655         props->odp_caps = dev->odp_caps;
 656 #endif
 657
 658         if (MLX5_CAP_GEN(mdev, cd))
 659                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 660
 661         if (!mlx5_core_is_pf(mdev))
 662                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 663
 664         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 665             IB_LINK_LAYER_ETHERNET) {
 666                 props->rss_caps.max_rwq_indirection_tables =
 667                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 668                 props->rss_caps.max_rwq_indirection_table_size =
 669                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 670                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 671                 props->max_wq_type_rq =
 672                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 673         }
 674
 675         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 676                         uhw->outlen)) {
 677                 resp.mlx5_ib_support_multi_pkt_send_wqes =
 678                         MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
 679                 resp.response_length +=
 680                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 681         }
 682
 683         if (field_avail(typeof(resp), reserved, uhw->outlen))
 684                 resp.response_length += sizeof(resp.reserved);
 685
 686         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 687                 resp.cqe_comp_caps.max_num =
 688                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 689                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 690                 resp.cqe_comp_caps.supported_format =
 691                         MLX5_IB_CQE_RES_FORMAT_HASH |
 692                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 693                 resp.response_length += sizeof(resp.cqe_comp_caps);
 694         }
 695
 696         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
 697                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 698                     MLX5_CAP_GEN(mdev, qos)) {
 699                         resp.packet_pacing_caps.qp_rate_limit_max =
 700                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 701                         resp.packet_pacing_caps.qp_rate_limit_min =
 702                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 703                         resp.packet_pacing_caps.supported_qpts |=
 704                                 1 << IB_QPT_RAW_PACKET;
 705                 }
 706                 resp.response_length += sizeof(resp.packet_pacing_caps);
 707         }
 708
 709         if (uhw->outlen) {
 710                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 711
 712                 if (err)
 713                         return err;
 714         }
 715
 716         return 0;
 717 }
 718
 719 enum mlx5_ib_width {
 720         MLX5_IB_WIDTH_1X        = 1 << 0,
 721         MLX5_IB_WIDTH_2X        = 1 << 1,
 722         MLX5_IB_WIDTH_4X        = 1 << 2,
 723         MLX5_IB_WIDTH_8X        = 1 << 3,
 724         MLX5_IB_WIDTH_12X       = 1 << 4
 725 };
 726
 727 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 728                                   u8 *ib_width)
 729 {
 730         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 731         int err = 0;
 732
 733         if (active_width & MLX5_IB_WIDTH_1X) {
 734                 *ib_width = IB_WIDTH_1X;
 735         } else if (active_width & MLX5_IB_WIDTH_2X) {
 736                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 737                             (int)active_width);
 738                 err = -EINVAL;
 739         } else if (active_width & MLX5_IB_WIDTH_4X) {
 740                 *ib_width = IB_WIDTH_4X;
 741         } else if (active_width & MLX5_IB_WIDTH_8X) {
 742                 *ib_width = IB_WIDTH_8X;
 743         } else if (active_width & MLX5_IB_WIDTH_12X) {
 744                 *ib_width = IB_WIDTH_12X;
 745         } else {
 746                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 747                             (int)active_width);
 748                 err = -EINVAL;
 749         }
 750
 751         return err;
 752 }
 753
 754 static int mlx5_mtu_to_ib_mtu(int mtu)
 755 {
 756         switch (mtu) {
 757         case 256: return 1;
 758         case 512: return 2;
 759         case 1024: return 3;
 760         case 2048: return 4;
 761         case 4096: return 5;
 762         default:
 763                 pr_warn("invalid mtu\n");
 764                 return -1;
 765         }
 766 }
 767
 768 enum ib_max_vl_num {
 769         __IB_MAX_VL_0           = 1,
 770         __IB_MAX_VL_0_1         = 2,
 771         __IB_MAX_VL_0_3         = 3,
 772         __IB_MAX_VL_0_7         = 4,
 773         __IB_MAX_VL_0_14        = 5,
 774 };
 775
 776 enum mlx5_vl_hw_cap {
 777         MLX5_VL_HW_0    = 1,
 778         MLX5_VL_HW_0_1  = 2,
 779         MLX5_VL_HW_0_2  = 3,
 780         MLX5_VL_HW_0_3  = 4,
 781         MLX5_VL_HW_0_4  = 5,
 782         MLX5_VL_HW_0_5  = 6,
 783         MLX5_VL_HW_0_6  = 7,
 784         MLX5_VL_HW_0_7  = 8,
 785         MLX5_VL_HW_0_14 = 15
 786 };
 787
 788 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 789                                 u8 *max_vl_num)
 790 {
 791         switch (vl_hw_cap) {
 792         case MLX5_VL_HW_0:
 793                 *max_vl_num = __IB_MAX_VL_0;
 794                 break;
 795         case MLX5_VL_HW_0_1:
 796                 *max_vl_num = __IB_MAX_VL_0_1;
 797                 break;
 798         case MLX5_VL_HW_0_3:
 799                 *max_vl_num = __IB_MAX_VL_0_3;
 800                 break;
 801         case MLX5_VL_HW_0_7:
 802                 *max_vl_num = __IB_MAX_VL_0_7;
 803                 break;
 804         case MLX5_VL_HW_0_14:
 805                 *max_vl_num = __IB_MAX_VL_0_14;
 806                 break;
 807
 808         default:
 809                 return -EINVAL;
 810         }
 811
 812         return 0;
 813 }
 814
 815 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 816                                struct ib_port_attr *props)
 817 {
 818         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 819         struct mlx5_core_dev *mdev = dev->mdev;
 820         struct mlx5_hca_vport_context *rep;
 821         u16 max_mtu;
 822         u16 oper_mtu;
 823         int err;
 824         u8 ib_link_width_oper;
 825         u8 vl_hw_cap;
 826
 827         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 828         if (!rep) {
 829                 err = -ENOMEM;
 830                 goto out;
 831         }
 832
 833         memset(props, 0, sizeof(*props));
 834
 835         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 836         if (err)
 837                 goto out;
 838
 839         props->lid              = rep->lid;
 840         props->lmc              = rep->lmc;
 841         props->sm_lid           = rep->sm_lid;
 842         props->sm_sl            = rep->sm_sl;
 843         props->state            = rep->vport_state;
 844         props->phys_state       = rep->port_physical_state;
 845         props->port_cap_flags   = rep->cap_mask1;
 846         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 847         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 848         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 849         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 850         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 851         props->subnet_timeout   = rep->subnet_timeout;
 852         props->init_type_reply  = rep->init_type_reply;
 853         props->grh_required     = rep->grh_required;
 854
 855         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 856         if (err)
 857                 goto out;
 858
 859         err = translate_active_width(ibdev, ib_link_width_oper,
 860                                      &props->active_width);
 861         if (err)
 862                 goto out;
 863         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 864         if (err)
 865                 goto out;
 866
 867         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 868
 869         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 870
 871         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 872
 873         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 874
 875         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 876         if (err)
 877                 goto out;
 878
 879         err = translate_max_vl_num(ibdev, vl_hw_cap,
 880                                    &props->max_vl_num);
 881 out:
 882         kfree(rep);
 883         return err;
 884 }
 885
 886 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 887                        struct ib_port_attr *props)
 888 {
 889         switch (mlx5_get_vport_access_method(ibdev)) {
 890         case MLX5_VPORT_ACCESS_METHOD_MAD:
 891                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 892
 893         case MLX5_VPORT_ACCESS_METHOD_HCA:
 894                 return mlx5_query_hca_port(ibdev, port, props);
 895
 896         case MLX5_VPORT_ACCESS_METHOD_NIC:
 897                 return mlx5_query_port_roce(ibdev, port, props);
 898
 899         default:
 900                 return -EINVAL;
 901         }
 902 }
 903
 904 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 905                              union ib_gid *gid)
 906 {
 907         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 908         struct mlx5_core_dev *mdev = dev->mdev;
 909
 910         switch (mlx5_get_vport_access_method(ibdev)) {
 911         case MLX5_VPORT_ACCESS_METHOD_MAD:
 912                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 913
 914         case MLX5_VPORT_ACCESS_METHOD_HCA:
 915                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 916
 917         default:
 918                 return -EINVAL;
 919         }
 920
 921 }
 922
 923 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 924                               u16 *pkey)
 925 {
 926         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 927         struct mlx5_core_dev *mdev = dev->mdev;
 928
 929         switch (mlx5_get_vport_access_method(ibdev)) {
 930         case MLX5_VPORT_ACCESS_METHOD_MAD:
 931                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 932
 933         case MLX5_VPORT_ACCESS_METHOD_HCA:
 934         case MLX5_VPORT_ACCESS_METHOD_NIC:
 935                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 936                                                  pkey);
 937         default:
 938                 return -EINVAL;
 939         }
 940 }
 941
 942 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 943                                  struct ib_device_modify *props)
 944 {
 945         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 946         struct mlx5_reg_node_desc in;
 947         struct mlx5_reg_node_desc out;
 948         int err;
 949
 950         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 951                 return -EOPNOTSUPP;
 952
 953         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 954                 return 0;
 955
 956         /*
 957          * If possible, pass node desc to FW, so it can generate
 958          * a 144 trap.  If cmd fails, just ignore.
 959          */
 960         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 961         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 962                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 963         if (err)
 964                 return err;
 965
 966         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 967
 968         return err;
 969 }
 970
 971 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
 972                                struct ib_port_modify *props)
 973 {
 974         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 975         struct ib_port_attr attr;
 976         u32 tmp;
 977         int err;
 978
 979         mutex_lock(&dev->cap_mask_mutex);
 980
 981         err = mlx5_ib_query_port(ibdev, port, &attr);
 982         if (err)
 983                 goto out;
 984
 985         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
 986                 ~props->clr_port_cap_mask;
 987
 988         err = mlx5_set_port_caps(dev->mdev, port, tmp);
 989
 990 out:
 991         mutex_unlock(&dev->cap_mask_mutex);
 992         return err;
 993 }
 994
 995 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
 996                                                   struct ib_udata *udata)
 997 {
 998         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 999         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1000         struct mlx5_ib_alloc_ucontext_resp resp = {};
1001         struct mlx5_ib_ucontext *context;
1002         struct mlx5_uuar_info *uuari;
1003         struct mlx5_uar *uars;
1004         int gross_uuars;
1005         int num_uars;
1006         int ver;
1007         int uuarn;
1008         int err;
1009         int i;
1010         size_t reqlen;
1011         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1012                                      max_cqe_version);
1013
1014         if (!dev->ib_active)
1015                 return ERR_PTR(-EAGAIN);
1016
1017         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1018                 return ERR_PTR(-EINVAL);
1019
1020         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1021         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1022                 ver = 0;
1023         else if (reqlen >= min_req_v2)
1024                 ver = 2;
1025         else
1026                 return ERR_PTR(-EINVAL);
1027
1028         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1029         if (err)
1030                 return ERR_PTR(err);
1031
1032         if (req.flags)
1033                 return ERR_PTR(-EINVAL);
1034
1035         if (req.total_num_uuars > MLX5_MAX_UUARS)
1036                 return ERR_PTR(-ENOMEM);
1037
1038         if (req.total_num_uuars == 0)
1039                 return ERR_PTR(-EINVAL);
1040
1041         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1042                 return ERR_PTR(-EOPNOTSUPP);
1043
1044         if (reqlen > sizeof(req) &&
1045             !ib_is_udata_cleared(udata, sizeof(req),
1046                                  reqlen - sizeof(req)))
1047                 return ERR_PTR(-EOPNOTSUPP);
1048
1049         req.total_num_uuars = ALIGN(req.total_num_uuars,
1050                                     MLX5_NON_FP_BF_REGS_PER_PAGE);
1051         if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1052                 return ERR_PTR(-EINVAL);
1053
1054         num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1055         gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1056         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1057         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1058                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1059         resp.cache_line_size = cache_line_size();
1060         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1061         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1062         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1063         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1064         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1065         resp.cqe_version = min_t(__u8,
1066                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1067                                  req.max_cqe_version);
1068         resp.response_length = min(offsetof(typeof(resp), response_length) +
1069                                    sizeof(resp.response_length), udata->outlen);
1070
1071         context = kzalloc(sizeof(*context), GFP_KERNEL);
1072         if (!context)
1073                 return ERR_PTR(-ENOMEM);
1074
1075         uuari = &context->uuari;
1076         mutex_init(&uuari->lock);
1077         uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1078         if (!uars) {
1079                 err = -ENOMEM;
1080                 goto out_ctx;
1081         }
1082
1083         uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1084                                 sizeof(*uuari->bitmap),
1085                                 GFP_KERNEL);
1086         if (!uuari->bitmap) {
1087                 err = -ENOMEM;
1088                 goto out_uar_ctx;
1089         }
1090         /*
1091          * clear all fast path uuars
1092          */
1093         for (i = 0; i < gross_uuars; i++) {
1094                 uuarn = i & 3;
1095                 if (uuarn == 2 || uuarn == 3)
1096                         set_bit(i, uuari->bitmap);
1097         }
1098
1099         uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1100         if (!uuari->count) {
1101                 err = -ENOMEM;
1102                 goto out_bitmap;
1103         }
1104
1105         for (i = 0; i < num_uars; i++) {
1106                 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1107                 if (err)
1108                         goto out_count;
1109         }
1110
1111 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1112         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1113 #endif
1114
1115         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1116                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1117                                                        &context->tdn);
1118                 if (err)
1119                         goto out_uars;
1120         }
1121
1122         INIT_LIST_HEAD(&context->vma_private_list);
1123         INIT_LIST_HEAD(&context->db_page_list);
1124         mutex_init(&context->db_page_mutex);
1125
1126         resp.tot_uuars = req.total_num_uuars;
1127         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1128
1129         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1130                 resp.response_length += sizeof(resp.cqe_version);
1131
1132         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1133                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1134                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1135                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1136         }
1137
1138         /*
1139          * We don't want to expose information from the PCI bar that is located
1140          * after 4096 bytes, so if the arch only supports larger pages, let's
1141          * pretend we don't support reading the HCA's core clock. This is also
1142          * forced by mmap function.
1143          */
1144         if (PAGE_SIZE <= 4096 &&
1145             field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1146                 resp.comp_mask |=
1147                         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1148                 resp.hca_core_clock_offset =
1149                         offsetof(struct mlx5_init_seg, internal_timer_h) %
1150                         PAGE_SIZE;
1151                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1152                                         sizeof(resp.reserved2);
1153         }
1154
1155         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1156         if (err)
1157                 goto out_td;
1158
1159         uuari->ver = ver;
1160         uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1161         uuari->uars = uars;
1162         uuari->num_uars = num_uars;
1163         context->cqe_version = resp.cqe_version;
1164
1165         return &context->ibucontext;
1166
1167 out_td:
1168         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1169                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1170
1171 out_uars:
1172         for (i--; i >= 0; i--)
1173                 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1174 out_count:
1175         kfree(uuari->count);
1176
1177 out_bitmap:
1178         kfree(uuari->bitmap);
1179
1180 out_uar_ctx:
1181         kfree(uars);
1182
1183 out_ctx:
1184         kfree(context);
1185         return ERR_PTR(err);
1186 }
1187
1188 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1189 {
1190         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1191         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1192         struct mlx5_uuar_info *uuari = &context->uuari;
1193         int i;
1194
1195         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1196                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1197
1198         for (i = 0; i < uuari->num_uars; i++) {
1199                 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1200                         mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1201         }
1202
1203         kfree(uuari->count);
1204         kfree(uuari->bitmap);
1205         kfree(uuari->uars);
1206         kfree(context);
1207
1208         return 0;
1209 }
1210
1211 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1212 {
1213         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1214 }
1215
1216 static int get_command(unsigned long offset)
1217 {
1218         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1219 }
1220
1221 static int get_arg(unsigned long offset)
1222 {
1223         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1224 }
1225
1226 static int get_index(unsigned long offset)
1227 {
1228         return get_arg(offset);
1229 }
1230
1231 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1232 {
1233         /* vma_open is called when a new VMA is created on top of our VMA.  This
1234          * is done through either mremap flow or split_vma (usually due to
1235          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1236          * as this VMA is strongly hardware related.  Therefore we set the
1237          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1238          * calling us again and trying to do incorrect actions.  We assume that
1239          * the original VMA size is exactly a single page, and therefore all
1240          * "splitting" operation will not happen to it.
1241          */
1242         area->vm_ops = NULL;
1243 }
1244
1245 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1246 {
1247         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1248
1249         /* It's guaranteed that all VMAs opened on a FD are closed before the
1250          * file itself is closed, therefore no sync is needed with the regular
1251          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1252          * However need a sync with accessing the vma as part of
1253          * mlx5_ib_disassociate_ucontext.
1254          * The close operation is usually called under mm->mmap_sem except when
1255          * process is exiting.
1256          * The exiting case is handled explicitly as part of
1257          * mlx5_ib_disassociate_ucontext.
1258          */
1259         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1260
1261         /* setting the vma context pointer to null in the mlx5_ib driver's
1262          * private data, to protect a race condition in
1263          * mlx5_ib_disassociate_ucontext().
1264          */
1265         mlx5_ib_vma_priv_data->vma = NULL;
1266         list_del(&mlx5_ib_vma_priv_data->list);
1267         kfree(mlx5_ib_vma_priv_data);
1268 }
1269
1270 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1271         .open = mlx5_ib_vma_open,
1272         .close = mlx5_ib_vma_close
1273 };
1274
1275 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1276                                 struct mlx5_ib_ucontext *ctx)
1277 {
1278         struct mlx5_ib_vma_private_data *vma_prv;
1279         struct list_head *vma_head = &ctx->vma_private_list;
1280
1281         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1282         if (!vma_prv)
1283                 return -ENOMEM;
1284
1285         vma_prv->vma = vma;
1286         vma->vm_private_data = vma_prv;
1287         vma->vm_ops =  &mlx5_ib_vm_ops;
1288
1289         list_add(&vma_prv->list, vma_head);
1290
1291         return 0;
1292 }
1293
1294 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1295 {
1296         int ret;
1297         struct vm_area_struct *vma;
1298         struct mlx5_ib_vma_private_data *vma_private, *n;
1299         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1300         struct task_struct *owning_process  = NULL;
1301         struct mm_struct   *owning_mm       = NULL;
1302
1303         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1304         if (!owning_process)
1305                 return;
1306
1307         owning_mm = get_task_mm(owning_process);
1308         if (!owning_mm) {
1309                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1310                 while (1) {
1311                         put_task_struct(owning_process);
1312                         usleep_range(1000, 2000);
1313                         owning_process = get_pid_task(ibcontext->tgid,
1314                                                       PIDTYPE_PID);
1315                         if (!owning_process ||
1316                             owning_process->state == TASK_DEAD) {
1317                                 pr_info("disassociate ucontext done, task was terminated\n");
1318                                 /* in case task was dead need to release the
1319                                  * task struct.
1320                                  */
1321                                 if (owning_process)
1322                                         put_task_struct(owning_process);
1323                                 return;
1324                         }
1325                 }
1326         }
1327
1328         /* need to protect from a race on closing the vma as part of
1329          * mlx5_ib_vma_close.
1330          */
1331         down_read(&owning_mm->mmap_sem);
1332         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1333                                  list) {
1334                 vma = vma_private->vma;
1335                 ret = zap_vma_ptes(vma, vma->vm_start,
1336                                    PAGE_SIZE);
1337                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1338                 /* context going to be destroyed, should
1339                  * not access ops any more.
1340                  */
1341                 vma->vm_ops = NULL;
1342                 list_del(&vma_private->list);
1343                 kfree(vma_private);
1344         }
1345         up_read(&owning_mm->mmap_sem);
1346         mmput(owning_mm);
1347         put_task_struct(owning_process);
1348 }
1349
1350 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1351 {
1352         switch (cmd) {
1353         case MLX5_IB_MMAP_WC_PAGE:
1354                 return "WC";
1355         case MLX5_IB_MMAP_REGULAR_PAGE:
1356                 return "best effort WC";
1357         case MLX5_IB_MMAP_NC_PAGE:
1358                 return "NC";
1359         default:
1360                 return NULL;
1361         }
1362 }
1363
1364 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1365                     struct vm_area_struct *vma,
1366                     struct mlx5_ib_ucontext *context)
1367 {
1368         struct mlx5_uuar_info *uuari = &context->uuari;
1369         int err;
1370         unsigned long idx;
1371         phys_addr_t pfn, pa;
1372         pgprot_t prot;
1373
1374         switch (cmd) {
1375         case MLX5_IB_MMAP_WC_PAGE:
1376 /* Some architectures don't support WC memory */
1377 #if defined(CONFIG_X86)
1378                 if (!pat_enabled())
1379                         return -EPERM;
1380 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1381                         return -EPERM;
1382 #endif
1383         /* fall through */
1384         case MLX5_IB_MMAP_REGULAR_PAGE:
1385                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1386                 prot = pgprot_writecombine(vma->vm_page_prot);
1387                 break;
1388         case MLX5_IB_MMAP_NC_PAGE:
1389                 prot = pgprot_noncached(vma->vm_page_prot);
1390                 break;
1391         default:
1392                 return -EINVAL;
1393         }
1394
1395         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1396                 return -EINVAL;
1397
1398         idx = get_index(vma->vm_pgoff);
1399         if (idx >= uuari->num_uars)
1400                 return -EINVAL;
1401
1402         pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1403         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1404
1405         vma->vm_page_prot = prot;
1406         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1407                                  PAGE_SIZE, vma->vm_page_prot);
1408         if (err) {
1409                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1410                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1411                 return -EAGAIN;
1412         }
1413
1414         pa = pfn << PAGE_SHIFT;
1415         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1416                     vma->vm_start, &pa);
1417
1418         return mlx5_ib_set_vma_data(vma, context);
1419 }
1420
1421 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1422 {
1423         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1424         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1425         unsigned long command;
1426         phys_addr_t pfn;
1427
1428         command = get_command(vma->vm_pgoff);
1429         switch (command) {
1430         case MLX5_IB_MMAP_WC_PAGE:
1431         case MLX5_IB_MMAP_NC_PAGE:
1432         case MLX5_IB_MMAP_REGULAR_PAGE:
1433                 return uar_mmap(dev, command, vma, context);
1434
1435         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1436                 return -ENOSYS;
1437
1438         case MLX5_IB_MMAP_CORE_CLOCK:
1439                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1440                         return -EINVAL;
1441
1442                 if (vma->vm_flags & VM_WRITE)
1443                         return -EPERM;
1444
1445                 /* Don't expose to user-space information it shouldn't have */
1446                 if (PAGE_SIZE > 4096)
1447                         return -EOPNOTSUPP;
1448
1449                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1450                 pfn = (dev->mdev->iseg_base +
1451                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1452                         PAGE_SHIFT;
1453                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1454                                        PAGE_SIZE, vma->vm_page_prot))
1455                         return -EAGAIN;
1456
1457                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1458                             vma->vm_start,
1459                             (unsigned long long)pfn << PAGE_SHIFT);
1460                 break;
1461
1462         default:
1463                 return -EINVAL;
1464         }
1465
1466         return 0;
1467 }
1468
1469 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1470                                       struct ib_ucontext *context,
1471                                       struct ib_udata *udata)
1472 {
1473         struct mlx5_ib_alloc_pd_resp resp;
1474         struct mlx5_ib_pd *pd;
1475         int err;
1476
1477         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1478         if (!pd)
1479                 return ERR_PTR(-ENOMEM);
1480
1481         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1482         if (err) {
1483                 kfree(pd);
1484                 return ERR_PTR(err);
1485         }
1486
1487         if (context) {
1488                 resp.pdn = pd->pdn;
1489                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1490                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1491                         kfree(pd);
1492                         return ERR_PTR(-EFAULT);
1493                 }
1494         }
1495
1496         return &pd->ibpd;
1497 }
1498
1499 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1500 {
1501         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1502         struct mlx5_ib_pd *mpd = to_mpd(pd);
1503
1504         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1505         kfree(mpd);
1506
1507         return 0;
1508 }
1509
1510 enum {
1511         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1512         MATCH_CRITERIA_ENABLE_MISC_BIT,
1513         MATCH_CRITERIA_ENABLE_INNER_BIT
1514 };
1515
1516 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1517         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1518                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1519
1520 static u8 get_match_criteria_enable(u32 *match_criteria)
1521 {
1522         u8 match_criteria_enable;
1523
1524         match_criteria_enable =
1525                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1526                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1527         match_criteria_enable |=
1528                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1529                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1530         match_criteria_enable |=
1531                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1532                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1533
1534         return match_criteria_enable;
1535 }
1536
1537 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1538 {
1539         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1540         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1541 }
1542
1543 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1544                            bool inner)
1545 {
1546         if (inner) {
1547                 MLX5_SET(fte_match_set_misc,
1548                          misc_c, inner_ipv6_flow_label, mask);
1549                 MLX5_SET(fte_match_set_misc,
1550                          misc_v, inner_ipv6_flow_label, val);
1551         } else {
1552                 MLX5_SET(fte_match_set_misc,
1553                          misc_c, outer_ipv6_flow_label, mask);
1554                 MLX5_SET(fte_match_set_misc,
1555                          misc_v, outer_ipv6_flow_label, val);
1556         }
1557 }
1558
1559 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1560 {
1561         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1562         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1563         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1564         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1565 }
1566
1567 #define LAST_ETH_FIELD vlan_tag
1568 #define LAST_IB_FIELD sl
1569 #define LAST_IPV4_FIELD tos
1570 #define LAST_IPV6_FIELD traffic_class
1571 #define LAST_TCP_UDP_FIELD src_port
1572 #define LAST_TUNNEL_FIELD tunnel_id
1573
1574 /* Field is the last supported field */
1575 #define FIELDS_NOT_SUPPORTED(filter, field)\
1576         memchr_inv((void *)&filter.field  +\
1577                    sizeof(filter.field), 0,\
1578                    sizeof(filter) -\
1579                    offsetof(typeof(filter), field) -\
1580                    sizeof(filter.field))
1581
1582 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1583                            const union ib_flow_spec *ib_spec)
1584 {
1585         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1586                                            misc_parameters);
1587         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1588                                            misc_parameters);
1589         void *headers_c;
1590         void *headers_v;
1591
1592         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1593                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1594                                          inner_headers);
1595                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1596                                          inner_headers);
1597         } else {
1598                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1599                                          outer_headers);
1600                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1601                                          outer_headers);
1602         }
1603
1604         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1605         case IB_FLOW_SPEC_ETH:
1606                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1607                         return -ENOTSUPP;
1608
1609                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1610                                              dmac_47_16),
1611                                 ib_spec->eth.mask.dst_mac);
1612                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1613                                              dmac_47_16),
1614                                 ib_spec->eth.val.dst_mac);
1615
1616                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1617                                              smac_47_16),
1618                                 ib_spec->eth.mask.src_mac);
1619                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1620                                              smac_47_16),
1621                                 ib_spec->eth.val.src_mac);
1622
1623                 if (ib_spec->eth.mask.vlan_tag) {
1624                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1625                                  vlan_tag, 1);
1626                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1627                                  vlan_tag, 1);
1628
1629                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1630                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1631                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1632                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1633
1634                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1635                                  first_cfi,
1636                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1637                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1638                                  first_cfi,
1639                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1640
1641                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1642                                  first_prio,
1643                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1644                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1645                                  first_prio,
1646                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1647                 }
1648                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1649                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1650                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1651                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1652                 break;
1653         case IB_FLOW_SPEC_IPV4:
1654                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1655                         return -ENOTSUPP;
1656
1657                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1658                          ethertype, 0xffff);
1659                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1660                          ethertype, ETH_P_IP);
1661
1662                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1663                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1664                        &ib_spec->ipv4.mask.src_ip,
1665                        sizeof(ib_spec->ipv4.mask.src_ip));
1666                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1667                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1668                        &ib_spec->ipv4.val.src_ip,
1669                        sizeof(ib_spec->ipv4.val.src_ip));
1670                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1671                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1672                        &ib_spec->ipv4.mask.dst_ip,
1673                        sizeof(ib_spec->ipv4.mask.dst_ip));
1674                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1675                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1676                        &ib_spec->ipv4.val.dst_ip,
1677                        sizeof(ib_spec->ipv4.val.dst_ip));
1678
1679                 set_tos(headers_c, headers_v,
1680                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1681
1682                 set_proto(headers_c, headers_v,
1683                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1684                 break;
1685         case IB_FLOW_SPEC_IPV6:
1686                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1687                         return -ENOTSUPP;
1688
1689                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1690                          ethertype, 0xffff);
1691                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1692                          ethertype, ETH_P_IPV6);
1693
1694                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1695                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1696                        &ib_spec->ipv6.mask.src_ip,
1697                        sizeof(ib_spec->ipv6.mask.src_ip));
1698                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1699                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1700                        &ib_spec->ipv6.val.src_ip,
1701                        sizeof(ib_spec->ipv6.val.src_ip));
1702                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1703                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1704                        &ib_spec->ipv6.mask.dst_ip,
1705                        sizeof(ib_spec->ipv6.mask.dst_ip));
1706                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1707                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1708                        &ib_spec->ipv6.val.dst_ip,
1709                        sizeof(ib_spec->ipv6.val.dst_ip));
1710
1711                 set_tos(headers_c, headers_v,
1712                         ib_spec->ipv6.mask.traffic_class,
1713                         ib_spec->ipv6.val.traffic_class);
1714
1715                 set_proto(headers_c, headers_v,
1716                           ib_spec->ipv6.mask.next_hdr,
1717                           ib_spec->ipv6.val.next_hdr);
1718
1719                 set_flow_label(misc_params_c, misc_params_v,
1720                                ntohl(ib_spec->ipv6.mask.flow_label),
1721                                ntohl(ib_spec->ipv6.val.flow_label),
1722                                ib_spec->type & IB_FLOW_SPEC_INNER);
1723
1724                 break;
1725         case IB_FLOW_SPEC_TCP:
1726                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1727                                          LAST_TCP_UDP_FIELD))
1728                         return -ENOTSUPP;
1729
1730                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1731                          0xff);
1732                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1733                          IPPROTO_TCP);
1734
1735                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1736                          ntohs(ib_spec->tcp_udp.mask.src_port));
1737                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1738                          ntohs(ib_spec->tcp_udp.val.src_port));
1739
1740                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1741                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1742                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1743                          ntohs(ib_spec->tcp_udp.val.dst_port));
1744                 break;
1745         case IB_FLOW_SPEC_UDP:
1746                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1747                                          LAST_TCP_UDP_FIELD))
1748                         return -ENOTSUPP;
1749
1750                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1751                          0xff);
1752                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1753                          IPPROTO_UDP);
1754
1755                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1756                          ntohs(ib_spec->tcp_udp.mask.src_port));
1757                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1758                          ntohs(ib_spec->tcp_udp.val.src_port));
1759
1760                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1761                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1762                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1763                          ntohs(ib_spec->tcp_udp.val.dst_port));
1764                 break;
1765         case IB_FLOW_SPEC_VXLAN_TUNNEL:
1766                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1767                                          LAST_TUNNEL_FIELD))
1768                         return -ENOTSUPP;
1769
1770                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1771                          ntohl(ib_spec->tunnel.mask.tunnel_id));
1772                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1773                          ntohl(ib_spec->tunnel.val.tunnel_id));
1774                 break;
1775         default:
1776                 return -EINVAL;
1777         }
1778
1779         return 0;
1780 }
1781
1782 /* If a flow could catch both multicast and unicast packets,
1783  * it won't fall into the multicast flow steering table and this rule
1784  * could steal other multicast packets.
1785  */
1786 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1787 {
1788         struct ib_flow_spec_eth *eth_spec;
1789
1790         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1791             ib_attr->size < sizeof(struct ib_flow_attr) +
1792             sizeof(struct ib_flow_spec_eth) ||
1793             ib_attr->num_of_specs < 1)
1794                 return false;
1795
1796         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1797         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1798             eth_spec->size != sizeof(*eth_spec))
1799                 return false;
1800
1801         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1802                is_multicast_ether_addr(eth_spec->val.dst_mac);
1803 }
1804
1805 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1806 {
1807         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1808         bool has_ipv4_spec = false;
1809         bool eth_type_ipv4 = true;
1810         unsigned int spec_index;
1811
1812         /* Validate that ethertype is correct */
1813         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1814                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1815                     ib_spec->eth.mask.ether_type) {
1816                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1817                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1818                                 eth_type_ipv4 = false;
1819                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1820                         has_ipv4_spec = true;
1821                 }
1822                 ib_spec = (void *)ib_spec + ib_spec->size;
1823         }
1824         return !has_ipv4_spec || eth_type_ipv4;
1825 }
1826
1827 static void put_flow_table(struct mlx5_ib_dev *dev,
1828                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1829 {
1830         prio->refcount -= !!ft_added;
1831         if (!prio->refcount) {
1832                 mlx5_destroy_flow_table(prio->flow_table);
1833                 prio->flow_table = NULL;
1834         }
1835 }
1836
1837 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1838 {
1839         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1840         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1841                                                           struct mlx5_ib_flow_handler,
1842                                                           ibflow);
1843         struct mlx5_ib_flow_handler *iter, *tmp;
1844
1845         mutex_lock(&dev->flow_db.lock);
1846
1847         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1848                 mlx5_del_flow_rules(iter->rule);
1849                 put_flow_table(dev, iter->prio, true);
1850                 list_del(&iter->list);
1851                 kfree(iter);
1852         }
1853
1854         mlx5_del_flow_rules(handler->rule);
1855         put_flow_table(dev, handler->prio, true);
1856         mutex_unlock(&dev->flow_db.lock);
1857
1858         kfree(handler);
1859
1860         return 0;
1861 }
1862
1863 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1864 {
1865         priority *= 2;
1866         if (!dont_trap)
1867                 priority++;
1868         return priority;
1869 }
1870
1871 enum flow_table_type {
1872         MLX5_IB_FT_RX,
1873         MLX5_IB_FT_TX
1874 };
1875
1876 #define MLX5_FS_MAX_TYPES        10
1877 #define MLX5_FS_MAX_ENTRIES      32000UL
1878 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1879                                                 struct ib_flow_attr *flow_attr,
1880                                                 enum flow_table_type ft_type)
1881 {
1882         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1883         struct mlx5_flow_namespace *ns = NULL;
1884         struct mlx5_ib_flow_prio *prio;
1885         struct mlx5_flow_table *ft;
1886         int num_entries;
1887         int num_groups;
1888         int priority;
1889         int err = 0;
1890
1891         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1892                 if (flow_is_multicast_only(flow_attr) &&
1893                     !dont_trap)
1894                         priority = MLX5_IB_FLOW_MCAST_PRIO;
1895                 else
1896                         priority = ib_prio_to_core_prio(flow_attr->priority,
1897                                                         dont_trap);
1898                 ns = mlx5_get_flow_namespace(dev->mdev,
1899                                              MLX5_FLOW_NAMESPACE_BYPASS);
1900                 num_entries = MLX5_FS_MAX_ENTRIES;
1901                 num_groups = MLX5_FS_MAX_TYPES;
1902                 prio = &dev->flow_db.prios[priority];
1903         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1904                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1905                 ns = mlx5_get_flow_namespace(dev->mdev,
1906                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
1907                 build_leftovers_ft_param(&priority,
1908                                          &num_entries,
1909                                          &num_groups);
1910                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1911         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1912                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1913                                         allow_sniffer_and_nic_rx_shared_tir))
1914                         return ERR_PTR(-ENOTSUPP);
1915
1916                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1917                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1918                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1919
1920                 prio = &dev->flow_db.sniffer[ft_type];
1921                 priority = 0;
1922                 num_entries = 1;
1923                 num_groups = 1;
1924         }
1925
1926         if (!ns)
1927                 return ERR_PTR(-ENOTSUPP);
1928
1929         ft = prio->flow_table;
1930         if (!ft) {
1931                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1932                                                          num_entries,
1933                                                          num_groups,
1934                                                          0, 0);
1935
1936                 if (!IS_ERR(ft)) {
1937                         prio->refcount = 0;
1938                         prio->flow_table = ft;
1939                 } else {
1940                         err = PTR_ERR(ft);
1941                 }
1942         }
1943
1944         return err ? ERR_PTR(err) : prio;
1945 }
1946
1947 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1948                                                      struct mlx5_ib_flow_prio *ft_prio,
1949                                                      const struct ib_flow_attr *flow_attr,
1950                                                      struct mlx5_flow_destination *dst)
1951 {
1952         struct mlx5_flow_table  *ft = ft_prio->flow_table;
1953         struct mlx5_ib_flow_handler *handler;
1954         struct mlx5_flow_act flow_act = {0};
1955         struct mlx5_flow_spec *spec;
1956         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1957         unsigned int spec_index;
1958         int err = 0;
1959
1960         if (!is_valid_attr(flow_attr))
1961                 return ERR_PTR(-EINVAL);
1962
1963         spec = mlx5_vzalloc(sizeof(*spec));
1964         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1965         if (!handler || !spec) {
1966                 err = -ENOMEM;
1967                 goto free;
1968         }
1969
1970         INIT_LIST_HEAD(&handler->list);
1971
1972         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1973                 err = parse_flow_attr(spec->match_criteria,
1974                                       spec->match_value, ib_flow);
1975                 if (err < 0)
1976                         goto free;
1977
1978                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1979         }
1980
1981         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1982         flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1983                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1984         flow_act.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1985         handler->rule = mlx5_add_flow_rules(ft, spec,
1986                                             &flow_act,
1987                                             dst, 1);
1988
1989         if (IS_ERR(handler->rule)) {
1990                 err = PTR_ERR(handler->rule);
1991                 goto free;
1992         }
1993
1994         ft_prio->refcount++;
1995         handler->prio = ft_prio;
1996
1997         ft_prio->flow_table = ft;
1998 free:
1999         if (err)
2000                 kfree(handler);
2001         kvfree(spec);
2002         return err ? ERR_PTR(err) : handler;
2003 }
2004
2005 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2006                                                           struct mlx5_ib_flow_prio *ft_prio,
2007                                                           struct ib_flow_attr *flow_attr,
2008                                                           struct mlx5_flow_destination *dst)
2009 {
2010         struct mlx5_ib_flow_handler *handler_dst = NULL;
2011         struct mlx5_ib_flow_handler *handler = NULL;
2012
2013         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2014         if (!IS_ERR(handler)) {
2015                 handler_dst = create_flow_rule(dev, ft_prio,
2016                                                flow_attr, dst);
2017                 if (IS_ERR(handler_dst)) {
2018                         mlx5_del_flow_rules(handler->rule);
2019                         ft_prio->refcount--;
2020                         kfree(handler);
2021                         handler = handler_dst;
2022                 } else {
2023                         list_add(&handler_dst->list, &handler->list);
2024                 }
2025         }
2026
2027         return handler;
2028 }
2029 enum {
2030         LEFTOVERS_MC,
2031         LEFTOVERS_UC,
2032 };
2033
2034 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2035                                                           struct mlx5_ib_flow_prio *ft_prio,
2036                                                           struct ib_flow_attr *flow_attr,
2037                                                           struct mlx5_flow_destination *dst)
2038 {
2039         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2040         struct mlx5_ib_flow_handler *handler = NULL;
2041
2042         static struct {
2043                 struct ib_flow_attr     flow_attr;
2044                 struct ib_flow_spec_eth eth_flow;
2045         } leftovers_specs[] = {
2046                 [LEFTOVERS_MC] = {
2047                         .flow_attr = {
2048                                 .num_of_specs = 1,
2049                                 .size = sizeof(leftovers_specs[0])
2050                         },
2051                         .eth_flow = {
2052                                 .type = IB_FLOW_SPEC_ETH,
2053                                 .size = sizeof(struct ib_flow_spec_eth),
2054                                 .mask = {.dst_mac = {0x1} },
2055                                 .val =  {.dst_mac = {0x1} }
2056                         }
2057                 },
2058                 [LEFTOVERS_UC] = {
2059                         .flow_attr = {
2060                                 .num_of_specs = 1,
2061                                 .size = sizeof(leftovers_specs[0])
2062                         },
2063                         .eth_flow = {
2064                                 .type = IB_FLOW_SPEC_ETH,
2065                                 .size = sizeof(struct ib_flow_spec_eth),
2066                                 .mask = {.dst_mac = {0x1} },
2067                                 .val = {.dst_mac = {} }
2068                         }
2069                 }
2070         };
2071
2072         handler = create_flow_rule(dev, ft_prio,
2073                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2074                                    dst);
2075         if (!IS_ERR(handler) &&
2076             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2077                 handler_ucast = create_flow_rule(dev, ft_prio,
2078                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2079                                                  dst);
2080                 if (IS_ERR(handler_ucast)) {
2081                         mlx5_del_flow_rules(handler->rule);
2082                         ft_prio->refcount--;
2083                         kfree(handler);
2084                         handler = handler_ucast;
2085                 } else {
2086                         list_add(&handler_ucast->list, &handler->list);
2087                 }
2088         }
2089
2090         return handler;
2091 }
2092
2093 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2094                                                         struct mlx5_ib_flow_prio *ft_rx,
2095                                                         struct mlx5_ib_flow_prio *ft_tx,
2096                                                         struct mlx5_flow_destination *dst)
2097 {
2098         struct mlx5_ib_flow_handler *handler_rx;
2099         struct mlx5_ib_flow_handler *handler_tx;
2100         int err;
2101         static const struct ib_flow_attr flow_attr  = {
2102                 .num_of_specs = 0,
2103                 .size = sizeof(flow_attr)
2104         };
2105
2106         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2107         if (IS_ERR(handler_rx)) {
2108                 err = PTR_ERR(handler_rx);
2109                 goto err;
2110         }
2111
2112         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2113         if (IS_ERR(handler_tx)) {
2114                 err = PTR_ERR(handler_tx);
2115                 goto err_tx;
2116         }
2117
2118         list_add(&handler_tx->list, &handler_rx->list);
2119
2120         return handler_rx;
2121
2122 err_tx:
2123         mlx5_del_flow_rules(handler_rx->rule);
2124         ft_rx->refcount--;
2125         kfree(handler_rx);
2126 err:
2127         return ERR_PTR(err);
2128 }
2129
2130 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2131                                            struct ib_flow_attr *flow_attr,
2132                                            int domain)
2133 {
2134         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2135         struct mlx5_ib_qp *mqp = to_mqp(qp);
2136         struct mlx5_ib_flow_handler *handler = NULL;
2137         struct mlx5_flow_destination *dst = NULL;
2138         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2139         struct mlx5_ib_flow_prio *ft_prio;
2140         int err;
2141
2142         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2143                 return ERR_PTR(-ENOSPC);
2144
2145         if (domain != IB_FLOW_DOMAIN_USER ||
2146             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2147             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2148                 return ERR_PTR(-EINVAL);
2149
2150         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2151         if (!dst)
2152                 return ERR_PTR(-ENOMEM);
2153
2154         mutex_lock(&dev->flow_db.lock);
2155
2156         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2157         if (IS_ERR(ft_prio)) {
2158                 err = PTR_ERR(ft_prio);
2159                 goto unlock;
2160         }
2161         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2162                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2163                 if (IS_ERR(ft_prio_tx)) {
2164                         err = PTR_ERR(ft_prio_tx);
2165                         ft_prio_tx = NULL;
2166                         goto destroy_ft;
2167                 }
2168         }
2169
2170         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2171         if (mqp->flags & MLX5_IB_QP_RSS)
2172                 dst->tir_num = mqp->rss_qp.tirn;
2173         else
2174                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2175
2176         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2177                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2178                         handler = create_dont_trap_rule(dev, ft_prio,
2179                                                         flow_attr, dst);
2180                 } else {
2181                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2182                                                    dst);
2183                 }
2184         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2185                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2186                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2187                                                 dst);
2188         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2189                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2190         } else {
2191                 err = -EINVAL;
2192                 goto destroy_ft;
2193         }
2194
2195         if (IS_ERR(handler)) {
2196                 err = PTR_ERR(handler);
2197                 handler = NULL;
2198                 goto destroy_ft;
2199         }
2200
2201         mutex_unlock(&dev->flow_db.lock);
2202         kfree(dst);
2203
2204         return &handler->ibflow;
2205
2206 destroy_ft:
2207         put_flow_table(dev, ft_prio, false);
2208         if (ft_prio_tx)
2209                 put_flow_table(dev, ft_prio_tx, false);
2210 unlock:
2211         mutex_unlock(&dev->flow_db.lock);
2212         kfree(dst);
2213         kfree(handler);
2214         return ERR_PTR(err);
2215 }
2216
2217 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2218 {
2219         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2220         int err;
2221
2222         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2223         if (err)
2224                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2225                              ibqp->qp_num, gid->raw);
2226
2227         return err;
2228 }
2229
2230 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2231 {
2232         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2233         int err;
2234
2235         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2236         if (err)
2237                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2238                              ibqp->qp_num, gid->raw);
2239
2240         return err;
2241 }
2242
2243 static int init_node_data(struct mlx5_ib_dev *dev)
2244 {
2245         int err;
2246
2247         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2248         if (err)
2249                 return err;
2250
2251         dev->mdev->rev_id = dev->mdev->pdev->revision;
2252
2253         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2254 }
2255
2256 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2257                              char *buf)
2258 {
2259         struct mlx5_ib_dev *dev =
2260                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2261
2262         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2263 }
2264
2265 static ssize_t show_reg_pages(struct device *device,
2266                               struct device_attribute *attr, char *buf)
2267 {
2268         struct mlx5_ib_dev *dev =
2269                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2270
2271         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2272 }
2273
2274 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2275                         char *buf)
2276 {
2277         struct mlx5_ib_dev *dev =
2278                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2279         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2280 }
2281
2282 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2283                         char *buf)
2284 {
2285         struct mlx5_ib_dev *dev =
2286                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2287         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2288 }
2289
2290 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2291                           char *buf)
2292 {
2293         struct mlx5_ib_dev *dev =
2294                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2295         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2296                        dev->mdev->board_id);
2297 }
2298
2299 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2300 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2301 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2302 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2303 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2304
2305 static struct device_attribute *mlx5_class_attributes[] = {
2306         &dev_attr_hw_rev,
2307         &dev_attr_hca_type,
2308         &dev_attr_board_id,
2309         &dev_attr_fw_pages,
2310         &dev_attr_reg_pages,
2311 };
2312
2313 static void pkey_change_handler(struct work_struct *work)
2314 {
2315         struct mlx5_ib_port_resources *ports =
2316                 container_of(work, struct mlx5_ib_port_resources,
2317                              pkey_change_work);
2318
2319         mutex_lock(&ports->devr->mutex);
2320         mlx5_ib_gsi_pkey_change(ports->gsi);
2321         mutex_unlock(&ports->devr->mutex);
2322 }
2323
2324 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2325 {
2326         struct mlx5_ib_qp *mqp;
2327         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2328         struct mlx5_core_cq *mcq;
2329         struct list_head cq_armed_list;
2330         unsigned long flags_qp;
2331         unsigned long flags_cq;
2332         unsigned long flags;
2333
2334         INIT_LIST_HEAD(&cq_armed_list);
2335
2336         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2337         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2338         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2339                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2340                 if (mqp->sq.tail != mqp->sq.head) {
2341                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2342                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2343                         if (send_mcq->mcq.comp &&
2344                             mqp->ibqp.send_cq->comp_handler) {
2345                                 if (!send_mcq->mcq.reset_notify_added) {
2346                                         send_mcq->mcq.reset_notify_added = 1;
2347                                         list_add_tail(&send_mcq->mcq.reset_notify,
2348                                                       &cq_armed_list);
2349                                 }
2350                         }
2351                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2352                 }
2353                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2354                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2355                 /* no handling is needed for SRQ */
2356                 if (!mqp->ibqp.srq) {
2357                         if (mqp->rq.tail != mqp->rq.head) {
2358                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2359                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2360                                 if (recv_mcq->mcq.comp &&
2361                                     mqp->ibqp.recv_cq->comp_handler) {
2362                                         if (!recv_mcq->mcq.reset_notify_added) {
2363                                                 recv_mcq->mcq.reset_notify_added = 1;
2364                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2365                                                               &cq_armed_list);
2366                                         }
2367                                 }
2368                                 spin_unlock_irqrestore(&recv_mcq->lock,
2369                                                        flags_cq);
2370                         }
2371                 }
2372                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2373         }
2374         /*At that point all inflight post send were put to be executed as of we
2375          * lock/unlock above locks Now need to arm all involved CQs.
2376          */
2377         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2378                 mcq->comp(mcq);
2379         }
2380         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2381 }
2382
2383 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2384                           enum mlx5_dev_event event, unsigned long param)
2385 {
2386         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2387         struct ib_event ibev;
2388         bool fatal = false;
2389         u8 port = 0;
2390
2391         switch (event) {
2392         case MLX5_DEV_EVENT_SYS_ERROR:
2393                 ibev.event = IB_EVENT_DEVICE_FATAL;
2394                 mlx5_ib_handle_internal_error(ibdev);
2395                 fatal = true;
2396                 break;
2397
2398         case MLX5_DEV_EVENT_PORT_UP:
2399         case MLX5_DEV_EVENT_PORT_DOWN:
2400         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2401                 port = (u8)param;
2402
2403                 /* In RoCE, port up/down events are handled in
2404                  * mlx5_netdev_event().
2405                  */
2406                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2407                         IB_LINK_LAYER_ETHERNET)
2408                         return;
2409
2410                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2411                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2412                 break;
2413
2414         case MLX5_DEV_EVENT_LID_CHANGE:
2415                 ibev.event = IB_EVENT_LID_CHANGE;
2416                 port = (u8)param;
2417                 break;
2418
2419         case MLX5_DEV_EVENT_PKEY_CHANGE:
2420                 ibev.event = IB_EVENT_PKEY_CHANGE;
2421                 port = (u8)param;
2422
2423                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2424                 break;
2425
2426         case MLX5_DEV_EVENT_GUID_CHANGE:
2427                 ibev.event = IB_EVENT_GID_CHANGE;
2428                 port = (u8)param;
2429                 break;
2430
2431         case MLX5_DEV_EVENT_CLIENT_REREG:
2432                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2433                 port = (u8)param;
2434                 break;
2435         default:
2436                 return;
2437         }
2438
2439         ibev.device           = &ibdev->ib_dev;
2440         ibev.element.port_num = port;
2441
2442         if (port < 1 || port > ibdev->num_ports) {
2443                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2444                 return;
2445         }
2446
2447         if (ibdev->ib_active)
2448                 ib_dispatch_event(&ibev);
2449
2450         if (fatal)
2451                 ibdev->ib_active = false;
2452 }
2453
2454 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2455 {
2456         int port;
2457
2458         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2459                 mlx5_query_ext_port_caps(dev, port);
2460 }
2461
2462 static int get_port_caps(struct mlx5_ib_dev *dev)
2463 {
2464         struct ib_device_attr *dprops = NULL;
2465         struct ib_port_attr *pprops = NULL;
2466         int err = -ENOMEM;
2467         int port;
2468         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2469
2470         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2471         if (!pprops)
2472                 goto out;
2473
2474         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2475         if (!dprops)
2476                 goto out;
2477
2478         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2479         if (err) {
2480                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2481                 goto out;
2482         }
2483
2484         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2485                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2486                 if (err) {
2487                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2488                                      port, err);
2489                         break;
2490                 }
2491                 dev->mdev->port_caps[port - 1].pkey_table_len =
2492                                                 dprops->max_pkeys;
2493                 dev->mdev->port_caps[port - 1].gid_table_len =
2494                                                 pprops->gid_tbl_len;
2495                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2496                             dprops->max_pkeys, pprops->gid_tbl_len);
2497         }
2498
2499 out:
2500         kfree(pprops);
2501         kfree(dprops);
2502
2503         return err;
2504 }
2505
2506 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2507 {
2508         int err;
2509
2510         err = mlx5_mr_cache_cleanup(dev);
2511         if (err)
2512                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2513
2514         mlx5_ib_destroy_qp(dev->umrc.qp);
2515         ib_free_cq(dev->umrc.cq);
2516         ib_dealloc_pd(dev->umrc.pd);
2517 }
2518
2519 enum {
2520         MAX_UMR_WR = 128,
2521 };
2522
2523 static int create_umr_res(struct mlx5_ib_dev *dev)
2524 {
2525         struct ib_qp_init_attr *init_attr = NULL;
2526         struct ib_qp_attr *attr = NULL;
2527         struct ib_pd *pd;
2528         struct ib_cq *cq;
2529         struct ib_qp *qp;
2530         int ret;
2531
2532         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2533         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2534         if (!attr || !init_attr) {
2535                 ret = -ENOMEM;
2536                 goto error_0;
2537         }
2538
2539         pd = ib_alloc_pd(&dev->ib_dev, 0);
2540         if (IS_ERR(pd)) {
2541                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2542                 ret = PTR_ERR(pd);
2543                 goto error_0;
2544         }
2545
2546         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2547         if (IS_ERR(cq)) {
2548                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2549                 ret = PTR_ERR(cq);
2550                 goto error_2;
2551         }
2552
2553         init_attr->send_cq = cq;
2554         init_attr->recv_cq = cq;
2555         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2556         init_attr->cap.max_send_wr = MAX_UMR_WR;
2557         init_attr->cap.max_send_sge = 1;
2558         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2559         init_attr->port_num = 1;
2560         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2561         if (IS_ERR(qp)) {
2562                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2563                 ret = PTR_ERR(qp);
2564                 goto error_3;
2565         }
2566         qp->device     = &dev->ib_dev;
2567         qp->real_qp    = qp;
2568         qp->uobject    = NULL;
2569         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2570
2571         attr->qp_state = IB_QPS_INIT;
2572         attr->port_num = 1;
2573         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2574                                 IB_QP_PORT, NULL);
2575         if (ret) {
2576                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2577                 goto error_4;
2578         }
2579
2580         memset(attr, 0, sizeof(*attr));
2581         attr->qp_state = IB_QPS_RTR;
2582         attr->path_mtu = IB_MTU_256;
2583
2584         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2585         if (ret) {
2586                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2587                 goto error_4;
2588         }
2589
2590         memset(attr, 0, sizeof(*attr));
2591         attr->qp_state = IB_QPS_RTS;
2592         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2593         if (ret) {
2594                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2595                 goto error_4;
2596         }
2597
2598         dev->umrc.qp = qp;
2599         dev->umrc.cq = cq;
2600         dev->umrc.pd = pd;
2601
2602         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2603         ret = mlx5_mr_cache_init(dev);
2604         if (ret) {
2605                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2606                 goto error_4;
2607         }
2608
2609         kfree(attr);
2610         kfree(init_attr);
2611
2612         return 0;
2613
2614 error_4:
2615         mlx5_ib_destroy_qp(qp);
2616
2617 error_3:
2618         ib_free_cq(cq);
2619
2620 error_2:
2621         ib_dealloc_pd(pd);
2622
2623 error_0:
2624         kfree(attr);
2625         kfree(init_attr);
2626         return ret;
2627 }
2628
2629 static int create_dev_resources(struct mlx5_ib_resources *devr)
2630 {
2631         struct ib_srq_init_attr attr;
2632         struct mlx5_ib_dev *dev;
2633         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2634         int port;
2635         int ret = 0;
2636
2637         dev = container_of(devr, struct mlx5_ib_dev, devr);
2638
2639         mutex_init(&devr->mutex);
2640
2641         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2642         if (IS_ERR(devr->p0)) {
2643                 ret = PTR_ERR(devr->p0);
2644                 goto error0;
2645         }
2646         devr->p0->device  = &dev->ib_dev;
2647         devr->p0->uobject = NULL;
2648         atomic_set(&devr->p0->usecnt, 0);
2649
2650         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2651         if (IS_ERR(devr->c0)) {
2652                 ret = PTR_ERR(devr->c0);
2653                 goto error1;
2654         }
2655         devr->c0->device        = &dev->ib_dev;
2656         devr->c0->uobject       = NULL;
2657         devr->c0->comp_handler  = NULL;
2658         devr->c0->event_handler = NULL;
2659         devr->c0->cq_context    = NULL;
2660         atomic_set(&devr->c0->usecnt, 0);
2661
2662         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2663         if (IS_ERR(devr->x0)) {
2664                 ret = PTR_ERR(devr->x0);
2665                 goto error2;
2666         }
2667         devr->x0->device = &dev->ib_dev;
2668         devr->x0->inode = NULL;
2669         atomic_set(&devr->x0->usecnt, 0);
2670         mutex_init(&devr->x0->tgt_qp_mutex);
2671         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2672
2673         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2674         if (IS_ERR(devr->x1)) {
2675                 ret = PTR_ERR(devr->x1);
2676                 goto error3;
2677         }
2678         devr->x1->device = &dev->ib_dev;
2679         devr->x1->inode = NULL;
2680         atomic_set(&devr->x1->usecnt, 0);
2681         mutex_init(&devr->x1->tgt_qp_mutex);
2682         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2683
2684         memset(&attr, 0, sizeof(attr));
2685         attr.attr.max_sge = 1;
2686         attr.attr.max_wr = 1;
2687         attr.srq_type = IB_SRQT_XRC;
2688         attr.ext.xrc.cq = devr->c0;
2689         attr.ext.xrc.xrcd = devr->x0;
2690
2691         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2692         if (IS_ERR(devr->s0)) {
2693                 ret = PTR_ERR(devr->s0);
2694                 goto error4;
2695         }
2696         devr->s0->device        = &dev->ib_dev;
2697         devr->s0->pd            = devr->p0;
2698         devr->s0->uobject       = NULL;
2699         devr->s0->event_handler = NULL;
2700         devr->s0->srq_context   = NULL;
2701         devr->s0->srq_type      = IB_SRQT_XRC;
2702         devr->s0->ext.xrc.xrcd  = devr->x0;
2703         devr->s0->ext.xrc.cq    = devr->c0;
2704         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2705         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2706         atomic_inc(&devr->p0->usecnt);
2707         atomic_set(&devr->s0->usecnt, 0);
2708
2709         memset(&attr, 0, sizeof(attr));
2710         attr.attr.max_sge = 1;
2711         attr.attr.max_wr = 1;
2712         attr.srq_type = IB_SRQT_BASIC;
2713         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2714         if (IS_ERR(devr->s1)) {
2715                 ret = PTR_ERR(devr->s1);
2716                 goto error5;
2717         }
2718         devr->s1->device        = &dev->ib_dev;
2719         devr->s1->pd            = devr->p0;
2720         devr->s1->uobject       = NULL;
2721         devr->s1->event_handler = NULL;
2722         devr->s1->srq_context   = NULL;
2723         devr->s1->srq_type      = IB_SRQT_BASIC;
2724         devr->s1->ext.xrc.cq    = devr->c0;
2725         atomic_inc(&devr->p0->usecnt);
2726         atomic_set(&devr->s0->usecnt, 0);
2727
2728         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2729                 INIT_WORK(&devr->ports[port].pkey_change_work,
2730                           pkey_change_handler);
2731                 devr->ports[port].devr = devr;
2732         }
2733
2734         return 0;
2735
2736 error5:
2737         mlx5_ib_destroy_srq(devr->s0);
2738 error4:
2739         mlx5_ib_dealloc_xrcd(devr->x1);
2740 error3:
2741         mlx5_ib_dealloc_xrcd(devr->x0);
2742 error2:
2743         mlx5_ib_destroy_cq(devr->c0);
2744 error1:
2745         mlx5_ib_dealloc_pd(devr->p0);
2746 error0:
2747         return ret;
2748 }
2749
2750 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2751 {
2752         struct mlx5_ib_dev *dev =
2753                 container_of(devr, struct mlx5_ib_dev, devr);
2754         int port;
2755
2756         mlx5_ib_destroy_srq(devr->s1);
2757         mlx5_ib_destroy_srq(devr->s0);
2758         mlx5_ib_dealloc_xrcd(devr->x0);
2759         mlx5_ib_dealloc_xrcd(devr->x1);
2760         mlx5_ib_destroy_cq(devr->c0);
2761         mlx5_ib_dealloc_pd(devr->p0);
2762
2763         /* Make sure no change P_Key work items are still executing */
2764         for (port = 0; port < dev->num_ports; ++port)
2765                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2766 }
2767
2768 static u32 get_core_cap_flags(struct ib_device *ibdev)
2769 {
2770         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2771         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2772         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2773         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2774         u32 ret = 0;
2775
2776         if (ll == IB_LINK_LAYER_INFINIBAND)
2777                 return RDMA_CORE_PORT_IBA_IB;
2778
2779         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2780                 return 0;
2781
2782         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2783                 return 0;
2784
2785         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2786                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2787
2788         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2789                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2790
2791         return ret;
2792 }
2793
2794 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2795                                struct ib_port_immutable *immutable)
2796 {
2797         struct ib_port_attr attr;
2798         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2799         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2800         int err;
2801
2802         err = mlx5_ib_query_port(ibdev, port_num, &attr);
2803         if (err)
2804                 return err;
2805
2806         immutable->pkey_tbl_len = attr.pkey_tbl_len;
2807         immutable->gid_tbl_len = attr.gid_tbl_len;
2808         immutable->core_cap_flags = get_core_cap_flags(ibdev);
2809         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
2810                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2811
2812         return 0;
2813 }
2814
2815 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2816                            size_t str_len)
2817 {
2818         struct mlx5_ib_dev *dev =
2819                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2820         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2821                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2822 }
2823
2824 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2825 {
2826         struct mlx5_core_dev *mdev = dev->mdev;
2827         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2828                                                                  MLX5_FLOW_NAMESPACE_LAG);
2829         struct mlx5_flow_table *ft;
2830         int err;
2831
2832         if (!ns || !mlx5_lag_is_active(mdev))
2833                 return 0;
2834
2835         err = mlx5_cmd_create_vport_lag(mdev);
2836         if (err)
2837                 return err;
2838
2839         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2840         if (IS_ERR(ft)) {
2841                 err = PTR_ERR(ft);
2842                 goto err_destroy_vport_lag;
2843         }
2844
2845         dev->flow_db.lag_demux_ft = ft;
2846         return 0;
2847
2848 err_destroy_vport_lag:
2849         mlx5_cmd_destroy_vport_lag(mdev);
2850         return err;
2851 }
2852
2853 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
2854 {
2855         struct mlx5_core_dev *mdev = dev->mdev;
2856
2857         if (dev->flow_db.lag_demux_ft) {
2858                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2859                 dev->flow_db.lag_demux_ft = NULL;
2860
2861                 mlx5_cmd_destroy_vport_lag(mdev);
2862         }
2863 }
2864
2865 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
2866 {
2867         int err;
2868
2869         dev->roce.nb.notifier_call = mlx5_netdev_event;
2870         err = register_netdevice_notifier(&dev->roce.nb);
2871         if (err) {
2872                 dev->roce.nb.notifier_call = NULL;
2873                 return err;
2874         }
2875
2876         return 0;
2877 }
2878
2879 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
2880 {
2881         if (dev->roce.nb.notifier_call) {
2882                 unregister_netdevice_notifier(&dev->roce.nb);
2883                 dev->roce.nb.notifier_call = NULL;
2884         }
2885 }
2886
2887 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
2888 {
2889         int err;
2890
2891         err = mlx5_add_netdev_notifier(dev);
2892         if (err)
2893                 return err;
2894
2895         if (MLX5_CAP_GEN(dev->mdev, roce)) {
2896                 err = mlx5_nic_vport_enable_roce(dev->mdev);
2897                 if (err)
2898                         goto err_unregister_netdevice_notifier;
2899         }
2900
2901         err = mlx5_eth_lag_init(dev);
2902         if (err)
2903                 goto err_disable_roce;
2904
2905         return 0;
2906
2907 err_disable_roce:
2908         if (MLX5_CAP_GEN(dev->mdev, roce))
2909                 mlx5_nic_vport_disable_roce(dev->mdev);
2910
2911 err_unregister_netdevice_notifier:
2912         mlx5_remove_netdev_notifier(dev);
2913         return err;
2914 }
2915
2916 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
2917 {
2918         mlx5_eth_lag_cleanup(dev);
2919         if (MLX5_CAP_GEN(dev->mdev, roce))
2920                 mlx5_nic_vport_disable_roce(dev->mdev);
2921 }
2922
2923 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2924 {
2925         unsigned int i;
2926
2927         for (i = 0; i < dev->num_ports; i++)
2928                 mlx5_core_dealloc_q_counter(dev->mdev,
2929                                             dev->port[i].q_cnt_id);
2930 }
2931
2932 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2933 {
2934         int i;
2935         int ret;
2936
2937         for (i = 0; i < dev->num_ports; i++) {
2938                 ret = mlx5_core_alloc_q_counter(dev->mdev,
2939                                                 &dev->port[i].q_cnt_id);
2940                 if (ret) {
2941                         mlx5_ib_warn(dev,
2942                                      "couldn't allocate queue counter for port %d, err %d\n",
2943                                      i + 1, ret);
2944                         goto dealloc_counters;
2945                 }
2946         }
2947
2948         return 0;
2949
2950 dealloc_counters:
2951         while (--i >= 0)
2952                 mlx5_core_dealloc_q_counter(dev->mdev,
2953                                             dev->port[i].q_cnt_id);
2954
2955         return ret;
2956 }
2957
2958 static const char * const names[] = {
2959         "rx_write_requests",
2960         "rx_read_requests",
2961         "rx_atomic_requests",
2962         "out_of_buffer",
2963         "out_of_sequence",
2964         "duplicate_request",
2965         "rnr_nak_retry_err",
2966         "packet_seq_err",
2967         "implied_nak_seq_err",
2968         "local_ack_timeout_err",
2969 };
2970
2971 static const size_t stats_offsets[] = {
2972         MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2973         MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2974         MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2975         MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2976         MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2977         MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2978         MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2979         MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2980         MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2981         MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2982 };
2983
2984 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2985                                                     u8 port_num)
2986 {
2987         BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2988
2989         /* We support only per port stats */
2990         if (port_num == 0)
2991                 return NULL;
2992
2993         return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2994                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
2995 }
2996
2997 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2998                                 struct rdma_hw_stats *stats,
2999                                 u8 port, int index)
3000 {
3001         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3002         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3003         void *out;
3004         __be32 val;
3005         int ret;
3006         int i;
3007
3008         if (!port || !stats)
3009                 return -ENOSYS;
3010
3011         out = mlx5_vzalloc(outlen);
3012         if (!out)
3013                 return -ENOMEM;
3014
3015         ret = mlx5_core_query_q_counter(dev->mdev,
3016                                         dev->port[port - 1].q_cnt_id, 0,
3017                                         out, outlen);
3018         if (ret)
3019                 goto free;
3020
3021         for (i = 0; i < ARRAY_SIZE(names); i++) {
3022                 val = *(__be32 *)(out + stats_offsets[i]);
3023                 stats->value[i] = (u64)be32_to_cpu(val);
3024         }
3025 free:
3026         kvfree(out);
3027         return ARRAY_SIZE(names);
3028 }
3029
3030 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3031 {
3032         struct mlx5_ib_dev *dev;
3033         enum rdma_link_layer ll;
3034         int port_type_cap;
3035         const char *name;
3036         int err;
3037         int i;
3038
3039         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3040         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3041
3042         printk_once(KERN_INFO "%s", mlx5_version);
3043
3044         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3045         if (!dev)
3046                 return NULL;
3047
3048         dev->mdev = mdev;
3049
3050         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3051                             GFP_KERNEL);
3052         if (!dev->port)
3053                 goto err_dealloc;
3054
3055         rwlock_init(&dev->roce.netdev_lock);
3056         err = get_port_caps(dev);
3057         if (err)
3058                 goto err_free_port;
3059
3060         if (mlx5_use_mad_ifc(dev))
3061                 get_ext_port_caps(dev);
3062
3063         MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
3064
3065         if (!mlx5_lag_is_active(mdev))
3066                 name = "mlx5_%d";
3067         else
3068                 name = "mlx5_bond_%d";
3069
3070         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3071         dev->ib_dev.owner               = THIS_MODULE;
3072         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3073         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3074         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3075         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3076         dev->ib_dev.num_comp_vectors    =
3077                 dev->mdev->priv.eq_table.num_comp_vectors;
3078         dev->ib_dev.dma_device  = &mdev->pdev->dev;
3079
3080         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
3081         dev->ib_dev.uverbs_cmd_mask     =
3082                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
3083                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
3084                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
3085                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
3086                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
3087                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
3088                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
3089                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
3090                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
3091                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
3092                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3093                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
3094                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
3095                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
3096                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
3097                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
3098                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
3099                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
3100                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
3101                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
3102                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
3103                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
3104                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
3105                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
3106                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3107                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3108         dev->ib_dev.uverbs_ex_cmd_mask =
3109                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3110                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3111                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
3112                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3113
3114         dev->ib_dev.query_device        = mlx5_ib_query_device;
3115         dev->ib_dev.query_port          = mlx5_ib_query_port;
3116         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3117         if (ll == IB_LINK_LAYER_ETHERNET)
3118                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3119         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3120         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3121         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3122         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3123         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3124         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3125         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3126         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3127         dev->ib_dev.mmap                = mlx5_ib_mmap;
3128         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3129         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3130         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3131         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3132         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3133         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3134         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3135         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3136         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3137         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3138         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3139         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3140         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3141         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3142         dev->ib_dev.post_send           = mlx5_ib_post_send;
3143         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3144         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3145         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3146         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3147         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3148         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3149         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3150         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3151         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3152         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3153         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3154         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3155         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3156         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3157         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3158         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3159         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3160         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3161         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3162         if (mlx5_core_is_pf(mdev)) {
3163                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3164                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3165                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3166                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3167         }
3168
3169         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3170
3171         mlx5_ib_internal_fill_odp_caps(dev);
3172
3173         if (MLX5_CAP_GEN(mdev, imaicl)) {
3174                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3175                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3176                 dev->ib_dev.uverbs_cmd_mask |=
3177                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3178                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3179         }
3180
3181         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3182             MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3183                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3184                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3185         }
3186
3187         if (MLX5_CAP_GEN(mdev, xrc)) {
3188                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3189                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3190                 dev->ib_dev.uverbs_cmd_mask |=
3191                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3192                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3193         }
3194
3195         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3196             IB_LINK_LAYER_ETHERNET) {
3197                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3198                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3199                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3200                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3201                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3202                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3203                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3204                 dev->ib_dev.uverbs_ex_cmd_mask |=
3205                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3206                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3207                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3208                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3209                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3210                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3211                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3212         }
3213         err = init_node_data(dev);
3214         if (err)
3215                 goto err_free_port;
3216
3217         mutex_init(&dev->flow_db.lock);
3218         mutex_init(&dev->cap_mask_mutex);
3219         INIT_LIST_HEAD(&dev->qp_list);
3220         spin_lock_init(&dev->reset_flow_resource_lock);
3221
3222         if (ll == IB_LINK_LAYER_ETHERNET) {
3223                 err = mlx5_enable_eth(dev);
3224                 if (err)
3225                         goto err_free_port;
3226         }
3227
3228         err = create_dev_resources(&dev->devr);
3229         if (err)
3230                 goto err_disable_eth;
3231
3232         err = mlx5_ib_odp_init_one(dev);
3233         if (err)
3234                 goto err_rsrc;
3235
3236         err = mlx5_ib_alloc_q_counters(dev);
3237         if (err)
3238                 goto err_odp;
3239
3240         err = ib_register_device(&dev->ib_dev, NULL);
3241         if (err)
3242                 goto err_q_cnt;
3243
3244         err = create_umr_res(dev);
3245         if (err)
3246                 goto err_dev;
3247
3248         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3249                 err = device_create_file(&dev->ib_dev.dev,
3250                                          mlx5_class_attributes[i]);
3251                 if (err)
3252                         goto err_umrc;
3253         }
3254
3255         dev->ib_active = true;
3256
3257         return dev;
3258
3259 err_umrc:
3260         destroy_umrc_res(dev);
3261
3262 err_dev:
3263         ib_unregister_device(&dev->ib_dev);
3264
3265 err_q_cnt:
3266         mlx5_ib_dealloc_q_counters(dev);
3267
3268 err_odp:
3269         mlx5_ib_odp_remove_one(dev);
3270
3271 err_rsrc:
3272         destroy_dev_resources(&dev->devr);
3273
3274 err_disable_eth:
3275         if (ll == IB_LINK_LAYER_ETHERNET) {
3276                 mlx5_disable_eth(dev);
3277                 mlx5_remove_netdev_notifier(dev);
3278         }
3279
3280 err_free_port:
3281         kfree(dev->port);
3282
3283 err_dealloc:
3284         ib_dealloc_device((struct ib_device *)dev);
3285
3286         return NULL;
3287 }
3288
3289 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3290 {
3291         struct mlx5_ib_dev *dev = context;
3292         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3293
3294         mlx5_remove_netdev_notifier(dev);
3295         ib_unregister_device(&dev->ib_dev);
3296         mlx5_ib_dealloc_q_counters(dev);
3297         destroy_umrc_res(dev);
3298         mlx5_ib_odp_remove_one(dev);
3299         destroy_dev_resources(&dev->devr);
3300         if (ll == IB_LINK_LAYER_ETHERNET)
3301                 mlx5_disable_eth(dev);
3302         kfree(dev->port);
3303         ib_dealloc_device(&dev->ib_dev);
3304 }
3305
3306 static struct mlx5_interface mlx5_ib_interface = {
3307         .add            = mlx5_ib_add,
3308         .remove         = mlx5_ib_remove,
3309         .event          = mlx5_ib_event,
3310         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3311 };
3312
3313 static int __init mlx5_ib_init(void)
3314 {
3315         int err;
3316
3317         if (deprecated_prof_sel != 2)
3318                 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3319
3320         err = mlx5_ib_odp_init();
3321         if (err)
3322                 return err;
3323
3324         err = mlx5_register_interface(&mlx5_ib_interface);
3325         if (err)
3326                 goto clean_odp;
3327
3328         return err;
3329
3330 clean_odp:
3331         mlx5_ib_odp_cleanup();
3332         return err;
3333 }
3334
3335 static void __exit mlx5_ib_cleanup(void)
3336 {
3337         mlx5_unregister_interface(&mlx5_ib_interface);
3338         mlx5_ib_odp_cleanup();
3339 }
3340
3341 module_init(mlx5_ib_init);
3342 module_exit(mlx5_ib_cleanup);