drivers/infiniband/hw/ocrdma/ocrdma_sli.h

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) adapters.                   *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #ifndef __OCRDMA_SLI_H__
  29 #define __OCRDMA_SLI_H__
  30
  31 #define Bit(_b) (1 << (_b))
  32
  33 #define OCRDMA_GEN1_FAMILY      0xB
  34 #define OCRDMA_GEN2_FAMILY      0x2
  35
  36 #define OCRDMA_SUBSYS_ROCE 10
  37 enum {
  38         OCRDMA_CMD_QUERY_CONFIG = 1,
  39         OCRDMA_CMD_ALLOC_PD,
  40         OCRDMA_CMD_DEALLOC_PD,
  41
  42         OCRDMA_CMD_CREATE_AH_TBL,
  43         OCRDMA_CMD_DELETE_AH_TBL,
  44
  45         OCRDMA_CMD_CREATE_QP,
  46         OCRDMA_CMD_QUERY_QP,
  47         OCRDMA_CMD_MODIFY_QP,
  48         OCRDMA_CMD_DELETE_QP,
  49
  50         OCRDMA_CMD_RSVD1,
  51         OCRDMA_CMD_ALLOC_LKEY,
  52         OCRDMA_CMD_DEALLOC_LKEY,
  53         OCRDMA_CMD_REGISTER_NSMR,
  54         OCRDMA_CMD_REREGISTER_NSMR,
  55         OCRDMA_CMD_REGISTER_NSMR_CONT,
  56         OCRDMA_CMD_QUERY_NSMR,
  57         OCRDMA_CMD_ALLOC_MW,
  58         OCRDMA_CMD_QUERY_MW,
  59
  60         OCRDMA_CMD_CREATE_SRQ,
  61         OCRDMA_CMD_QUERY_SRQ,
  62         OCRDMA_CMD_MODIFY_SRQ,
  63         OCRDMA_CMD_DELETE_SRQ,
  64
  65         OCRDMA_CMD_ATTACH_MCAST,
  66         OCRDMA_CMD_DETACH_MCAST,
  67
  68         OCRDMA_CMD_MAX
  69 };
  70
  71 #define OCRDMA_SUBSYS_COMMON 1
  72 enum {
  73         OCRDMA_CMD_CREATE_CQ            = 12,
  74         OCRDMA_CMD_CREATE_EQ            = 13,
  75         OCRDMA_CMD_CREATE_MQ            = 21,
  76         OCRDMA_CMD_GET_FW_VER           = 35,
  77         OCRDMA_CMD_DELETE_MQ            = 53,
  78         OCRDMA_CMD_DELETE_CQ            = 54,
  79         OCRDMA_CMD_DELETE_EQ            = 55,
  80         OCRDMA_CMD_GET_FW_CONFIG        = 58,
  81         OCRDMA_CMD_CREATE_MQ_EXT        = 90
  82 };
  83
  84 enum {
  85         QTYPE_EQ        = 1,
  86         QTYPE_CQ        = 2,
  87         QTYPE_MCCQ      = 3
  88 };
  89
  90 #define OCRDMA_MAX_SGID (8)
  91
  92 #define OCRDMA_MAX_QP    2048
  93 #define OCRDMA_MAX_CQ    2048
  94
  95 enum {
  96         OCRDMA_DB_RQ_OFFSET             = 0xE0,
  97         OCRDMA_DB_GEN2_RQ1_OFFSET       = 0x100,
  98         OCRDMA_DB_GEN2_RQ2_OFFSET       = 0xC0,
  99         OCRDMA_DB_SQ_OFFSET             = 0x60,
 100         OCRDMA_DB_GEN2_SQ_OFFSET        = 0x1C0,
 101         OCRDMA_DB_SRQ_OFFSET            = OCRDMA_DB_RQ_OFFSET,
 102         OCRDMA_DB_GEN2_SRQ_OFFSET       = OCRDMA_DB_GEN2_RQ1_OFFSET,
 103         OCRDMA_DB_CQ_OFFSET             = 0x120,
 104         OCRDMA_DB_EQ_OFFSET             = OCRDMA_DB_CQ_OFFSET,
 105         OCRDMA_DB_MQ_OFFSET             = 0x140
 106 };
 107
 108 #define OCRDMA_DB_CQ_RING_ID_MASK       0x3FF   /* bits 0 - 9 */
 109 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK  0x0C00   /* bits 10-11 of qid at 12-11 */
 110 /* qid #2 msbits at 12-11 */
 111 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT  0x1
 112 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT       (16)        /* bits 16 - 28 */
 113 /* Rearm bit */
 114 #define OCRDMA_DB_CQ_REARM_SHIFT        (29)    /* bit 29 */
 115 /* solicited bit */
 116 #define OCRDMA_DB_CQ_SOLICIT_SHIFT   (31)       /* bit 31 */
 117
 118 #define OCRDMA_EQ_ID_MASK               0x1FF   /* bits 0 - 8 */
 119 #define OCRDMA_EQ_ID_EXT_MASK           0x3e00  /* bits 9-13 */
 120 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT     (2)     /* qid bits 9-13 at 11-15 */
 121
 122 /* Clear the interrupt for this eq */
 123 #define OCRDMA_EQ_CLR_SHIFT                     (9)     /* bit 9 */
 124 /* Must be 1 */
 125 #define OCRDMA_EQ_TYPE_SHIFT            (10)    /* bit 10 */
 126 /* Number of event entries processed */
 127 #define OCRDMA_NUM_EQE_SHIFT            (16)    /* bits 16 - 28 */
 128 /* Rearm bit */
 129 #define OCRDMA_REARM_SHIFT              (29)    /* bit 29 */
 130
 131 #define OCRDMA_MQ_ID_MASK               0x7FF   /* bits 0 - 10 */
 132 /* Number of entries posted */
 133 #define OCRDMA_MQ_NUM_MQE_SHIFT (16)    /* bits 16 - 29 */
 134
 135 #define OCRDMA_MIN_HPAGE_SIZE (4096)
 136
 137 #define OCRDMA_MIN_Q_PAGE_SIZE (4096)
 138 #define OCRDMA_MAX_Q_PAGES     (8)
 139
 140 /*
 141 # 0: 4K Bytes
 142 # 1: 8K Bytes
 143 # 2: 16K Bytes
 144 # 3: 32K Bytes
 145 # 4: 64K Bytes
 146 */
 147 #define OCRDMA_MAX_Q_PAGE_SIZE_CNT (5)
 148 #define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)
 149
 150 #define MAX_OCRDMA_QP_PAGES      (8)
 151 #define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)
 152
 153 #define OCRDMA_CREATE_CQ_MAX_PAGES (4)
 154 #define OCRDMA_DPP_CQE_SIZE (4)
 155
 156 #define OCRDMA_GEN2_MAX_CQE 1024
 157 #define OCRDMA_GEN2_CQ_PAGE_SIZE 4096
 158 #define OCRDMA_GEN2_WQE_SIZE 256
 159 #define OCRDMA_MAX_CQE  4095
 160 #define OCRDMA_CQ_PAGE_SIZE 16384
 161 #define OCRDMA_WQE_SIZE 128
 162 #define OCRDMA_WQE_STRIDE 8
 163 #define OCRDMA_WQE_ALIGN_BYTES 16
 164
 165 #define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES
 166
 167 enum {
 168         OCRDMA_MCH_OPCODE_SHIFT = 0,
 169         OCRDMA_MCH_OPCODE_MASK  = 0xFF,
 170         OCRDMA_MCH_SUBSYS_SHIFT = 8,
 171         OCRDMA_MCH_SUBSYS_MASK  = 0xFF00
 172 };
 173
 174 /* mailbox cmd header */
 175 struct ocrdma_mbx_hdr {
 176         u32 subsys_op;
 177         u32 timeout;            /* in seconds */
 178         u32 cmd_len;
 179         u32 rsvd_version;
 180 } __packed;
 181
 182 enum {
 183         OCRDMA_MBX_RSP_OPCODE_SHIFT     = 0,
 184         OCRDMA_MBX_RSP_OPCODE_MASK      = 0xFF,
 185         OCRDMA_MBX_RSP_SUBSYS_SHIFT     = 8,
 186         OCRDMA_MBX_RSP_SUBSYS_MASK      = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,
 187
 188         OCRDMA_MBX_RSP_STATUS_SHIFT     = 0,
 189         OCRDMA_MBX_RSP_STATUS_MASK      = 0xFF,
 190         OCRDMA_MBX_RSP_ASTATUS_SHIFT    = 8,
 191         OCRDMA_MBX_RSP_ASTATUS_MASK     = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT
 192 };
 193
 194 /* mailbox cmd response */
 195 struct ocrdma_mbx_rsp {
 196         u32 subsys_op;
 197         u32 status;
 198         u32 rsp_len;
 199         u32 add_rsp_len;
 200 } __packed;
 201
 202 enum {
 203         OCRDMA_MQE_EMBEDDED     = 1,
 204         OCRDMA_MQE_NONEMBEDDED  = 0
 205 };
 206
 207 struct ocrdma_mqe_sge {
 208         u32 pa_lo;
 209         u32 pa_hi;
 210         u32 len;
 211 } __packed;
 212
 213 enum {
 214         OCRDMA_MQE_HDR_EMB_SHIFT        = 0,
 215         OCRDMA_MQE_HDR_EMB_MASK         = Bit(0),
 216         OCRDMA_MQE_HDR_SGE_CNT_SHIFT    = 3,
 217         OCRDMA_MQE_HDR_SGE_CNT_MASK     = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,
 218         OCRDMA_MQE_HDR_SPECIAL_SHIFT    = 24,
 219         OCRDMA_MQE_HDR_SPECIAL_MASK     = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT
 220 };
 221
 222 struct ocrdma_mqe_hdr {
 223         u32 spcl_sge_cnt_emb;
 224         u32 pyld_len;
 225         u32 tag_lo;
 226         u32 tag_hi;
 227         u32 rsvd3;
 228 } __packed;
 229
 230 struct ocrdma_mqe_emb_cmd {
 231         struct ocrdma_mbx_hdr mch;
 232         u8 pyld[220];
 233 } __packed;
 234
 235 struct ocrdma_mqe {
 236         struct ocrdma_mqe_hdr hdr;
 237         union {
 238                 struct ocrdma_mqe_emb_cmd emb_req;
 239                 struct {
 240                         struct ocrdma_mqe_sge sge[19];
 241                 } nonemb_req;
 242                 u8 cmd[236];
 243                 struct ocrdma_mbx_rsp rsp;
 244         } u;
 245 } __packed;
 246
 247 #define OCRDMA_EQ_LEN       4096
 248 #define OCRDMA_MQ_CQ_LEN    256
 249 #define OCRDMA_MQ_LEN       128
 250
 251 #define PAGE_SHIFT_4K           12
 252 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 253
 254 /* Returns number of pages spanned by the data starting at the given addr */
 255 #define PAGES_4K_SPANNED(_address, size) \
 256         ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 257                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 258
 259 struct ocrdma_delete_q_req {
 260         struct ocrdma_mbx_hdr req;
 261         u32 id;
 262 } __packed;
 263
 264 struct ocrdma_pa {
 265         u32 lo;
 266         u32 hi;
 267 } __packed;
 268
 269 #define MAX_OCRDMA_EQ_PAGES (8)
 270 struct ocrdma_create_eq_req {
 271         struct ocrdma_mbx_hdr req;
 272         u32 num_pages;
 273         u32 valid;
 274         u32 cnt;
 275         u32 delay;
 276         u32 rsvd;
 277         struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];
 278 } __packed;
 279
 280 enum {
 281         OCRDMA_CREATE_EQ_VALID  = Bit(29),
 282         OCRDMA_CREATE_EQ_CNT_SHIFT      = 26,
 283         OCRDMA_CREATE_CQ_DELAY_SHIFT    = 13,
 284 };
 285
 286 struct ocrdma_create_eq_rsp {
 287         struct ocrdma_mbx_rsp rsp;
 288         u32 vector_eqid;
 289 };
 290
 291 #define OCRDMA_EQ_MINOR_OTHER (0x1)
 292
 293 enum {
 294         OCRDMA_MCQE_STATUS_SHIFT        = 0,
 295         OCRDMA_MCQE_STATUS_MASK         = 0xFFFF,
 296         OCRDMA_MCQE_ESTATUS_SHIFT       = 16,
 297         OCRDMA_MCQE_ESTATUS_MASK        = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,
 298         OCRDMA_MCQE_CONS_SHIFT          = 27,
 299         OCRDMA_MCQE_CONS_MASK           = Bit(27),
 300         OCRDMA_MCQE_CMPL_SHIFT          = 28,
 301         OCRDMA_MCQE_CMPL_MASK           = Bit(28),
 302         OCRDMA_MCQE_AE_SHIFT            = 30,
 303         OCRDMA_MCQE_AE_MASK             = Bit(30),
 304         OCRDMA_MCQE_VALID_SHIFT         = 31,
 305         OCRDMA_MCQE_VALID_MASK          = Bit(31)
 306 };
 307
 308 struct ocrdma_mcqe {
 309         u32 status;
 310         u32 tag_lo;
 311         u32 tag_hi;
 312         u32 valid_ae_cmpl_cons;
 313 } __packed;
 314
 315 enum {
 316         OCRDMA_AE_MCQE_QPVALID          = Bit(31),
 317         OCRDMA_AE_MCQE_QPID_MASK        = 0xFFFF,
 318
 319         OCRDMA_AE_MCQE_CQVALID          = Bit(31),
 320         OCRDMA_AE_MCQE_CQID_MASK        = 0xFFFF,
 321         OCRDMA_AE_MCQE_VALID            = Bit(31),
 322         OCRDMA_AE_MCQE_AE               = Bit(30),
 323         OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
 324         OCRDMA_AE_MCQE_EVENT_TYPE_MASK  =
 325                                         0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,
 326         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,
 327         OCRDMA_AE_MCQE_EVENT_CODE_MASK  =
 328                                         0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
 329 };
 330 struct ocrdma_ae_mcqe {
 331         u32 qpvalid_qpid;
 332         u32 cqvalid_cqid;
 333         u32 evt_tag;
 334         u32 valid_ae_event;
 335 } __packed;
 336
 337 enum {
 338         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT         = 16,
 339         OCRDMA_AE_MPA_MCQE_REQ_ID_MASK          = 0xFFFF <<
 340                                         OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,
 341
 342         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT     = 8,
 343         OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK      = 0xFF <<
 344                                         OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,
 345         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT     = 16,
 346         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK      = 0xFF <<
 347                                         OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,
 348         OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT       = 30,
 349         OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK        = Bit(30),
 350         OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT    = 31,
 351         OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK     = Bit(31)
 352 };
 353
 354 struct ocrdma_ae_mpa_mcqe {
 355         u32 req_id;
 356         u32 w1;
 357         u32 w2;
 358         u32 valid_ae_event;
 359 } __packed;
 360
 361 enum {
 362         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT    = 0,
 363         OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK     = 0xFFFF,
 364         OCRDMA_AE_QP_MCQE_QP_ID_SHIFT           = 16,
 365         OCRDMA_AE_QP_MCQE_QP_ID_MASK            = 0xFFFF <<
 366                                                 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,
 367
 368         OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT      = 8,
 369         OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK       = 0xFF <<
 370                                 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,
 371         OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT      = 16,
 372         OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK       = 0xFF <<
 373                                 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,
 374         OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT        = 30,
 375         OCRDMA_AE_QP_MCQE_EVENT_AE_MASK         = Bit(30),
 376         OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT     = 31,
 377         OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK      = Bit(31)
 378 };
 379
 380 struct ocrdma_ae_qp_mcqe {
 381         u32 qp_id_state;
 382         u32 w1;
 383         u32 w2;
 384         u32 valid_ae_event;
 385 } __packed;
 386
 387 #define OCRDMA_ASYNC_EVE_CODE 0x14
 388
 389 enum OCRDMA_ASYNC_EVENT_TYPE {
 390         OCRDMA_CQ_ERROR                 = 0x00,
 391         OCRDMA_CQ_OVERRUN_ERROR         = 0x01,
 392         OCRDMA_CQ_QPCAT_ERROR           = 0x02,
 393         OCRDMA_QP_ACCESS_ERROR          = 0x03,
 394         OCRDMA_QP_COMM_EST_EVENT        = 0x04,
 395         OCRDMA_SQ_DRAINED_EVENT         = 0x05,
 396         OCRDMA_DEVICE_FATAL_EVENT       = 0x08,
 397         OCRDMA_SRQCAT_ERROR             = 0x0E,
 398         OCRDMA_SRQ_LIMIT_EVENT          = 0x0F,
 399         OCRDMA_QP_LAST_WQE_EVENT        = 0x10
 400 };
 401
 402 /* mailbox command request and responses */
 403 enum {
 404         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT          = 2,
 405         OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK           = Bit(2),
 406         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT        = 3,
 407         OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK         = Bit(3),
 408         OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT               = 8,
 409         OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK                = 0xFFFFFF <<
 410                                 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,
 411
 412         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT               = 16,
 413         OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK                = 0xFFFF <<
 414                                         OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,
 415         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT         = 8,
 416         OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK          = 0xFF <<
 417                                 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,
 418
 419         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT         = 0,
 420         OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK          = 0xFFFF,
 421         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT        = 16,
 422         OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_MASK         = 0xFFFF <<
 423                                 OCRDMA_MBX_QUERY_CFG_MAX_WRITE_SGE_SHIFT,
 424
 425         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT       = 0,
 426         OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK        = 0xFFFF,
 427         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT       = 16,
 428         OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK        = 0xFFFF <<
 429                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,
 430
 431         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET        = 24,
 432         OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK          = 0xFF <<
 433                                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,
 434         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET        = 16,
 435         OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK          = 0xFF <<
 436                                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,
 437         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET        = 0,
 438         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK          = 0xFFFF <<
 439                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,
 440
 441         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET             = 16,
 442         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK               = 0xFFFF <<
 443                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,
 444         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET        = 0,
 445         OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK          = 0xFFFF <<
 446                                 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,
 447
 448         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET         = 16,
 449         OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK           = 0xFFFF <<
 450                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,
 451         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET     = 0,
 452         OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK       = 0xFFFF <<
 453                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,
 454
 455         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET         = 0,
 456         OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK           = 0xFFFF <<
 457                                 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,
 458
 459         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET     = 16,
 460         OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK       = 0xFFFF <<
 461                                 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,
 462         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET     = 0,
 463         OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK       = 0xFFFF <<
 464                                 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,
 465
 466         OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET              = 16,
 467         OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK                = 0xFFFF <<
 468                                 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,
 469         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET     = 0,
 470         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK       = 0xFFFF <<
 471                                 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,
 472
 473         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET         = 16,
 474         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK           = 0xFFFF <<
 475                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,
 476         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET         = 0,
 477         OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK           = 0xFFFF <<
 478                                 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,
 479 };
 480
 481 struct ocrdma_mbx_query_config {
 482         struct ocrdma_mqe_hdr hdr;
 483         struct ocrdma_mbx_rsp rsp;
 484         u32 qp_srq_cq_ird_ord;
 485         u32 max_pd_ca_ack_delay;
 486         u32 max_write_send_sge;
 487         u32 max_ird_ord_per_qp;
 488         u32 max_shared_ird_ord;
 489         u32 max_mr;
 490         u64 max_mr_size;
 491         u32 max_num_mr_pbl;
 492         u32 max_mw;
 493         u32 max_fmr;
 494         u32 max_pages_per_frmr;
 495         u32 max_mcast_group;
 496         u32 max_mcast_qp_attach;
 497         u32 max_total_mcast_qp_attach;
 498         u32 wqe_rqe_stride_max_dpp_cqs;
 499         u32 max_srq_rpir_qps;
 500         u32 max_dpp_pds_credits;
 501         u32 max_dpp_credits_pds_per_pd;
 502         u32 max_wqes_rqes_per_q;
 503         u32 max_cq_cqes_per_cq;
 504         u32 max_srq_rqe_sge;
 505 } __packed;
 506
 507 struct ocrdma_fw_ver_rsp {
 508         struct ocrdma_mqe_hdr hdr;
 509         struct ocrdma_mbx_rsp rsp;
 510
 511         u8 running_ver[32];
 512 } __packed;
 513
 514 struct ocrdma_fw_conf_rsp {
 515         struct ocrdma_mqe_hdr hdr;
 516         struct ocrdma_mbx_rsp rsp;
 517
 518         u32 config_num;
 519         u32 asic_revision;
 520         u32 phy_port;
 521         u32 fn_mode;
 522         struct {
 523                 u32 mode;
 524                 u32 nic_wqid_base;
 525                 u32 nic_wq_tot;
 526                 u32 prot_wqid_base;
 527                 u32 prot_wq_tot;
 528                 u32 prot_rqid_base;
 529                 u32 prot_rqid_tot;
 530                 u32 rsvd[6];
 531         } ulp[2];
 532         u32 fn_capabilities;
 533         u32 rsvd1;
 534         u32 rsvd2;
 535         u32 base_eqid;
 536         u32 max_eq;
 537
 538 } __packed;
 539
 540 enum {
 541         OCRDMA_FN_MODE_RDMA     = 0x4
 542 };
 543
 544 enum {
 545         OCRDMA_CREATE_CQ_VER2                   = 2,
 546
 547         OCRDMA_CREATE_CQ_PAGE_CNT_MASK          = 0xFFFF,
 548         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT        = 16,
 549         OCRDMA_CREATE_CQ_PAGE_SIZE_MASK         = 0xFF,
 550
 551         OCRDMA_CREATE_CQ_COALESCWM_SHIFT        = 12,
 552         OCRDMA_CREATE_CQ_COALESCWM_MASK         = Bit(13) | Bit(12),
 553         OCRDMA_CREATE_CQ_FLAGS_NODELAY          = Bit(14),
 554         OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID       = Bit(15),
 555
 556         OCRDMA_CREATE_CQ_EQ_ID_MASK             = 0xFFFF,
 557         OCRDMA_CREATE_CQ_CQE_COUNT_MASK         = 0xFFFF
 558 };
 559
 560 enum {
 561         OCRDMA_CREATE_CQ_VER0                   = 0,
 562         OCRDMA_CREATE_CQ_DPP                    = 1,
 563         OCRDMA_CREATE_CQ_TYPE_SHIFT             = 24,
 564         OCRDMA_CREATE_CQ_EQID_SHIFT             = 22,
 565
 566         OCRDMA_CREATE_CQ_CNT_SHIFT              = 27,
 567         OCRDMA_CREATE_CQ_FLAGS_VALID            = Bit(29),
 568         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE        = Bit(31),
 569         OCRDMA_CREATE_CQ_DEF_FLAGS              = OCRDMA_CREATE_CQ_FLAGS_VALID |
 570                                         OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |
 571                                         OCRDMA_CREATE_CQ_FLAGS_NODELAY
 572 };
 573
 574 struct ocrdma_create_cq_cmd {
 575         struct ocrdma_mbx_hdr req;
 576         u32 pgsz_pgcnt;
 577         u32 ev_cnt_flags;
 578         u32 eqn;
 579         u32 cqe_count;
 580         u32 rsvd6;
 581         struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];
 582 };
 583
 584 struct ocrdma_create_cq {
 585         struct ocrdma_mqe_hdr hdr;
 586         struct ocrdma_create_cq_cmd cmd;
 587 } __packed;
 588
 589 enum {
 590         OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF
 591 };
 592
 593 struct ocrdma_create_cq_cmd_rsp {
 594         struct ocrdma_mbx_rsp rsp;
 595         u32 cq_id;
 596 } __packed;
 597
 598 struct ocrdma_create_cq_rsp {
 599         struct ocrdma_mqe_hdr hdr;
 600         struct ocrdma_create_cq_cmd_rsp rsp;
 601 } __packed;
 602
 603 enum {
 604         OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT         = 22,
 605         OCRDMA_CREATE_MQ_CQ_ID_SHIFT            = 16,
 606         OCRDMA_CREATE_MQ_RING_SIZE_SHIFT        = 16,
 607         OCRDMA_CREATE_MQ_VALID                  = Bit(31),
 608         OCRDMA_CREATE_MQ_ASYNC_CQ_VALID         = Bit(0)
 609 };
 610
 611 struct ocrdma_create_mq_v0 {
 612         u32 pages;
 613         u32 cqid_ringsize;
 614         u32 valid;
 615         u32 async_cqid_valid;
 616         u32 rsvd;
 617         struct ocrdma_pa pa[8];
 618 } __packed;
 619
 620 struct ocrdma_create_mq_v1 {
 621         u32 cqid_pages;
 622         u32 async_event_bitmap;
 623         u32 async_cqid_ringsize;
 624         u32 valid;
 625         u32 async_cqid_valid;
 626         u32 rsvd;
 627         struct ocrdma_pa pa[8];
 628 } __packed;
 629
 630 struct ocrdma_create_mq_req {
 631         struct ocrdma_mbx_hdr req;
 632         union {
 633                 struct ocrdma_create_mq_v0 v0;
 634                 struct ocrdma_create_mq_v1 v1;
 635         };
 636 } __packed;
 637
 638 struct ocrdma_create_mq_rsp {
 639         struct ocrdma_mbx_rsp rsp;
 640         u32 id;
 641 } __packed;
 642
 643 enum {
 644         OCRDMA_DESTROY_CQ_QID_SHIFT                     = 0,
 645         OCRDMA_DESTROY_CQ_QID_MASK                      = 0xFFFF,
 646         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT        = 16,
 647         OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK         = 0xFFFF <<
 648                                 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
 649 };
 650
 651 struct ocrdma_destroy_cq {
 652         struct ocrdma_mqe_hdr hdr;
 653         struct ocrdma_mbx_hdr req;
 654
 655         u32 bypass_flush_qid;
 656 } __packed;
 657
 658 struct ocrdma_destroy_cq_rsp {
 659         struct ocrdma_mqe_hdr hdr;
 660         struct ocrdma_mbx_rsp rsp;
 661 } __packed;
 662
 663 enum {
 664         OCRDMA_QPT_GSI  = 1,
 665         OCRDMA_QPT_RC   = 2,
 666         OCRDMA_QPT_UD   = 4,
 667 };
 668
 669 enum {
 670         OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT        = 0,
 671         OCRDMA_CREATE_QP_REQ_PD_ID_MASK         = 0xFFFF,
 672         OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
 673         OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,
 674         OCRDMA_CREATE_QP_REQ_QPT_SHIFT          = 29,
 675         OCRDMA_CREATE_QP_REQ_QPT_MASK           = Bit(31) | Bit(30) | Bit(29),
 676
 677         OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT      = 0,
 678         OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK       = 0xFFFF,
 679         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT      = 16,
 680         OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK       = 0xFFFF <<
 681                                         OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,
 682
 683         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT        = 0,
 684         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK         = 0xFFFF,
 685         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT         = 16,
 686         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK          = 0xFFFF <<
 687                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,
 688
 689         OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT               = 0,
 690         OCRDMA_CREATE_QP_REQ_FMR_EN_MASK                = Bit(0),
 691         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT          = 1,
 692         OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK           = Bit(1),
 693         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT          = 2,
 694         OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK           = Bit(2),
 695         OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT             = 3,
 696         OCRDMA_CREATE_QP_REQ_INB_WREN_MASK              = Bit(3),
 697         OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT             = 4,
 698         OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK              = Bit(4),
 699         OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT              = 5,
 700         OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK               = Bit(5),
 701         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT          = 6,
 702         OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK           = Bit(6),
 703         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT           = 7,
 704         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK            = Bit(7),
 705         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT        = 8,
 706         OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK         = Bit(8),
 707         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT         = 16,
 708         OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK          = 0xFFFF <<
 709                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,
 710
 711         OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT              = 0,
 712         OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK               = 0xFFFF,
 713         OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT              = 16,
 714         OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK               = 0xFFFF <<
 715                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,
 716
 717         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT         = 0,
 718         OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK          = 0xFFFF,
 719         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT         = 16,
 720         OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK          = 0xFFFF <<
 721                                 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,
 722
 723         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT             = 0,
 724         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK              = 0xFFFF,
 725         OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT             = 16,
 726         OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK              = 0xFFFF <<
 727                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,
 728
 729         OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT              = 0,
 730         OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK               = 0xFFFF,
 731         OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT              = 16,
 732         OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK               = 0xFFFF <<
 733                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,
 734
 735         OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT            = 0,
 736         OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK             = 0xFFFF,
 737         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT           = 16,
 738         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK            = 0xFFFF <<
 739                                 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
 740 };
 741
 742 enum {
 743         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT   = 16,
 744         OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT     = 1
 745 };
 746
 747 #define MAX_OCRDMA_IRD_PAGES 4
 748
 749 enum ocrdma_qp_flags {
 750         OCRDMA_QP_MW_BIND       = 1,
 751         OCRDMA_QP_LKEY0         = (1 << 1),
 752         OCRDMA_QP_FAST_REG      = (1 << 2),
 753         OCRDMA_QP_INB_RD        = (1 << 6),
 754         OCRDMA_QP_INB_WR        = (1 << 7),
 755 };
 756
 757 enum ocrdma_qp_state {
 758         OCRDMA_QPS_RST          = 0,
 759         OCRDMA_QPS_INIT         = 1,
 760         OCRDMA_QPS_RTR          = 2,
 761         OCRDMA_QPS_RTS          = 3,
 762         OCRDMA_QPS_SQE          = 4,
 763         OCRDMA_QPS_SQ_DRAINING  = 5,
 764         OCRDMA_QPS_ERR          = 6,
 765         OCRDMA_QPS_SQD          = 7
 766 };
 767
 768 struct ocrdma_create_qp_req {
 769         struct ocrdma_mqe_hdr hdr;
 770         struct ocrdma_mbx_hdr req;
 771
 772         u32 type_pgsz_pdn;
 773         u32 max_wqe_rqe;
 774         u32 max_sge_send_write;
 775         u32 max_sge_recv_flags;
 776         u32 max_ord_ird;
 777         u32 num_wq_rq_pages;
 778         u32 wqe_rqe_size;
 779         u32 wq_rq_cqid;
 780         struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];
 781         struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];
 782         u32 dpp_credits_cqid;
 783         u32 rpir_lkey;
 784         struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];
 785 } __packed;
 786
 787 enum {
 788         OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT                = 0,
 789         OCRDMA_CREATE_QP_RSP_QP_ID_MASK                 = 0xFFFF,
 790
 791         OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT              = 0,
 792         OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK               = 0xFFFF,
 793         OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT              = 16,
 794         OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK               = 0xFFFF <<
 795                                 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,
 796
 797         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT        = 0,
 798         OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK         = 0xFFFF,
 799         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT         = 16,
 800         OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK          = 0xFFFF <<
 801                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,
 802
 803         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT         = 16,
 804         OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK          = 0xFFFF <<
 805                                 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,
 806
 807         OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT              = 0,
 808         OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK               = 0xFFFF,
 809         OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT              = 16,
 810         OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK               = 0xFFFF <<
 811                                 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,
 812
 813         OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT                = 0,
 814         OCRDMA_CREATE_QP_RSP_RQ_ID_MASK                 = 0xFFFF,
 815         OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT                = 16,
 816         OCRDMA_CREATE_QP_RSP_SQ_ID_MASK                 = 0xFFFF <<
 817                                 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,
 818
 819         OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK           = Bit(0),
 820         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT      = 1,
 821         OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK       = 0x7FFF <<
 822                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,
 823         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT          = 16,
 824         OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK           = 0xFFFF <<
 825                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,
 826 };
 827
 828 struct ocrdma_create_qp_rsp {
 829         struct ocrdma_mqe_hdr hdr;
 830         struct ocrdma_mbx_rsp rsp;
 831
 832         u32 qp_id;
 833         u32 max_wqe_rqe;
 834         u32 max_sge_send_write;
 835         u32 max_sge_recv;
 836         u32 max_ord_ird;
 837         u32 sq_rq_id;
 838         u32 dpp_response;
 839 } __packed;
 840
 841 struct ocrdma_destroy_qp {
 842         struct ocrdma_mqe_hdr hdr;
 843         struct ocrdma_mbx_hdr req;
 844         u32 qp_id;
 845 } __packed;
 846
 847 struct ocrdma_destroy_qp_rsp {
 848         struct ocrdma_mqe_hdr hdr;
 849         struct ocrdma_mbx_rsp rsp;
 850 } __packed;
 851
 852 enum {
 853         OCRDMA_MODIFY_QP_ID_SHIFT       = 0,
 854         OCRDMA_MODIFY_QP_ID_MASK        = 0xFFFF,
 855
 856         OCRDMA_QP_PARA_QPS_VALID        = Bit(0),
 857         OCRDMA_QP_PARA_SQD_ASYNC_VALID  = Bit(1),
 858         OCRDMA_QP_PARA_PKEY_VALID       = Bit(2),
 859         OCRDMA_QP_PARA_QKEY_VALID       = Bit(3),
 860         OCRDMA_QP_PARA_PMTU_VALID       = Bit(4),
 861         OCRDMA_QP_PARA_ACK_TO_VALID     = Bit(5),
 862         OCRDMA_QP_PARA_RETRY_CNT_VALID  = Bit(6),
 863         OCRDMA_QP_PARA_RRC_VALID        = Bit(7),
 864         OCRDMA_QP_PARA_RQPSN_VALID      = Bit(8),
 865         OCRDMA_QP_PARA_MAX_IRD_VALID    = Bit(9),
 866         OCRDMA_QP_PARA_MAX_ORD_VALID    = Bit(10),
 867         OCRDMA_QP_PARA_RNT_VALID        = Bit(11),
 868         OCRDMA_QP_PARA_SQPSN_VALID      = Bit(12),
 869         OCRDMA_QP_PARA_DST_QPN_VALID    = Bit(13),
 870         OCRDMA_QP_PARA_MAX_WQE_VALID    = Bit(14),
 871         OCRDMA_QP_PARA_MAX_RQE_VALID    = Bit(15),
 872         OCRDMA_QP_PARA_SGE_SEND_VALID   = Bit(16),
 873         OCRDMA_QP_PARA_SGE_RECV_VALID   = Bit(17),
 874         OCRDMA_QP_PARA_SGE_WR_VALID     = Bit(18),
 875         OCRDMA_QP_PARA_INB_RDEN_VALID   = Bit(19),
 876         OCRDMA_QP_PARA_INB_WREN_VALID   = Bit(20),
 877         OCRDMA_QP_PARA_FLOW_LBL_VALID   = Bit(21),
 878         OCRDMA_QP_PARA_BIND_EN_VALID    = Bit(22),
 879         OCRDMA_QP_PARA_ZLKEY_EN_VALID   = Bit(23),
 880         OCRDMA_QP_PARA_FMR_EN_VALID     = Bit(24),
 881         OCRDMA_QP_PARA_INBAT_EN_VALID   = Bit(25),
 882         OCRDMA_QP_PARA_VLAN_EN_VALID    = Bit(26),
 883
 884         OCRDMA_MODIFY_QP_FLAGS_RD       = Bit(0),
 885         OCRDMA_MODIFY_QP_FLAGS_WR       = Bit(1),
 886         OCRDMA_MODIFY_QP_FLAGS_SEND     = Bit(2),
 887         OCRDMA_MODIFY_QP_FLAGS_ATOMIC   = Bit(3)
 888 };
 889
 890 enum {
 891         OCRDMA_QP_PARAMS_SRQ_ID_SHIFT           = 0,
 892         OCRDMA_QP_PARAMS_SRQ_ID_MASK            = 0xFFFF,
 893
 894         OCRDMA_QP_PARAMS_MAX_RQE_SHIFT          = 0,
 895         OCRDMA_QP_PARAMS_MAX_RQE_MASK           = 0xFFFF,
 896         OCRDMA_QP_PARAMS_MAX_WQE_SHIFT          = 16,
 897         OCRDMA_QP_PARAMS_MAX_WQE_MASK           = 0xFFFF <<
 898             OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,
 899
 900         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT    = 0,
 901         OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK     = 0xFFFF,
 902         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT     = 16,
 903         OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK      = 0xFFFF <<
 904                                         OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,
 905
 906         OCRDMA_QP_PARAMS_FLAGS_FMR_EN           = Bit(0),
 907         OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN        = Bit(1),
 908         OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN       = Bit(2),
 909         OCRDMA_QP_PARAMS_FLAGS_INBWR_EN         = Bit(3),
 910         OCRDMA_QP_PARAMS_FLAGS_INBRD_EN         = Bit(4),
 911         OCRDMA_QP_PARAMS_STATE_SHIFT            = 5,
 912         OCRDMA_QP_PARAMS_STATE_MASK             = Bit(5) | Bit(6) | Bit(7),
 913         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC        = Bit(8),
 914         OCRDMA_QP_PARAMS_FLAGS_INB_ATEN         = Bit(9),
 915         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT     = 16,
 916         OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK      = 0xFFFF <<
 917                                         OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,
 918
 919         OCRDMA_QP_PARAMS_MAX_IRD_SHIFT          = 0,
 920         OCRDMA_QP_PARAMS_MAX_IRD_MASK           = 0xFFFF,
 921         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT          = 16,
 922         OCRDMA_QP_PARAMS_MAX_ORD_MASK           = 0xFFFF <<
 923                                         OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,
 924
 925         OCRDMA_QP_PARAMS_RQ_CQID_SHIFT          = 0,
 926         OCRDMA_QP_PARAMS_RQ_CQID_MASK           = 0xFFFF,
 927         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT          = 16,
 928         OCRDMA_QP_PARAMS_WQ_CQID_MASK           = 0xFFFF <<
 929                                         OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,
 930
 931         OCRDMA_QP_PARAMS_RQ_PSN_SHIFT           = 0,
 932         OCRDMA_QP_PARAMS_RQ_PSN_MASK            = 0xFFFFFF,
 933         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT          = 24,
 934         OCRDMA_QP_PARAMS_HOP_LMT_MASK           = 0xFF <<
 935                                         OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
 936
 937         OCRDMA_QP_PARAMS_SQ_PSN_SHIFT           = 0,
 938         OCRDMA_QP_PARAMS_SQ_PSN_MASK            = 0xFFFFFF,
 939         OCRDMA_QP_PARAMS_TCLASS_SHIFT           = 24,
 940         OCRDMA_QP_PARAMS_TCLASS_MASK            = 0xFF <<
 941                                         OCRDMA_QP_PARAMS_TCLASS_SHIFT,
 942
 943         OCRDMA_QP_PARAMS_DEST_QPN_SHIFT         = 0,
 944         OCRDMA_QP_PARAMS_DEST_QPN_MASK          = 0xFFFFFF,
 945         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT    = 24,
 946         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK     = 0x7 <<
 947                                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,
 948         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT      = 27,
 949         OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK       = 0x1F <<
 950                                         OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,
 951
 952         OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT       = 0,
 953         OCRDMA_QP_PARAMS_PKEY_INDEX_MASK        = 0xFFFF,
 954         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT         = 18,
 955         OCRDMA_QP_PARAMS_PATH_MTU_MASK          = 0x3FFF <<
 956                                         OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,
 957
 958         OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT       = 0,
 959         OCRDMA_QP_PARAMS_FLOW_LABEL_MASK        = 0xFFFFF,
 960         OCRDMA_QP_PARAMS_SL_SHIFT               = 20,
 961         OCRDMA_QP_PARAMS_SL_MASK                = 0xF <<
 962                                         OCRDMA_QP_PARAMS_SL_SHIFT,
 963         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT        = 24,
 964         OCRDMA_QP_PARAMS_RETRY_CNT_MASK         = 0x7 <<
 965                                         OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,
 966         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT    = 27,
 967         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK     = 0x1F <<
 968                                         OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,
 969
 970         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT    = 0,
 971         OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK     = 0xFFFF,
 972         OCRDMA_QP_PARAMS_VLAN_SHIFT             = 16,
 973         OCRDMA_QP_PARAMS_VLAN_MASK              = 0xFFFF <<
 974                                         OCRDMA_QP_PARAMS_VLAN_SHIFT
 975 };
 976
 977 struct ocrdma_qp_params {
 978         u32 id;
 979         u32 max_wqe_rqe;
 980         u32 max_sge_send_write;
 981         u32 max_sge_recv_flags;
 982         u32 max_ord_ird;
 983         u32 wq_rq_cqid;
 984         u32 hop_lmt_rq_psn;
 985         u32 tclass_sq_psn;
 986         u32 ack_to_rnr_rtc_dest_qpn;
 987         u32 path_mtu_pkey_indx;
 988         u32 rnt_rc_sl_fl;
 989         u8 sgid[16];
 990         u8 dgid[16];
 991         u32 dmac_b0_to_b3;
 992         u32 vlan_dmac_b4_to_b5;
 993         u32 qkey;
 994 } __packed;
 995
 996
 997 struct ocrdma_modify_qp {
 998         struct ocrdma_mqe_hdr hdr;
 999         struct ocrdma_mbx_hdr req;
1000
1001         struct ocrdma_qp_params params;
1002         u32 flags;
1003         u32 rdma_flags;
1004         u32 num_outstanding_atomic_rd;
1005 } __packed;
1006
1007 enum {
1008         OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT      = 0,
1009         OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK       = 0xFFFF,
1010         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT      = 16,
1011         OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK       = 0xFFFF <<
1012                                         OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,
1013
1014         OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT      = 0,
1015         OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK       = 0xFFFF,
1016         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT      = 16,
1017         OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK       = 0xFFFF <<
1018                                         OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
1019 };
1020 struct ocrdma_modify_qp_rsp {
1021         struct ocrdma_mqe_hdr hdr;
1022         struct ocrdma_mbx_rsp rsp;
1023
1024         u32 max_wqe_rqe;
1025         u32 max_ord_ird;
1026 } __packed;
1027
1028 struct ocrdma_query_qp {
1029         struct ocrdma_mqe_hdr hdr;
1030         struct ocrdma_mbx_hdr req;
1031
1032 #define OCRDMA_QUERY_UP_QP_ID_SHIFT 0
1033 #define OCRDMA_QUERY_UP_QP_ID_MASK   0xFFFFFF
1034         u32 qp_id;
1035 } __packed;
1036
1037 struct ocrdma_query_qp_rsp {
1038         struct ocrdma_mqe_hdr hdr;
1039         struct ocrdma_mbx_rsp rsp;
1040         struct ocrdma_qp_params params;
1041 } __packed;
1042
1043 enum {
1044         OCRDMA_CREATE_SRQ_PD_ID_SHIFT           = 0,
1045         OCRDMA_CREATE_SRQ_PD_ID_MASK            = 0xFFFF,
1046         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT           = 16,
1047         OCRDMA_CREATE_SRQ_PG_SZ_MASK            = 0x3 <<
1048                                         OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,
1049
1050         OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT         = 0,
1051         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT    = 16,
1052         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK     = 0xFFFF <<
1053                                         OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,
1054
1055         OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT        = 0,
1056         OCRDMA_CREATE_SRQ_RQE_SIZE_MASK         = 0xFFFF,
1057         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT    = 16,
1058         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK     = 0xFFFF <<
1059                                         OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
1060 };
1061
1062 struct ocrdma_create_srq {
1063         struct ocrdma_mqe_hdr hdr;
1064         struct ocrdma_mbx_hdr req;
1065
1066         u32 pgsz_pdid;
1067         u32 max_sge_rqe;
1068         u32 pages_rqe_sz;
1069         struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];
1070 } __packed;
1071
1072 enum {
1073         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT                      = 0,
1074         OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK                       = 0xFFFFFF,
1075
1076         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT           = 0,
1077         OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK            = 0xFFFF,
1078         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT      = 16,
1079         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK       = 0xFFFF <<
1080                         OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
1081 };
1082
1083 struct ocrdma_create_srq_rsp {
1084         struct ocrdma_mqe_hdr hdr;
1085         struct ocrdma_mbx_rsp rsp;
1086
1087         u32 id;
1088         u32 max_sge_rqe_allocated;
1089 } __packed;
1090
1091 enum {
1092         OCRDMA_MODIFY_SRQ_ID_SHIFT      = 0,
1093         OCRDMA_MODIFY_SRQ_ID_MASK       = 0xFFFFFF,
1094
1095         OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,
1096         OCRDMA_MODIFY_SRQ_MAX_RQE_MASK  = 0xFFFF,
1097         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT   = 16,
1098         OCRDMA_MODIFY_SRQ__LIMIT_MASK   = 0xFFFF <<
1099                                         OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
1100 };
1101
1102 struct ocrdma_modify_srq {
1103         struct ocrdma_mqe_hdr hdr;
1104         struct ocrdma_mbx_rsp rep;
1105
1106         u32 id;
1107         u32 limit_max_rqe;
1108 } __packed;
1109
1110 enum {
1111         OCRDMA_QUERY_SRQ_ID_SHIFT       = 0,
1112         OCRDMA_QUERY_SRQ_ID_MASK        = 0xFFFFFF
1113 };
1114
1115 struct ocrdma_query_srq {
1116         struct ocrdma_mqe_hdr hdr;
1117         struct ocrdma_mbx_rsp req;
1118
1119         u32 id;
1120 } __packed;
1121
1122 enum {
1123         OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT        = 0,
1124         OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK         = 0xFFFF,
1125         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT      = 16,
1126         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK       = 0xFFFF <<
1127                                         OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,
1128
1129         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,
1130         OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK  = 0xFFFF,
1131         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT    = 16,
1132         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK     = 0xFFFF <<
1133                                         OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
1134 };
1135
1136 struct ocrdma_query_srq_rsp {
1137         struct ocrdma_mqe_hdr hdr;
1138         struct ocrdma_mbx_rsp req;
1139
1140         u32 max_rqe_pdid;
1141         u32 srq_lmt_max_sge;
1142 } __packed;
1143
1144 enum {
1145         OCRDMA_DESTROY_SRQ_ID_SHIFT     = 0,
1146         OCRDMA_DESTROY_SRQ_ID_MASK      = 0xFFFFFF
1147 };
1148
1149 struct ocrdma_destroy_srq {
1150         struct ocrdma_mqe_hdr hdr;
1151         struct ocrdma_mbx_rsp req;
1152
1153         u32 id;
1154 } __packed;
1155
1156 enum {
1157         OCRDMA_ALLOC_PD_ENABLE_DPP      = BIT(16),
1158         OCRDMA_PD_MAX_DPP_ENABLED_QP    = 8,
1159         OCRDMA_DPP_PAGE_SIZE            = 4096
1160 };
1161
1162 struct ocrdma_alloc_pd {
1163         struct ocrdma_mqe_hdr hdr;
1164         struct ocrdma_mbx_hdr req;
1165         u32 enable_dpp_rsvd;
1166 } __packed;
1167
1168 enum {
1169         OCRDMA_ALLOC_PD_RSP_DPP                 = Bit(16),
1170         OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT      = 20,
1171         OCRDMA_ALLOC_PD_RSP_PDID_MASK           = 0xFFFF,
1172 };
1173
1174 struct ocrdma_alloc_pd_rsp {
1175         struct ocrdma_mqe_hdr hdr;
1176         struct ocrdma_mbx_rsp rsp;
1177         u32 dpp_page_pdid;
1178 } __packed;
1179
1180 struct ocrdma_dealloc_pd {
1181         struct ocrdma_mqe_hdr hdr;
1182         struct ocrdma_mbx_hdr req;
1183         u32 id;
1184 } __packed;
1185
1186 struct ocrdma_dealloc_pd_rsp {
1187         struct ocrdma_mqe_hdr hdr;
1188         struct ocrdma_mbx_rsp rsp;
1189 } __packed;
1190
1191 enum {
1192         OCRDMA_ADDR_CHECK_ENABLE        = 1,
1193         OCRDMA_ADDR_CHECK_DISABLE       = 0
1194 };
1195
1196 enum {
1197         OCRDMA_ALLOC_LKEY_PD_ID_SHIFT           = 0,
1198         OCRDMA_ALLOC_LKEY_PD_ID_MASK            = 0xFFFF,
1199
1200         OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT      = 0,
1201         OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK       = Bit(0),
1202         OCRDMA_ALLOC_LKEY_FMR_SHIFT             = 1,
1203         OCRDMA_ALLOC_LKEY_FMR_MASK              = Bit(1),
1204         OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT      = 2,
1205         OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK       = Bit(2),
1206         OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT       = 3,
1207         OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK        = Bit(3),
1208         OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT       = 4,
1209         OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK        = Bit(4),
1210         OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT        = 5,
1211         OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK         = Bit(5),
1212         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK    = Bit(6),
1213         OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT   = 6,
1214         OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT        = 16,
1215         OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK         = 0xFFFF <<
1216                                                 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
1217 };
1218
1219 struct ocrdma_alloc_lkey {
1220         struct ocrdma_mqe_hdr hdr;
1221         struct ocrdma_mbx_hdr req;
1222
1223         u32 pdid;
1224         u32 pbl_sz_flags;
1225 } __packed;
1226
1227 struct ocrdma_alloc_lkey_rsp {
1228         struct ocrdma_mqe_hdr hdr;
1229         struct ocrdma_mbx_rsp rsp;
1230
1231         u32 lrkey;
1232         u32 num_pbl_rsvd;
1233 } __packed;
1234
1235 struct ocrdma_dealloc_lkey {
1236         struct ocrdma_mqe_hdr hdr;
1237         struct ocrdma_mbx_hdr req;
1238
1239         u32 lkey;
1240         u32 rsvd_frmr;
1241 } __packed;
1242
1243 struct ocrdma_dealloc_lkey_rsp {
1244         struct ocrdma_mqe_hdr hdr;
1245         struct ocrdma_mbx_rsp rsp;
1246 } __packed;
1247
1248 #define MAX_OCRDMA_NSMR_PBL    (u32)22
1249 #define MAX_OCRDMA_PBL_SIZE     65536
1250 #define MAX_OCRDMA_PBL_PER_LKEY 32767
1251
1252 enum {
1253         OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT       = 0,
1254         OCRDMA_REG_NSMR_LRKEY_INDEX_MASK        = 0xFFFFFF,
1255         OCRDMA_REG_NSMR_LRKEY_SHIFT             = 24,
1256         OCRDMA_REG_NSMR_LRKEY_MASK              = 0xFF <<
1257                                         OCRDMA_REG_NSMR_LRKEY_SHIFT,
1258
1259         OCRDMA_REG_NSMR_PD_ID_SHIFT             = 0,
1260         OCRDMA_REG_NSMR_PD_ID_MASK              = 0xFFFF,
1261         OCRDMA_REG_NSMR_NUM_PBL_SHIFT           = 16,
1262         OCRDMA_REG_NSMR_NUM_PBL_MASK            = 0xFFFF <<
1263                                         OCRDMA_REG_NSMR_NUM_PBL_SHIFT,
1264
1265         OCRDMA_REG_NSMR_PBE_SIZE_SHIFT          = 0,
1266         OCRDMA_REG_NSMR_PBE_SIZE_MASK           = 0xFFFF,
1267         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT        = 16,
1268         OCRDMA_REG_NSMR_HPAGE_SIZE_MASK         = 0xFF <<
1269                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,
1270         OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT       = 24,
1271         OCRDMA_REG_NSMR_BIND_MEMWIN_MASK        = Bit(24),
1272         OCRDMA_REG_NSMR_ZB_SHIFT                = 25,
1273         OCRDMA_REG_NSMR_ZB_SHIFT_MASK           = Bit(25),
1274         OCRDMA_REG_NSMR_REMOTE_INV_SHIFT        = 26,
1275         OCRDMA_REG_NSMR_REMOTE_INV_MASK         = Bit(26),
1276         OCRDMA_REG_NSMR_REMOTE_WR_SHIFT         = 27,
1277         OCRDMA_REG_NSMR_REMOTE_WR_MASK          = Bit(27),
1278         OCRDMA_REG_NSMR_REMOTE_RD_SHIFT         = 28,
1279         OCRDMA_REG_NSMR_REMOTE_RD_MASK          = Bit(28),
1280         OCRDMA_REG_NSMR_LOCAL_WR_SHIFT          = 29,
1281         OCRDMA_REG_NSMR_LOCAL_WR_MASK           = Bit(29),
1282         OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT     = 30,
1283         OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK      = Bit(30),
1284         OCRDMA_REG_NSMR_LAST_SHIFT              = 31,
1285         OCRDMA_REG_NSMR_LAST_MASK               = Bit(31)
1286 };
1287
1288 struct ocrdma_reg_nsmr {
1289         struct ocrdma_mqe_hdr hdr;
1290         struct ocrdma_mbx_hdr cmd;
1291
1292         u32 lrkey_key_index;
1293         u32 num_pbl_pdid;
1294         u32 flags_hpage_pbe_sz;
1295         u32 totlen_low;
1296         u32 totlen_high;
1297         u32 fbo_low;
1298         u32 fbo_high;
1299         u32 va_loaddr;
1300         u32 va_hiaddr;
1301         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1302 } __packed;
1303
1304 enum {
1305         OCRDMA_REG_NSMR_CONT_PBL_SHIFT          = 0,
1306         OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK     = 0xFFFF,
1307         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT      = 16,
1308         OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK       = 0xFFFF <<
1309                                         OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,
1310
1311         OCRDMA_REG_NSMR_CONT_LAST_SHIFT         = 31,
1312         OCRDMA_REG_NSMR_CONT_LAST_MASK          = Bit(31)
1313 };
1314
1315 struct ocrdma_reg_nsmr_cont {
1316         struct ocrdma_mqe_hdr hdr;
1317         struct ocrdma_mbx_hdr cmd;
1318
1319         u32 lrkey;
1320         u32 num_pbl_offset;
1321         u32 last;
1322
1323         struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];
1324 } __packed;
1325
1326 struct ocrdma_pbe {
1327         u32 pa_hi;
1328         u32 pa_lo;
1329 } __packed;
1330
1331 enum {
1332         OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT       = 16,
1333         OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK        = 0xFFFF0000
1334 };
1335 struct ocrdma_reg_nsmr_rsp {
1336         struct ocrdma_mqe_hdr hdr;
1337         struct ocrdma_mbx_rsp rsp;
1338
1339         u32 lrkey;
1340         u32 num_pbl;
1341 } __packed;
1342
1343 enum {
1344         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT      = 0,
1345         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK       = 0xFFFFFF,
1346         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT            = 24,
1347         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK             = 0xFF <<
1348                                         OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,
1349
1350         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT          = 16,
1351         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK           = 0xFFFF <<
1352                                         OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
1353 };
1354
1355 struct ocrdma_reg_nsmr_cont_rsp {
1356         struct ocrdma_mqe_hdr hdr;
1357         struct ocrdma_mbx_rsp rsp;
1358
1359         u32 lrkey_key_index;
1360         u32 num_pbl;
1361 } __packed;
1362
1363 enum {
1364         OCRDMA_ALLOC_MW_PD_ID_SHIFT     = 0,
1365         OCRDMA_ALLOC_MW_PD_ID_MASK      = 0xFFFF
1366 };
1367
1368 struct ocrdma_alloc_mw {
1369         struct ocrdma_mqe_hdr hdr;
1370         struct ocrdma_mbx_hdr req;
1371
1372         u32 pdid;
1373 } __packed;
1374
1375 enum {
1376         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT   = 0,
1377         OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK    = 0xFFFFFF
1378 };
1379
1380 struct ocrdma_alloc_mw_rsp {
1381         struct ocrdma_mqe_hdr hdr;
1382         struct ocrdma_mbx_rsp rsp;
1383
1384         u32 lrkey_index;
1385 } __packed;
1386
1387 struct ocrdma_attach_mcast {
1388         struct ocrdma_mqe_hdr hdr;
1389         struct ocrdma_mbx_hdr req;
1390         u32 qp_id;
1391         u8 mgid[16];
1392         u32 mac_b0_to_b3;
1393         u32 vlan_mac_b4_to_b5;
1394 } __packed;
1395
1396 struct ocrdma_attach_mcast_rsp {
1397         struct ocrdma_mqe_hdr hdr;
1398         struct ocrdma_mbx_rsp rsp;
1399 } __packed;
1400
1401 struct ocrdma_detach_mcast {
1402         struct ocrdma_mqe_hdr hdr;
1403         struct ocrdma_mbx_hdr req;
1404         u32 qp_id;
1405         u8 mgid[16];
1406         u32 mac_b0_to_b3;
1407         u32 vlan_mac_b4_to_b5;
1408 } __packed;
1409
1410 struct ocrdma_detach_mcast_rsp {
1411         struct ocrdma_mqe_hdr hdr;
1412         struct ocrdma_mbx_rsp rsp;
1413 } __packed;
1414
1415 enum {
1416         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT        = 19,
1417         OCRDMA_CREATE_AH_NUM_PAGES_MASK         = 0xF <<
1418                                         OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,
1419
1420         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT        = 16,
1421         OCRDMA_CREATE_AH_PAGE_SIZE_MASK         = 0x7 <<
1422                                         OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,
1423
1424         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT       = 23,
1425         OCRDMA_CREATE_AH_ENTRY_SIZE_MASK        = 0x1FF <<
1426                                         OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,
1427 };
1428
1429 #define OCRDMA_AH_TBL_PAGES 8
1430
1431 struct ocrdma_create_ah_tbl {
1432         struct ocrdma_mqe_hdr hdr;
1433         struct ocrdma_mbx_hdr req;
1434
1435         u32 ah_conf;
1436         struct ocrdma_pa tbl_addr[8];
1437 } __packed;
1438
1439 struct ocrdma_create_ah_tbl_rsp {
1440         struct ocrdma_mqe_hdr hdr;
1441         struct ocrdma_mbx_rsp rsp;
1442         u32 ahid;
1443 } __packed;
1444
1445 struct ocrdma_delete_ah_tbl {
1446         struct ocrdma_mqe_hdr hdr;
1447         struct ocrdma_mbx_hdr req;
1448         u32 ahid;
1449 } __packed;
1450
1451 struct ocrdma_delete_ah_tbl_rsp {
1452         struct ocrdma_mqe_hdr hdr;
1453         struct ocrdma_mbx_rsp rsp;
1454 } __packed;
1455
1456 enum {
1457         OCRDMA_EQE_VALID_SHIFT          = 0,
1458         OCRDMA_EQE_VALID_MASK           = Bit(0),
1459         OCRDMA_EQE_FOR_CQE_MASK         = 0xFFFE,
1460         OCRDMA_EQE_RESOURCE_ID_SHIFT    = 16,
1461         OCRDMA_EQE_RESOURCE_ID_MASK     = 0xFFFF <<
1462                                 OCRDMA_EQE_RESOURCE_ID_SHIFT,
1463 };
1464
1465 struct ocrdma_eqe {
1466         u32 id_valid;
1467 } __packed;
1468
1469 enum OCRDMA_CQE_STATUS {
1470         OCRDMA_CQE_SUCCESS = 0,
1471         OCRDMA_CQE_LOC_LEN_ERR,
1472         OCRDMA_CQE_LOC_QP_OP_ERR,
1473         OCRDMA_CQE_LOC_EEC_OP_ERR,
1474         OCRDMA_CQE_LOC_PROT_ERR,
1475         OCRDMA_CQE_WR_FLUSH_ERR,
1476         OCRDMA_CQE_MW_BIND_ERR,
1477         OCRDMA_CQE_BAD_RESP_ERR,
1478         OCRDMA_CQE_LOC_ACCESS_ERR,
1479         OCRDMA_CQE_REM_INV_REQ_ERR,
1480         OCRDMA_CQE_REM_ACCESS_ERR,
1481         OCRDMA_CQE_REM_OP_ERR,
1482         OCRDMA_CQE_RETRY_EXC_ERR,
1483         OCRDMA_CQE_RNR_RETRY_EXC_ERR,
1484         OCRDMA_CQE_LOC_RDD_VIOL_ERR,
1485         OCRDMA_CQE_REM_INV_RD_REQ_ERR,
1486         OCRDMA_CQE_REM_ABORT_ERR,
1487         OCRDMA_CQE_INV_EECN_ERR,
1488         OCRDMA_CQE_INV_EEC_STATE_ERR,
1489         OCRDMA_CQE_FATAL_ERR,
1490         OCRDMA_CQE_RESP_TIMEOUT_ERR,
1491         OCRDMA_CQE_GENERAL_ERR
1492 };
1493
1494 enum {
1495         /* w0 */
1496         OCRDMA_CQE_WQEIDX_SHIFT         = 0,
1497         OCRDMA_CQE_WQEIDX_MASK          = 0xFFFF,
1498
1499         /* w1 */
1500         OCRDMA_CQE_UD_XFER_LEN_SHIFT    = 16,
1501         OCRDMA_CQE_PKEY_SHIFT           = 0,
1502         OCRDMA_CQE_PKEY_MASK            = 0xFFFF,
1503
1504         /* w2 */
1505         OCRDMA_CQE_QPN_SHIFT            = 0,
1506         OCRDMA_CQE_QPN_MASK             = 0x0000FFFF,
1507
1508         OCRDMA_CQE_BUFTAG_SHIFT         = 16,
1509         OCRDMA_CQE_BUFTAG_MASK          = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,
1510
1511         /* w3 */
1512         OCRDMA_CQE_UD_STATUS_SHIFT      = 24,
1513         OCRDMA_CQE_UD_STATUS_MASK       = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,
1514         OCRDMA_CQE_STATUS_SHIFT         = 16,
1515         OCRDMA_CQE_STATUS_MASK          = 0xFF << OCRDMA_CQE_STATUS_SHIFT,
1516         OCRDMA_CQE_VALID                = Bit(31),
1517         OCRDMA_CQE_INVALIDATE           = Bit(30),
1518         OCRDMA_CQE_QTYPE                = Bit(29),
1519         OCRDMA_CQE_IMM                  = Bit(28),
1520         OCRDMA_CQE_WRITE_IMM            = Bit(27),
1521         OCRDMA_CQE_QTYPE_SQ             = 0,
1522         OCRDMA_CQE_QTYPE_RQ             = 1,
1523         OCRDMA_CQE_SRCQP_MASK           = 0xFFFFFF
1524 };
1525
1526 struct ocrdma_cqe {
1527         union {
1528                 /* w0 to w2 */
1529                 struct {
1530                         u32 wqeidx;
1531                         u32 bytes_xfered;
1532                         u32 qpn;
1533                 } wq;
1534                 struct {
1535                         u32 lkey_immdt;
1536                         u32 rxlen;
1537                         u32 buftag_qpn;
1538                 } rq;
1539                 struct {
1540                         u32 lkey_immdt;
1541                         u32 rxlen_pkey;
1542                         u32 buftag_qpn;
1543                 } ud;
1544                 struct {
1545                         u32 word_0;
1546                         u32 word_1;
1547                         u32 qpn;
1548                 } cmn;
1549         };
1550         u32 flags_status_srcqpn;        /* w3 */
1551 } __packed;
1552
1553 #define is_cqe_valid(cq, cqe) \
1554         (((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_VALID)\
1555         == cq->phase) ? 1 : 0)
1556 #define is_cqe_for_sq(cqe) \
1557         ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 0 : 1)
1558 #define is_cqe_for_rq(cqe) \
1559         ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_QTYPE) ? 1 : 0)
1560 #define is_cqe_invalidated(cqe) \
1561         ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_INVALIDATE) ? \
1562         1 : 0)
1563 #define is_cqe_imm(cqe) \
1564         ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_IMM) ? 1 : 0)
1565 #define is_cqe_wr_imm(cqe) \
1566         ((le32_to_cpu(cqe->flags_status_srcqpn) & OCRDMA_CQE_WRITE_IMM) ? 1 : 0)
1567
1568 struct ocrdma_sge {
1569         u32 addr_hi;
1570         u32 addr_lo;
1571         u32 lrkey;
1572         u32 len;
1573 } __packed;
1574
1575 enum {
1576         OCRDMA_FLAG_SIG         = 0x1,
1577         OCRDMA_FLAG_INV         = 0x2,
1578         OCRDMA_FLAG_FENCE_L     = 0x4,
1579         OCRDMA_FLAG_FENCE_R     = 0x8,
1580         OCRDMA_FLAG_SOLICIT     = 0x10,
1581         OCRDMA_FLAG_IMM         = 0x20,
1582
1583         /* Stag flags */
1584         OCRDMA_LKEY_FLAG_LOCAL_WR       = 0x1,
1585         OCRDMA_LKEY_FLAG_REMOTE_RD      = 0x2,
1586         OCRDMA_LKEY_FLAG_REMOTE_WR      = 0x4,
1587         OCRDMA_LKEY_FLAG_VATO           = 0x8,
1588 };
1589
1590 enum OCRDMA_WQE_OPCODE {
1591         OCRDMA_WRITE            = 0x06,
1592         OCRDMA_READ             = 0x0C,
1593         OCRDMA_RESV0            = 0x02,
1594         OCRDMA_SEND             = 0x00,
1595         OCRDMA_CMP_SWP          = 0x14,
1596         OCRDMA_BIND_MW          = 0x10,
1597         OCRDMA_RESV1            = 0x0A,
1598         OCRDMA_LKEY_INV         = 0x15,
1599         OCRDMA_FETCH_ADD        = 0x13,
1600         OCRDMA_POST_RQ          = 0x12
1601 };
1602
1603 enum {
1604         OCRDMA_TYPE_INLINE      = 0x0,
1605         OCRDMA_TYPE_LKEY        = 0x1,
1606 };
1607
1608 enum {
1609         OCRDMA_WQE_OPCODE_SHIFT         = 0,
1610         OCRDMA_WQE_OPCODE_MASK          = 0x0000001F,
1611         OCRDMA_WQE_FLAGS_SHIFT          = 5,
1612         OCRDMA_WQE_TYPE_SHIFT           = 16,
1613         OCRDMA_WQE_TYPE_MASK            = 0x00030000,
1614         OCRDMA_WQE_SIZE_SHIFT           = 18,
1615         OCRDMA_WQE_SIZE_MASK            = 0xFF,
1616         OCRDMA_WQE_NXT_WQE_SIZE_SHIFT   = 25,
1617
1618         OCRDMA_WQE_LKEY_FLAGS_SHIFT     = 0,
1619         OCRDMA_WQE_LKEY_FLAGS_MASK      = 0xF
1620 };
1621
1622 /* header WQE for all the SQ and RQ operations */
1623 struct ocrdma_hdr_wqe {
1624         u32 cw;
1625         union {
1626                 u32 rsvd_tag;
1627                 u32 rsvd_lkey_flags;
1628         };
1629         union {
1630                 u32 immdt;
1631                 u32 lkey;
1632         };
1633         u32 total_len;
1634 } __packed;
1635
1636 struct ocrdma_ewqe_ud_hdr {
1637         u32 rsvd_dest_qpn;
1638         u32 qkey;
1639         u32 rsvd_ahid;
1640         u32 rsvd;
1641 } __packed;
1642
1643 struct ocrdma_eth_basic {
1644         u8 dmac[6];
1645         u8 smac[6];
1646         __be16 eth_type;
1647 } __packed;
1648
1649 struct ocrdma_eth_vlan {
1650         u8 dmac[6];
1651         u8 smac[6];
1652         __be16 eth_type;
1653         __be16 vlan_tag;
1654 #define OCRDMA_ROCE_ETH_TYPE 0x8915
1655         __be16 roce_eth_type;
1656 } __packed;
1657
1658 struct ocrdma_grh {
1659         __be32  tclass_flow;
1660         __be32  pdid_hoplimit;
1661         u8      sgid[16];
1662         u8      dgid[16];
1663         u16     rsvd;
1664 } __packed;
1665
1666 #define OCRDMA_AV_VALID         Bit(0)
1667 #define OCRDMA_AV_VLAN_VALID    Bit(1)
1668
1669 struct ocrdma_av {
1670         struct ocrdma_eth_vlan eth_hdr;
1671         struct ocrdma_grh grh;
1672         u32 valid;
1673 } __packed;
1674
1675 #endif                          /* __OCRDMA_SLI_H__ */