2 * omap iommu: tlb and pagetable primitives
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/err.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/iommu.h>
20 #include <linux/omap-iommu.h>
21 #include <linux/mutex.h>
22 #include <linux/spinlock.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/of_iommu.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
30 #include <asm/cacheflush.h>
32 #include <linux/platform_data/iommu-omap.h>
34 #include "omap-iopgtable.h"
35 #include "omap-iommu.h"
37 #define to_iommu(dev) \
38 ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev)))
40 #define for_each_iotlb_cr(obj, n, __i, cr) \
42 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
45 /* bitmap of the page sizes currently supported */
46 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
49 * struct omap_iommu_domain - omap iommu domain
50 * @pgtable: the page table
51 * @iommu_dev: an omap iommu device attached to this domain. only a single
52 * iommu device can be attached for now.
53 * @dev: Device using this domain.
54 * @lock: domain lock, should be taken when attaching/detaching
56 struct omap_iommu_domain {
58 struct omap_iommu *iommu_dev;
61 struct iommu_domain domain;
64 #define MMU_LOCK_BASE_SHIFT 10
65 #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
66 #define MMU_LOCK_BASE(x) \
67 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
69 #define MMU_LOCK_VICT_SHIFT 4
70 #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
71 #define MMU_LOCK_VICT(x) \
72 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
79 static struct platform_driver omap_iommu_driver;
80 static struct kmem_cache *iopte_cachep;
83 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain
84 * @dom: generic iommu domain handle
86 static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom)
88 return container_of(dom, struct omap_iommu_domain, domain);
92 * omap_iommu_save_ctx - Save registers for pm off-mode support
95 void omap_iommu_save_ctx(struct device *dev)
97 struct omap_iommu *obj = dev_to_omap_iommu(dev);
101 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
102 p[i] = iommu_read_reg(obj, i * sizeof(u32));
103 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
106 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
109 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
110 * @dev: client device
112 void omap_iommu_restore_ctx(struct device *dev)
114 struct omap_iommu *obj = dev_to_omap_iommu(dev);
118 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
119 iommu_write_reg(obj, p[i], i * sizeof(u32));
120 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
123 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
125 static void __iommu_set_twl(struct omap_iommu *obj, bool on)
127 u32 l = iommu_read_reg(obj, MMU_CNTL);
130 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
132 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
136 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
138 l |= (MMU_CNTL_MMU_EN);
140 iommu_write_reg(obj, l, MMU_CNTL);
143 static int omap2_iommu_enable(struct omap_iommu *obj)
147 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
150 pa = virt_to_phys(obj->iopgd);
151 if (!IS_ALIGNED(pa, SZ_16K))
154 l = iommu_read_reg(obj, MMU_REVISION);
155 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
156 (l >> 4) & 0xf, l & 0xf);
158 iommu_write_reg(obj, pa, MMU_TTB);
160 if (obj->has_bus_err_back)
161 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
163 __iommu_set_twl(obj, true);
168 static void omap2_iommu_disable(struct omap_iommu *obj)
170 u32 l = iommu_read_reg(obj, MMU_CNTL);
173 iommu_write_reg(obj, l, MMU_CNTL);
175 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
178 static int iommu_enable(struct omap_iommu *obj)
181 struct platform_device *pdev = to_platform_device(obj->dev);
182 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
184 if (pdata && pdata->deassert_reset) {
185 err = pdata->deassert_reset(pdev, pdata->reset_name);
187 dev_err(obj->dev, "deassert_reset failed: %d\n", err);
192 pm_runtime_get_sync(obj->dev);
194 err = omap2_iommu_enable(obj);
199 static void iommu_disable(struct omap_iommu *obj)
201 struct platform_device *pdev = to_platform_device(obj->dev);
202 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
204 omap2_iommu_disable(obj);
206 pm_runtime_put_sync(obj->dev);
208 if (pdata && pdata->assert_reset)
209 pdata->assert_reset(pdev, pdata->reset_name);
215 static inline int iotlb_cr_valid(struct cr_regs *cr)
220 return cr->cam & MMU_CAM_V;
223 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
225 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
226 u32 mask = get_cam_va_mask(cr->cam & page_size);
228 return cr->cam & mask;
231 static u32 get_iopte_attr(struct iotlb_entry *e)
235 attr = e->mixed << 5;
237 attr |= e->elsz >> 3;
238 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
239 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
243 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
245 u32 status, fault_addr;
247 status = iommu_read_reg(obj, MMU_IRQSTATUS);
248 status &= MMU_IRQ_MASK;
254 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD);
257 iommu_write_reg(obj, status, MMU_IRQSTATUS);
262 static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
266 val = iommu_read_reg(obj, MMU_LOCK);
268 l->base = MMU_LOCK_BASE(val);
269 l->vict = MMU_LOCK_VICT(val);
273 static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
277 val = (l->base << MMU_LOCK_BASE_SHIFT);
278 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
280 iommu_write_reg(obj, val, MMU_LOCK);
283 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
285 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
286 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
289 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
291 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
292 iommu_write_reg(obj, cr->ram, MMU_RAM);
294 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
295 iommu_write_reg(obj, 1, MMU_LD_TLB);
298 /* only used in iotlb iteration for-loop */
299 static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
304 iotlb_lock_get(obj, &l);
306 iotlb_lock_set(obj, &l);
307 iotlb_read_cr(obj, &cr);
312 #ifdef PREFETCH_IOTLB
313 static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
314 struct iotlb_entry *e)
321 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
322 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
324 return ERR_PTR(-EINVAL);
327 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
329 return ERR_PTR(-ENOMEM);
331 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
332 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
338 * load_iotlb_entry - Set an iommu tlb entry
340 * @e: an iommu tlb entry info
342 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
348 if (!obj || !obj->nr_tlb_entries || !e)
351 pm_runtime_get_sync(obj->dev);
353 iotlb_lock_get(obj, &l);
354 if (l.base == obj->nr_tlb_entries) {
355 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
363 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
364 if (!iotlb_cr_valid(&tmp))
367 if (i == obj->nr_tlb_entries) {
368 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
373 iotlb_lock_get(obj, &l);
376 iotlb_lock_set(obj, &l);
379 cr = iotlb_alloc_cr(obj, e);
381 pm_runtime_put_sync(obj->dev);
385 iotlb_load_cr(obj, cr);
390 /* increment victim for next tlb load */
391 if (++l.vict == obj->nr_tlb_entries)
393 iotlb_lock_set(obj, &l);
395 pm_runtime_put_sync(obj->dev);
399 #else /* !PREFETCH_IOTLB */
401 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
406 #endif /* !PREFETCH_IOTLB */
408 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
410 return load_iotlb_entry(obj, e);
414 * flush_iotlb_page - Clear an iommu tlb entry
416 * @da: iommu device virtual address
418 * Clear an iommu tlb entry which includes 'da' address.
420 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
425 pm_runtime_get_sync(obj->dev);
427 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
431 if (!iotlb_cr_valid(&cr))
434 start = iotlb_cr_to_virt(&cr);
435 bytes = iopgsz_to_bytes(cr.cam & 3);
437 if ((start <= da) && (da < start + bytes)) {
438 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
439 __func__, start, da, bytes);
440 iotlb_load_cr(obj, &cr);
441 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
445 pm_runtime_put_sync(obj->dev);
447 if (i == obj->nr_tlb_entries)
448 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
452 * flush_iotlb_all - Clear all iommu tlb entries
455 static void flush_iotlb_all(struct omap_iommu *obj)
459 pm_runtime_get_sync(obj->dev);
463 iotlb_lock_set(obj, &l);
465 iommu_write_reg(obj, 1, MMU_GFLUSH);
467 pm_runtime_put_sync(obj->dev);
470 #ifdef CONFIG_OMAP_IOMMU_DEBUG
472 #define pr_reg(name) \
475 const char *str = "%20s: %08x\n"; \
476 const int maxcol = 32; \
477 bytes = snprintf(p, maxcol, str, __stringify(name), \
478 iommu_read_reg(obj, MMU_##name)); \
486 omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len)
505 pr_reg(EMU_FAULT_AD);
510 ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
515 pm_runtime_get_sync(obj->dev);
517 bytes = omap2_iommu_dump_ctx(obj, buf, bytes);
519 pm_runtime_put_sync(obj->dev);
525 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
528 struct iotlb_lock saved;
530 struct cr_regs *p = crs;
532 pm_runtime_get_sync(obj->dev);
533 iotlb_lock_get(obj, &saved);
535 for_each_iotlb_cr(obj, num, i, tmp) {
536 if (!iotlb_cr_valid(&tmp))
541 iotlb_lock_set(obj, &saved);
542 pm_runtime_put_sync(obj->dev);
548 * iotlb_dump_cr - Dump an iommu tlb entry into buf
550 * @cr: contents of cam and ram register
551 * @buf: output buffer
553 static ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
558 /* FIXME: Need more detail analysis of cam/ram */
559 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
560 (cr->cam & MMU_CAM_P) ? 1 : 0);
566 * omap_dump_tlb_entries - dump cr arrays to given buffer
568 * @buf: output buffer
570 size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
576 num = bytes / sizeof(*cr);
577 num = min(obj->nr_tlb_entries, num);
579 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
583 num = __dump_tlb_entries(obj, cr, num);
584 for (i = 0; i < num; i++)
585 p += iotlb_dump_cr(obj, cr + i, p);
591 #endif /* CONFIG_OMAP_IOMMU_DEBUG */
594 * H/W pagetable operations
596 static void flush_iopgd_range(u32 *first, u32 *last)
598 /* FIXME: L2 cache should be taken care of if it exists */
600 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
602 first += L1_CACHE_BYTES / sizeof(*first);
603 } while (first <= last);
606 static void flush_iopte_range(u32 *first, u32 *last)
608 /* FIXME: L2 cache should be taken care of if it exists */
610 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
612 first += L1_CACHE_BYTES / sizeof(*first);
613 } while (first <= last);
616 static void iopte_free(u32 *iopte)
618 /* Note: freed iopte's must be clean ready for re-use */
620 kmem_cache_free(iopte_cachep, iopte);
623 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
627 /* a table has already existed */
632 * do the allocation outside the page table lock
634 spin_unlock(&obj->page_table_lock);
635 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
636 spin_lock(&obj->page_table_lock);
640 return ERR_PTR(-ENOMEM);
642 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
643 flush_iopgd_range(iopgd, iopgd);
645 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
647 /* We raced, free the reduniovant table */
652 iopte = iopte_offset(iopgd, da);
655 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
656 __func__, da, iopgd, *iopgd, iopte, *iopte);
661 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
663 u32 *iopgd = iopgd_offset(obj, da);
665 if ((da | pa) & ~IOSECTION_MASK) {
666 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
667 __func__, da, pa, IOSECTION_SIZE);
671 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
672 flush_iopgd_range(iopgd, iopgd);
676 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
678 u32 *iopgd = iopgd_offset(obj, da);
681 if ((da | pa) & ~IOSUPER_MASK) {
682 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
683 __func__, da, pa, IOSUPER_SIZE);
687 for (i = 0; i < 16; i++)
688 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
689 flush_iopgd_range(iopgd, iopgd + 15);
693 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
695 u32 *iopgd = iopgd_offset(obj, da);
696 u32 *iopte = iopte_alloc(obj, iopgd, da);
699 return PTR_ERR(iopte);
701 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
702 flush_iopte_range(iopte, iopte);
704 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
705 __func__, da, pa, iopte, *iopte);
710 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
712 u32 *iopgd = iopgd_offset(obj, da);
713 u32 *iopte = iopte_alloc(obj, iopgd, da);
716 if ((da | pa) & ~IOLARGE_MASK) {
717 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
718 __func__, da, pa, IOLARGE_SIZE);
723 return PTR_ERR(iopte);
725 for (i = 0; i < 16; i++)
726 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
727 flush_iopte_range(iopte, iopte + 15);
732 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
734 int (*fn)(struct omap_iommu *, u32, u32, u32);
742 case MMU_CAM_PGSZ_16M:
743 fn = iopgd_alloc_super;
745 case MMU_CAM_PGSZ_1M:
746 fn = iopgd_alloc_section;
748 case MMU_CAM_PGSZ_64K:
749 fn = iopte_alloc_large;
751 case MMU_CAM_PGSZ_4K:
752 fn = iopte_alloc_page;
760 prot = get_iopte_attr(e);
762 spin_lock(&obj->page_table_lock);
763 err = fn(obj, e->da, e->pa, prot);
764 spin_unlock(&obj->page_table_lock);
770 * omap_iopgtable_store_entry - Make an iommu pte entry
772 * @e: an iommu tlb entry info
775 omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
779 flush_iotlb_page(obj, e->da);
780 err = iopgtable_store_entry_core(obj, e);
782 prefetch_iotlb_entry(obj, e);
787 * iopgtable_lookup_entry - Lookup an iommu pte entry
789 * @da: iommu device virtual address
790 * @ppgd: iommu pgd entry pointer to be returned
791 * @ppte: iommu pte entry pointer to be returned
794 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
796 u32 *iopgd, *iopte = NULL;
798 iopgd = iopgd_offset(obj, da);
802 if (iopgd_is_table(*iopgd))
803 iopte = iopte_offset(iopgd, da);
809 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
812 u32 *iopgd = iopgd_offset(obj, da);
818 if (iopgd_is_table(*iopgd)) {
820 u32 *iopte = iopte_offset(iopgd, da);
823 if (*iopte & IOPTE_LARGE) {
825 /* rewind to the 1st entry */
826 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
829 memset(iopte, 0, nent * sizeof(*iopte));
830 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
833 * do table walk to check if this table is necessary or not
835 iopte = iopte_offset(iopgd, 0);
836 for (i = 0; i < PTRS_PER_IOPTE; i++)
841 nent = 1; /* for the next L1 entry */
844 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
846 /* rewind to the 1st entry */
847 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
851 memset(iopgd, 0, nent * sizeof(*iopgd));
852 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
858 * iopgtable_clear_entry - Remove an iommu pte entry
860 * @da: iommu device virtual address
862 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
866 spin_lock(&obj->page_table_lock);
868 bytes = iopgtable_clear_entry_core(obj, da);
869 flush_iotlb_page(obj, da);
871 spin_unlock(&obj->page_table_lock);
876 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
880 spin_lock(&obj->page_table_lock);
882 for (i = 0; i < PTRS_PER_IOPGD; i++) {
886 da = i << IOPGD_SHIFT;
887 iopgd = iopgd_offset(obj, da);
892 if (iopgd_is_table(*iopgd))
893 iopte_free(iopte_offset(iopgd, 0));
896 flush_iopgd_range(iopgd, iopgd);
899 flush_iotlb_all(obj);
901 spin_unlock(&obj->page_table_lock);
905 * Device IOMMU generic operations
907 static irqreturn_t iommu_fault_handler(int irq, void *data)
911 struct omap_iommu *obj = data;
912 struct iommu_domain *domain = obj->domain;
913 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
915 if (!omap_domain->iommu_dev)
918 errs = iommu_report_fault(obj, &da);
922 /* Fault callback or TLB/PTE Dynamic loading */
923 if (!report_iommu_fault(domain, obj->dev, da, 0))
928 iopgd = iopgd_offset(obj, da);
930 if (!iopgd_is_table(*iopgd)) {
931 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
932 obj->name, errs, da, iopgd, *iopgd);
936 iopte = iopte_offset(iopgd, da);
938 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
939 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
944 static int device_match_by_alias(struct device *dev, void *data)
946 struct omap_iommu *obj = to_iommu(dev);
947 const char *name = data;
949 pr_debug("%s: %s %s\n", __func__, obj->name, name);
951 return strcmp(obj->name, name) == 0;
955 * omap_iommu_attach() - attach iommu device to an iommu domain
956 * @name: name of target omap iommu device
959 static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
963 struct omap_iommu *obj;
965 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
967 device_match_by_alias);
969 return ERR_PTR(-ENODEV);
973 spin_lock(&obj->iommu_lock);
976 err = iommu_enable(obj);
979 flush_iotlb_all(obj);
981 spin_unlock(&obj->iommu_lock);
983 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
987 spin_unlock(&obj->iommu_lock);
992 * omap_iommu_detach - release iommu device
995 static void omap_iommu_detach(struct omap_iommu *obj)
997 if (!obj || IS_ERR(obj))
1000 spin_lock(&obj->iommu_lock);
1005 spin_unlock(&obj->iommu_lock);
1007 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
1011 * OMAP Device MMU(IOMMU) detection
1013 static int omap_iommu_probe(struct platform_device *pdev)
1017 struct omap_iommu *obj;
1018 struct resource *res;
1019 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
1020 struct device_node *of = pdev->dev.of_node;
1022 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
1027 obj->name = dev_name(&pdev->dev);
1028 obj->nr_tlb_entries = 32;
1029 err = of_property_read_u32(of, "ti,#tlb-entries",
1030 &obj->nr_tlb_entries);
1031 if (err && err != -EINVAL)
1033 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
1035 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
1036 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
1038 obj->nr_tlb_entries = pdata->nr_tlb_entries;
1039 obj->name = pdata->name;
1042 obj->dev = &pdev->dev;
1043 obj->ctx = (void *)obj + sizeof(*obj);
1045 spin_lock_init(&obj->iommu_lock);
1046 spin_lock_init(&obj->page_table_lock);
1048 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1049 obj->regbase = devm_ioremap_resource(obj->dev, res);
1050 if (IS_ERR(obj->regbase))
1051 return PTR_ERR(obj->regbase);
1053 irq = platform_get_irq(pdev, 0);
1057 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
1058 dev_name(obj->dev), obj);
1061 platform_set_drvdata(pdev, obj);
1063 pm_runtime_irq_safe(obj->dev);
1064 pm_runtime_enable(obj->dev);
1066 omap_iommu_debugfs_add(obj);
1068 dev_info(&pdev->dev, "%s registered\n", obj->name);
1072 static int omap_iommu_remove(struct platform_device *pdev)
1074 struct omap_iommu *obj = platform_get_drvdata(pdev);
1076 iopgtable_clear_entry_all(obj);
1077 omap_iommu_debugfs_remove(obj);
1079 pm_runtime_disable(obj->dev);
1081 dev_info(&pdev->dev, "%s removed\n", obj->name);
1085 static const struct of_device_id omap_iommu_of_match[] = {
1086 { .compatible = "ti,omap2-iommu" },
1087 { .compatible = "ti,omap4-iommu" },
1088 { .compatible = "ti,dra7-iommu" },
1092 static struct platform_driver omap_iommu_driver = {
1093 .probe = omap_iommu_probe,
1094 .remove = omap_iommu_remove,
1096 .name = "omap-iommu",
1097 .of_match_table = of_match_ptr(omap_iommu_of_match),
1101 static void iopte_cachep_ctor(void *iopte)
1103 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1106 static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
1108 memset(e, 0, sizeof(*e));
1112 e->valid = MMU_CAM_V;
1114 e->endian = MMU_RAM_ENDIAN_LITTLE;
1115 e->elsz = MMU_RAM_ELSZ_8;
1118 return iopgsz_to_bytes(e->pgsz);
1121 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1122 phys_addr_t pa, size_t bytes, int prot)
1124 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1125 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1126 struct device *dev = oiommu->dev;
1127 struct iotlb_entry e;
1131 omap_pgsz = bytes_to_iopgsz(bytes);
1132 if (omap_pgsz < 0) {
1133 dev_err(dev, "invalid size to map: %d\n", bytes);
1137 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes);
1139 iotlb_init_entry(&e, da, pa, omap_pgsz);
1141 ret = omap_iopgtable_store_entry(oiommu, &e);
1143 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1148 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1151 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1152 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1153 struct device *dev = oiommu->dev;
1155 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1157 return iopgtable_clear_entry(oiommu, da);
1161 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1163 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1164 struct omap_iommu *oiommu;
1165 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1168 if (!arch_data || !arch_data->name) {
1169 dev_err(dev, "device doesn't have an associated iommu\n");
1173 spin_lock(&omap_domain->lock);
1175 /* only a single device is supported per domain for now */
1176 if (omap_domain->iommu_dev) {
1177 dev_err(dev, "iommu domain is already attached\n");
1182 /* get a handle to and enable the omap iommu */
1183 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
1184 if (IS_ERR(oiommu)) {
1185 ret = PTR_ERR(oiommu);
1186 dev_err(dev, "can't get omap iommu: %d\n", ret);
1190 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
1191 omap_domain->dev = dev;
1192 oiommu->domain = domain;
1195 spin_unlock(&omap_domain->lock);
1199 static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1202 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
1203 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1205 /* only a single device is supported per domain for now */
1206 if (omap_domain->iommu_dev != oiommu) {
1207 dev_err(dev, "invalid iommu device\n");
1211 iopgtable_clear_entry_all(oiommu);
1213 omap_iommu_detach(oiommu);
1215 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
1216 omap_domain->dev = NULL;
1217 oiommu->domain = NULL;
1220 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1223 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1225 spin_lock(&omap_domain->lock);
1226 _omap_iommu_detach_dev(omap_domain, dev);
1227 spin_unlock(&omap_domain->lock);
1230 static struct iommu_domain *omap_iommu_domain_alloc(unsigned type)
1232 struct omap_iommu_domain *omap_domain;
1234 if (type != IOMMU_DOMAIN_UNMANAGED)
1237 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1239 pr_err("kzalloc failed\n");
1243 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1244 if (!omap_domain->pgtable) {
1245 pr_err("kzalloc failed\n");
1250 * should never fail, but please keep this around to ensure
1251 * we keep the hardware happy
1253 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1255 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1256 spin_lock_init(&omap_domain->lock);
1258 omap_domain->domain.geometry.aperture_start = 0;
1259 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1;
1260 omap_domain->domain.geometry.force_aperture = true;
1262 return &omap_domain->domain;
1270 static void omap_iommu_domain_free(struct iommu_domain *domain)
1272 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1275 * An iommu device is still attached
1276 * (currently, only one device can be attached) ?
1278 if (omap_domain->iommu_dev)
1279 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1281 kfree(omap_domain->pgtable);
1285 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1288 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1289 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1290 struct device *dev = oiommu->dev;
1292 phys_addr_t ret = 0;
1294 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1297 if (iopte_is_small(*pte))
1298 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1299 else if (iopte_is_large(*pte))
1300 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1302 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1303 (unsigned long long)da);
1305 if (iopgd_is_section(*pgd))
1306 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1307 else if (iopgd_is_super(*pgd))
1308 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1310 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1311 (unsigned long long)da);
1317 static int omap_iommu_add_device(struct device *dev)
1319 struct omap_iommu_arch_data *arch_data;
1320 struct device_node *np;
1321 struct platform_device *pdev;
1324 * Allocate the archdata iommu structure for DT-based devices.
1326 * TODO: Simplify this when removing non-DT support completely from the
1332 np = of_parse_phandle(dev->of_node, "iommus", 0);
1336 pdev = of_find_device_by_node(np);
1337 if (WARN_ON(!pdev)) {
1342 arch_data = kzalloc(sizeof(*arch_data), GFP_KERNEL);
1348 arch_data->name = kstrdup(dev_name(&pdev->dev), GFP_KERNEL);
1349 dev->archdata.iommu = arch_data;
1356 static void omap_iommu_remove_device(struct device *dev)
1358 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1360 if (!dev->of_node || !arch_data)
1363 kfree(arch_data->name);
1367 static const struct iommu_ops omap_iommu_ops = {
1368 .domain_alloc = omap_iommu_domain_alloc,
1369 .domain_free = omap_iommu_domain_free,
1370 .attach_dev = omap_iommu_attach_dev,
1371 .detach_dev = omap_iommu_detach_dev,
1372 .map = omap_iommu_map,
1373 .unmap = omap_iommu_unmap,
1374 .map_sg = default_iommu_map_sg,
1375 .iova_to_phys = omap_iommu_iova_to_phys,
1376 .add_device = omap_iommu_add_device,
1377 .remove_device = omap_iommu_remove_device,
1378 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
1381 static int __init omap_iommu_init(void)
1383 struct kmem_cache *p;
1384 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1385 size_t align = 1 << 10; /* L2 pagetable alignement */
1386 struct device_node *np;
1388 np = of_find_matching_node(NULL, omap_iommu_of_match);
1394 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1400 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1402 omap_iommu_debugfs_init();
1404 return platform_driver_register(&omap_iommu_driver);
1406 subsys_initcall(omap_iommu_init);
1407 /* must be ready before omap3isp is probed */