]> git.kernelconcepts.de Git - karo-tx-linux.git/blob - drivers/irqchip/irq-ingenic.c
Merge branch 'for-rafael' of https://git.kernel.org/pub/scm/linux/kernel/git/mzx...
[karo-tx-linux.git] / drivers / irqchip / irq-ingenic.c
1 /*
2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3  *  JZ4740 platform IRQ support
4  *
5  *  This program is free software; you can redistribute it and/or modify it
6  *  under  the terms of the GNU General  Public License as published by the
7  *  Free Software Foundation;  either version 2 of the License, or (at your
8  *  option) any later version.
9  *
10  *  You should have received a copy of the GNU General Public License along
11  *  with this program; if not, write to the Free Software Foundation, Inc.,
12  *  675 Mass Ave, Cambridge, MA 02139, USA.
13  *
14  */
15
16 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/types.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/irqchip.h>
22 #include <linux/irqchip/ingenic.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/timex.h>
26 #include <linux/slab.h>
27 #include <linux/delay.h>
28
29 #include <asm/io.h>
30 #include <asm/mach-jz4740/irq.h>
31
32 struct ingenic_intc_data {
33         void __iomem *base;
34         unsigned num_chips;
35 };
36
37 #define JZ_REG_INTC_STATUS      0x00
38 #define JZ_REG_INTC_MASK        0x04
39 #define JZ_REG_INTC_SET_MASK    0x08
40 #define JZ_REG_INTC_CLEAR_MASK  0x0c
41 #define JZ_REG_INTC_PENDING     0x10
42 #define CHIP_SIZE               0x20
43
44 static irqreturn_t intc_cascade(int irq, void *data)
45 {
46         struct ingenic_intc_data *intc = irq_get_handler_data(irq);
47         uint32_t irq_reg;
48         unsigned i;
49
50         for (i = 0; i < intc->num_chips; i++) {
51                 irq_reg = readl(intc->base + (i * CHIP_SIZE) +
52                                 JZ_REG_INTC_PENDING);
53                 if (!irq_reg)
54                         continue;
55
56                 generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
57         }
58
59         return IRQ_HANDLED;
60 }
61
62 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
63 {
64         struct irq_chip_regs *regs = &gc->chip_types->regs;
65
66         writel(mask, gc->reg_base + regs->enable);
67         writel(~mask, gc->reg_base + regs->disable);
68 }
69
70 void ingenic_intc_irq_suspend(struct irq_data *data)
71 {
72         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
73         intc_irq_set_mask(gc, gc->wake_active);
74 }
75
76 void ingenic_intc_irq_resume(struct irq_data *data)
77 {
78         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
79         intc_irq_set_mask(gc, gc->mask_cache);
80 }
81
82 static struct irqaction intc_cascade_action = {
83         .handler = intc_cascade,
84         .name = "SoC intc cascade interrupt",
85 };
86
87 static int __init ingenic_intc_of_init(struct device_node *node,
88                                        unsigned num_chips)
89 {
90         struct ingenic_intc_data *intc;
91         struct irq_chip_generic *gc;
92         struct irq_chip_type *ct;
93         struct irq_domain *domain;
94         int parent_irq, err = 0;
95         unsigned i;
96
97         intc = kzalloc(sizeof(*intc), GFP_KERNEL);
98         if (!intc) {
99                 err = -ENOMEM;
100                 goto out_err;
101         }
102
103         parent_irq = irq_of_parse_and_map(node, 0);
104         if (!parent_irq) {
105                 err = -EINVAL;
106                 goto out_free;
107         }
108
109         err = irq_set_handler_data(parent_irq, intc);
110         if (err)
111                 goto out_unmap_irq;
112
113         intc->num_chips = num_chips;
114         intc->base = of_iomap(node, 0);
115         if (!intc->base) {
116                 err = -ENODEV;
117                 goto out_unmap_irq;
118         }
119
120         for (i = 0; i < num_chips; i++) {
121                 /* Mask all irqs */
122                 writel(0xffffffff, intc->base + (i * CHIP_SIZE) +
123                        JZ_REG_INTC_SET_MASK);
124
125                 gc = irq_alloc_generic_chip("INTC", 1,
126                                             JZ4740_IRQ_BASE + (i * 32),
127                                             intc->base + (i * CHIP_SIZE),
128                                             handle_level_irq);
129
130                 gc->wake_enabled = IRQ_MSK(32);
131
132                 ct = gc->chip_types;
133                 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
134                 ct->regs.disable = JZ_REG_INTC_SET_MASK;
135                 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
136                 ct->chip.irq_mask = irq_gc_mask_disable_reg;
137                 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
138                 ct->chip.irq_set_wake = irq_gc_set_wake;
139                 ct->chip.irq_suspend = ingenic_intc_irq_suspend;
140                 ct->chip.irq_resume = ingenic_intc_irq_resume;
141
142                 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0,
143                                        IRQ_NOPROBE | IRQ_LEVEL);
144         }
145
146         domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0,
147                                        &irq_domain_simple_ops, NULL);
148         if (!domain)
149                 pr_warn("unable to register IRQ domain\n");
150
151         setup_irq(parent_irq, &intc_cascade_action);
152         return 0;
153
154 out_unmap_irq:
155         irq_dispose_mapping(parent_irq);
156 out_free:
157         kfree(intc);
158 out_err:
159         return err;
160 }
161
162 static int __init intc_1chip_of_init(struct device_node *node,
163                                      struct device_node *parent)
164 {
165         return ingenic_intc_of_init(node, 1);
166 }
167 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
168
169 static int __init intc_2chip_of_init(struct device_node *node,
170         struct device_node *parent)
171 {
172         return ingenic_intc_of_init(node, 2);
173 }
174 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
175 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
176 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);