2 * isac.c ISAC specific routines
4 * Author Karsten Keil <keil@isdn4linux.de>
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/irqreturn.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/mISDNhw.h>
30 #define DBUSY_TIMER_VALUE 80
33 #define ISAC_REV "2.0"
35 MODULE_AUTHOR("Karsten Keil");
36 MODULE_VERSION(ISAC_REV);
37 MODULE_LICENSE("GPL v2");
39 #define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off))
40 #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
41 #define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o))
42 #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
43 #define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o))
44 #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
47 ph_command(struct isac_hw *isac, u8 command)
49 pr_debug("%s: ph_command %x\n", isac->name, command);
50 if (isac->type & IPAC_TYPE_ISACX)
51 WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE);
53 WriteISAC(isac, ISAC_CIX0, (command << 2) | 3);
57 isac_ph_state_change(struct isac_hw *isac)
59 switch (isac->state) {
62 ph_command(isac, ISAC_CMD_DUI);
64 schedule_event(&isac->dch, FLG_PHCHANGE);
68 isac_ph_state_bh(struct dchannel *dch)
70 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
72 switch (isac->state) {
76 l1_event(dch->l1, HW_RESET_IND);
80 l1_event(dch->l1, HW_DEACT_CNF);
85 l1_event(dch->l1, HW_DEACT_IND);
89 l1_event(dch->l1, HW_POWERUP_IND);
92 if (dch->state <= 5) {
94 l1_event(dch->l1, ANYSIGNAL);
97 l1_event(dch->l1, LOSTFRAMING);
102 l1_event(dch->l1, INFO2);
106 l1_event(dch->l1, INFO4_P8);
110 l1_event(dch->l1, INFO4_P10);
113 pr_debug("%s: TE newstate %x\n", isac->name, dch->state);
117 isac_empty_fifo(struct isac_hw *isac, int count)
121 pr_debug("%s: %s %d\n", isac->name, __func__, count);
123 if (!isac->dch.rx_skb) {
124 isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC);
125 if (!isac->dch.rx_skb) {
126 pr_info("%s: D receive out of memory\n", isac->name);
127 WriteISAC(isac, ISAC_CMDR, 0x80);
131 if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) {
132 pr_debug("%s: %s overrun %d\n", isac->name, __func__,
133 isac->dch.rx_skb->len + count);
134 WriteISAC(isac, ISAC_CMDR, 0x80);
137 ptr = skb_put(isac->dch.rx_skb, count);
138 isac->read_fifo(isac->dch.hw, isac->off, ptr, count);
139 WriteISAC(isac, ISAC_CMDR, 0x80);
140 if (isac->dch.debug & DEBUG_HW_DFIFO) {
141 char pfx[MISDN_MAX_IDLEN + 16];
143 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ",
145 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
150 isac_fill_fifo(struct isac_hw *isac)
155 if (!isac->dch.tx_skb)
157 count = isac->dch.tx_skb->len - isac->dch.tx_idx;
166 pr_debug("%s: %s %d\n", isac->name, __func__, count);
167 ptr = isac->dch.tx_skb->data + isac->dch.tx_idx;
168 isac->dch.tx_idx += count;
169 isac->write_fifo(isac->dch.hw, isac->off, ptr, count);
170 WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa);
171 if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
172 pr_debug("%s: %s dbusytimer running\n", isac->name, __func__);
173 del_timer(&isac->dch.timer);
175 init_timer(&isac->dch.timer);
176 isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
177 add_timer(&isac->dch.timer);
178 if (isac->dch.debug & DEBUG_HW_DFIFO) {
179 char pfx[MISDN_MAX_IDLEN + 16];
181 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ",
183 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
188 isac_rme_irq(struct isac_hw *isac)
192 val = ReadISAC(isac, ISAC_RSTA);
193 if ((val & 0x70) != 0x20) {
195 pr_debug("%s: ISAC RDO\n", isac->name);
196 #ifdef ERROR_STATISTIC
201 pr_debug("%s: ISAC CRC error\n", isac->name);
202 #ifdef ERROR_STATISTIC
206 WriteISAC(isac, ISAC_CMDR, 0x80);
207 if (isac->dch.rx_skb)
208 dev_kfree_skb(isac->dch.rx_skb);
209 isac->dch.rx_skb = NULL;
211 count = ReadISAC(isac, ISAC_RBCL) & 0x1f;
214 isac_empty_fifo(isac, count);
215 recv_Dchannel(&isac->dch);
220 isac_xpr_irq(struct isac_hw *isac)
222 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
223 del_timer(&isac->dch.timer);
224 if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) {
225 isac_fill_fifo(isac);
227 if (isac->dch.tx_skb)
228 dev_kfree_skb(isac->dch.tx_skb);
229 if (get_next_dframe(&isac->dch))
230 isac_fill_fifo(isac);
235 isac_retransmit(struct isac_hw *isac)
237 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
238 del_timer(&isac->dch.timer);
239 if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) {
241 isac->dch.tx_idx = 0;
242 isac_fill_fifo(isac);
243 } else if (isac->dch.tx_skb) { /* should not happen */
244 pr_info("%s: tx_skb exist but not busy\n", isac->name);
245 test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags);
246 isac->dch.tx_idx = 0;
247 isac_fill_fifo(isac);
249 pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name);
250 if (get_next_dframe(&isac->dch))
251 isac_fill_fifo(isac);
256 isac_mos_irq(struct isac_hw *isac)
261 val = ReadISAC(isac, ISAC_MOSR);
262 pr_debug("%s: ISAC MOSR %02x\n", isac->name, val);
266 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
268 pr_info("%s: ISAC MON RX out of memory!\n",
272 WriteISAC(isac, ISAC_MOCR, isac->mocr);
277 if (isac->mon_rxp >= MAX_MON_FRAME) {
280 WriteISAC(isac, ISAC_MOCR, isac->mocr);
282 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
285 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0);
286 pr_debug("%s: ISAC MOR0 %02x\n", isac->name,
287 isac->mon_rx[isac->mon_rxp - 1]);
288 if (isac->mon_rxp == 1) {
290 WriteISAC(isac, ISAC_MOCR, isac->mocr);
296 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
298 pr_info("%s: ISAC MON RX out of memory!\n",
302 WriteISAC(isac, ISAC_MOCR, isac->mocr);
307 if (isac->mon_rxp >= MAX_MON_FRAME) {
310 WriteISAC(isac, ISAC_MOCR, isac->mocr);
312 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
315 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1);
316 pr_debug("%s: ISAC MOR1 %02x\n", isac->name,
317 isac->mon_rx[isac->mon_rxp - 1]);
319 WriteISAC(isac, ISAC_MOCR, isac->mocr);
324 WriteISAC(isac, ISAC_MOCR, isac->mocr);
326 WriteISAC(isac, ISAC_MOCR, isac->mocr);
328 ret = isac->monitor(isac->dch.hw, MONITOR_RX_0,
329 isac->mon_rx, isac->mon_rxp);
333 pr_info("%s: MONITOR 0 received %d but no user\n",
334 isac->name, isac->mon_rxp);
342 WriteISAC(isac, ISAC_MOCR, isac->mocr);
344 WriteISAC(isac, ISAC_MOCR, isac->mocr);
346 ret = isac->monitor(isac->dch.hw, MONITOR_RX_1,
347 isac->mon_rx, isac->mon_rxp);
351 pr_info("%s: MONITOR 1 received %d but no user\n",
352 isac->name, isac->mon_rxp);
359 if ((!isac->mon_tx) || (isac->mon_txc &&
360 (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) {
362 WriteISAC(isac, ISAC_MOCR, isac->mocr);
364 WriteISAC(isac, ISAC_MOCR, isac->mocr);
365 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
367 isac->monitor(isac->dch.hw,
368 MONITOR_TX_0, NULL, 0);
376 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
378 isac->monitor(isac->dch.hw,
379 MONITOR_TX_0, NULL, 0);
386 WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]);
387 pr_debug("%s: ISAC %02x -> MOX0\n", isac->name,
388 isac->mon_tx[isac->mon_txp - 1]);
392 if ((!isac->mon_tx) || (isac->mon_txc &&
393 (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) {
395 WriteISAC(isac, ISAC_MOCR, isac->mocr);
397 WriteISAC(isac, ISAC_MOCR, isac->mocr);
398 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
400 isac->monitor(isac->dch.hw,
401 MONITOR_TX_1, NULL, 0);
409 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
411 isac->monitor(isac->dch.hw,
412 MONITOR_TX_1, NULL, 0);
419 WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]);
420 pr_debug("%s: ISAC %02x -> MOX1\n", isac->name,
421 isac->mon_tx[isac->mon_txp - 1]);
424 val = 0; /* dummy to avoid warning */
429 isac_cisq_irq(struct isac_hw *isac) {
432 val = ReadISAC(isac, ISAC_CIR0);
433 pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val);
435 pr_debug("%s: ph_state change %x->%x\n", isac->name,
436 isac->state, (val >> 2) & 0xf);
437 isac->state = (val >> 2) & 0xf;
438 isac_ph_state_change(isac);
441 val = ReadISAC(isac, ISAC_CIR1);
442 pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val);
447 isacsx_cic_irq(struct isac_hw *isac)
451 val = ReadISAC(isac, ISACX_CIR0);
452 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
453 if (val & ISACX_CIR0_CIC0) {
454 pr_debug("%s: ph_state change %x->%x\n", isac->name,
455 isac->state, val >> 4);
456 isac->state = val >> 4;
457 isac_ph_state_change(isac);
462 isacsx_rme_irq(struct isac_hw *isac)
467 val = ReadISAC(isac, ISACX_RSTAD);
468 if ((val & (ISACX_RSTAD_VFR |
472 != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) {
473 pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val);
474 #ifdef ERROR_STATISTIC
475 if (val & ISACX_RSTAD_CRC)
480 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
481 if (isac->dch.rx_skb)
482 dev_kfree_skb(isac->dch.rx_skb);
483 isac->dch.rx_skb = NULL;
485 count = ReadISAC(isac, ISACX_RBCLD) & 0x1f;
488 isac_empty_fifo(isac, count);
489 if (isac->dch.rx_skb) {
490 skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1);
491 pr_debug("%s: dchannel received %d\n", isac->name,
492 isac->dch.rx_skb->len);
493 recv_Dchannel(&isac->dch);
499 mISDNisac_irq(struct isac_hw *isac, u8 val)
503 pr_debug("%s: ISAC interrupt %02x\n", isac->name, val);
504 if (isac->type & IPAC_TYPE_ISACX) {
505 if (val & ISACX__CIC)
506 isacsx_cic_irq(isac);
507 if (val & ISACX__ICD) {
508 val = ReadISAC(isac, ISACX_ISTAD);
509 pr_debug("%s: ISTAD %02x\n", isac->name, val);
510 if (val & ISACX_D_XDU) {
511 pr_debug("%s: ISAC XDU\n", isac->name);
512 #ifdef ERROR_STATISTIC
515 isac_retransmit(isac);
517 if (val & ISACX_D_XMR) {
518 pr_debug("%s: ISAC XMR\n", isac->name);
519 #ifdef ERROR_STATISTIC
522 isac_retransmit(isac);
524 if (val & ISACX_D_XPR)
526 if (val & ISACX_D_RFO) {
527 pr_debug("%s: ISAC RFO\n", isac->name);
528 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
530 if (val & ISACX_D_RME)
531 isacsx_rme_irq(isac);
532 if (val & ISACX_D_RPF)
533 isac_empty_fifo(isac, 0x20);
536 if (val & 0x80) /* RME */
538 if (val & 0x40) /* RPF */
539 isac_empty_fifo(isac, 32);
540 if (val & 0x10) /* XPR */
542 if (val & 0x04) /* CISQ */
544 if (val & 0x20) /* RSC - never */
545 pr_debug("%s: ISAC RSC interrupt\n", isac->name);
546 if (val & 0x02) /* SIN - never */
547 pr_debug("%s: ISAC SIN interrupt\n", isac->name);
548 if (val & 0x01) { /* EXI */
549 val = ReadISAC(isac, ISAC_EXIR);
550 pr_debug("%s: ISAC EXIR %02x\n", isac->name, val);
551 if (val & 0x80) /* XMR */
552 pr_debug("%s: ISAC XMR\n", isac->name);
553 if (val & 0x40) { /* XDU */
554 pr_debug("%s: ISAC XDU\n", isac->name);
555 #ifdef ERROR_STATISTIC
558 isac_retransmit(isac);
560 if (val & 0x04) /* MOS */
566 EXPORT_SYMBOL(mISDNisac_irq);
569 isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb)
571 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
572 struct dchannel *dch = container_of(dev, struct dchannel, dev);
573 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
575 struct mISDNhead *hh = mISDN_HEAD_P(skb);
581 spin_lock_irqsave(isac->hwlock, flags);
582 ret = dchannel_senddata(dch, skb);
583 if (ret > 0) { /* direct TX */
584 id = hh->id; /* skb can be freed */
585 isac_fill_fifo(isac);
587 spin_unlock_irqrestore(isac->hwlock, flags);
588 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
590 spin_unlock_irqrestore(isac->hwlock, flags);
592 case PH_ACTIVATE_REQ:
593 ret = l1_event(dch->l1, hh->prim);
595 case PH_DEACTIVATE_REQ:
596 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
597 ret = l1_event(dch->l1, hh->prim);
607 isac_ctrl(struct isac_hw *isac, u32 cmd, unsigned long para)
615 spin_lock_irqsave(isac->hwlock, flags);
616 if (!(isac->type & IPAC_TYPE_ISACX)) {
617 /* TODO: implement for IPAC_TYPE_ISACX */
618 if (para & 1) /* B1 */
620 else if (para & 2) /* B2 */
622 /* we only support IOM2 mode */
623 WriteISAC(isac, ISAC_SPCR, tl);
625 WriteISAC(isac, ISAC_ADF1, 0x8);
627 WriteISAC(isac, ISAC_ADF1, 0x0);
629 spin_unlock_irqrestore(isac->hwlock, flags);
631 case HW_TIMER3_VALUE:
632 ret = l1_event(isac->dch.l1, HW_TIMER3_VALUE | (para & 0xff));
635 pr_debug("%s: %s unknown command %x %lx\n", isac->name,
636 __func__, cmd, para);
643 isac_l1cmd(struct dchannel *dch, u32 cmd)
645 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
648 pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state);
651 spin_lock_irqsave(isac->hwlock, flags);
652 ph_command(isac, ISAC_CMD_AR8);
653 spin_unlock_irqrestore(isac->hwlock, flags);
656 spin_lock_irqsave(isac->hwlock, flags);
657 ph_command(isac, ISAC_CMD_AR10);
658 spin_unlock_irqrestore(isac->hwlock, flags);
661 spin_lock_irqsave(isac->hwlock, flags);
662 if ((isac->state == ISAC_IND_EI) ||
663 (isac->state == ISAC_IND_DR) ||
664 (isac->state == ISAC_IND_DR6) ||
665 (isac->state == ISAC_IND_RS))
666 ph_command(isac, ISAC_CMD_TIM);
668 ph_command(isac, ISAC_CMD_RS);
669 spin_unlock_irqrestore(isac->hwlock, flags);
672 skb_queue_purge(&dch->squeue);
674 dev_kfree_skb(dch->tx_skb);
679 dev_kfree_skb(dch->rx_skb);
682 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
683 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
684 del_timer(&dch->timer);
687 spin_lock_irqsave(isac->hwlock, flags);
688 ph_command(isac, ISAC_CMD_TIM);
689 spin_unlock_irqrestore(isac->hwlock, flags);
691 case PH_ACTIVATE_IND:
692 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
693 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
696 case PH_DEACTIVATE_IND:
697 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
698 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
702 pr_debug("%s: %s unknown command %x\n", isac->name,
710 isac_release(struct isac_hw *isac)
712 if (isac->type & IPAC_TYPE_ISACX)
713 WriteISAC(isac, ISACX_MASK, 0xff);
715 WriteISAC(isac, ISAC_MASK, 0xff);
716 if (isac->dch.timer.function != NULL) {
717 del_timer(&isac->dch.timer);
718 isac->dch.timer.function = NULL;
725 l1_event(isac->dch.l1, CLOSE_CHANNEL);
726 mISDN_freedchannel(&isac->dch);
730 dbusy_timer_handler(struct isac_hw *isac)
735 if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
736 spin_lock_irqsave(isac->hwlock, flags);
737 rbch = ReadISAC(isac, ISAC_RBCH);
738 star = ReadISAC(isac, ISAC_STAR);
739 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
740 isac->name, rbch, star);
741 if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */
742 test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags);
744 /* discard frame; reset transceiver */
745 test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags);
746 if (isac->dch.tx_idx)
747 isac->dch.tx_idx = 0;
749 pr_info("%s: ISAC D-Channel Busy no tx_idx\n",
751 /* Transmitter reset */
752 WriteISAC(isac, ISAC_CMDR, 0x01);
754 spin_unlock_irqrestore(isac->hwlock, flags);
759 open_dchannel_caller(struct isac_hw *isac, struct channel_req *rq, void *caller)
761 pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__,
762 isac->dch.dev.id, caller);
763 if (rq->protocol != ISDN_P_TE_S0)
765 if (rq->adr.channel == 1)
766 /* E-Channel not supported */
768 rq->ch = &isac->dch.dev.D;
769 rq->ch->protocol = rq->protocol;
770 if (isac->dch.state == 7)
771 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
772 0, NULL, GFP_KERNEL);
777 open_dchannel(struct isac_hw *isac, struct channel_req *rq)
779 return open_dchannel_caller(isac, rq, __builtin_return_address(0));
782 static const char *ISACVer[] =
783 {"2086/2186 V1.1", "2085 B1", "2085 B2",
787 isac_init(struct isac_hw *isac)
793 err = create_l1(&isac->dch, isac_l1cmd);
799 setup_timer(&isac->dch.timer, (void *)dbusy_timer_handler,
802 if (isac->type & IPAC_TYPE_ISACX) {
803 /* Disable all IRQ */
804 WriteISAC(isac, ISACX_MASK, 0xff);
805 val = ReadISAC(isac, ISACX_STARD);
806 pr_debug("%s: ISACX STARD %x\n", isac->name, val);
807 val = ReadISAC(isac, ISACX_ISTAD);
808 pr_debug("%s: ISACX ISTAD %x\n", isac->name, val);
809 val = ReadISAC(isac, ISACX_ISTA);
810 pr_debug("%s: ISACX ISTA %x\n", isac->name, val);
812 WriteISAC(isac, ISACX_TR_CONF0, 0x00);
813 /* enable transmitter */
814 WriteISAC(isac, ISACX_TR_CONF2, 0x00);
815 /* transparent mode 0, RAC, stop/go */
816 WriteISAC(isac, ISACX_MODED, 0xc9);
817 /* all HDLC IRQ unmasked */
818 val = ReadISAC(isac, ISACX_ID);
819 if (isac->dch.debug & DEBUG_HW)
820 pr_notice("%s: ISACX Design ID %x\n",
821 isac->name, val & 0x3f);
822 val = ReadISAC(isac, ISACX_CIR0);
823 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
824 isac->state = val >> 4;
825 isac_ph_state_change(isac);
826 ph_command(isac, ISAC_CMD_RS);
827 WriteISAC(isac, ISACX_MASK, IPACX__ON);
828 WriteISAC(isac, ISACX_MASKD, 0x00);
829 } else { /* old isac */
830 WriteISAC(isac, ISAC_MASK, 0xff);
831 val = ReadISAC(isac, ISAC_STAR);
832 pr_debug("%s: ISAC STAR %x\n", isac->name, val);
833 val = ReadISAC(isac, ISAC_MODE);
834 pr_debug("%s: ISAC MODE %x\n", isac->name, val);
835 val = ReadISAC(isac, ISAC_ADF2);
836 pr_debug("%s: ISAC ADF2 %x\n", isac->name, val);
837 val = ReadISAC(isac, ISAC_ISTA);
838 pr_debug("%s: ISAC ISTA %x\n", isac->name, val);
840 val = ReadISAC(isac, ISAC_EXIR);
841 pr_debug("%s: ISAC EXIR %x\n", isac->name, val);
843 val = ReadISAC(isac, ISAC_RBCH);
844 if (isac->dch.debug & DEBUG_HW)
845 pr_notice("%s: ISAC version (%x): %s\n", isac->name,
846 val, ISACVer[(val >> 5) & 3]);
847 isac->type |= ((val >> 5) & 3);
850 if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */
851 pr_info("%s: only support IOM2 mode but adf2=%02x\n",
852 isac->name, isac->adf2);
856 WriteISAC(isac, ISAC_ADF2, isac->adf2);
857 WriteISAC(isac, ISAC_SQXR, 0x2f);
858 WriteISAC(isac, ISAC_SPCR, 0x00);
859 WriteISAC(isac, ISAC_STCR, 0x70);
860 WriteISAC(isac, ISAC_MODE, 0xc9);
861 WriteISAC(isac, ISAC_TIMR, 0x00);
862 WriteISAC(isac, ISAC_ADF1, 0x00);
863 val = ReadISAC(isac, ISAC_CIR0);
864 pr_debug("%s: ISAC CIR0 %x\n", isac->name, val);
865 isac->state = (val >> 2) & 0xf;
866 isac_ph_state_change(isac);
867 ph_command(isac, ISAC_CMD_RS);
868 WriteISAC(isac, ISAC_MASK, 0);
874 mISDNisac_init(struct isac_hw *isac, void *hw)
876 mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh);
878 isac->dch.dev.D.send = isac_l1hw;
879 isac->init = isac_init;
880 isac->release = isac_release;
881 isac->ctrl = isac_ctrl;
882 isac->open = open_dchannel;
883 isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
884 isac->dch.dev.nrbchan = 2;
887 EXPORT_SYMBOL(mISDNisac_init);
890 waitforCEC(struct hscx_hw *hx)
895 starb = ReadHSCX(hx, IPAC_STARB);
902 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr,
905 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr);
910 waitforXFW(struct hscx_hw *hx)
915 starb = ReadHSCX(hx, IPAC_STARB);
916 if ((starb & 0x44) == 0x40)
922 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr,
925 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr);
929 hscx_cmdr(struct hscx_hw *hx, u8 cmd)
931 if (hx->ip->type & IPAC_TYPE_IPACX)
932 WriteHSCX(hx, IPACX_CMDRB, cmd);
935 WriteHSCX(hx, IPAC_CMDRB, cmd);
940 hscx_empty_fifo(struct hscx_hw *hscx, u8 count)
945 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count);
946 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) {
947 hscx->bch.dropcnt += count;
948 hscx_cmdr(hscx, 0x80); /* RMC */
951 maxlen = bchannel_get_rxbuf(&hscx->bch, count);
953 hscx_cmdr(hscx, 0x80); /* RMC */
954 if (hscx->bch.rx_skb)
955 skb_trim(hscx->bch.rx_skb, 0);
956 pr_warning("%s.B%d: No bufferspace for %d bytes\n",
957 hscx->ip->name, hscx->bch.nr, count);
960 p = skb_put(hscx->bch.rx_skb, count);
962 if (hscx->ip->type & IPAC_TYPE_IPACX)
963 hscx->ip->read_fifo(hscx->ip->hw,
964 hscx->off + IPACX_RFIFOB, p, count);
966 hscx->ip->read_fifo(hscx->ip->hw,
967 hscx->off, p, count);
969 hscx_cmdr(hscx, 0x80); /* RMC */
971 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
972 snprintf(hscx->log, 64, "B%1d-recv %s %d ",
973 hscx->bch.nr, hscx->ip->name, count);
974 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
979 hscx_fill_fifo(struct hscx_hw *hscx)
984 if (!hscx->bch.tx_skb) {
985 if (!test_bit(FLG_TX_EMPTY, &hscx->bch.Flags))
987 count = hscx->fifo_size;
990 memset(p, hscx->bch.fill[0], count);
992 count = hscx->bch.tx_skb->len - hscx->bch.tx_idx;
995 p = hscx->bch.tx_skb->data + hscx->bch.tx_idx;
997 more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0;
998 if (count > hscx->fifo_size) {
999 count = hscx->fifo_size;
1002 pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr,
1003 count, hscx->bch.tx_idx, hscx->bch.tx_skb->len);
1004 hscx->bch.tx_idx += count;
1006 if (hscx->ip->type & IPAC_TYPE_IPACX)
1007 hscx->ip->write_fifo(hscx->ip->hw,
1008 hscx->off + IPACX_XFIFOB, p, count);
1011 hscx->ip->write_fifo(hscx->ip->hw,
1012 hscx->off, p, count);
1014 hscx_cmdr(hscx, more ? 0x08 : 0x0a);
1016 if (hscx->bch.tx_skb && (hscx->bch.debug & DEBUG_HW_BFIFO)) {
1017 snprintf(hscx->log, 64, "B%1d-send %s %d ",
1018 hscx->bch.nr, hscx->ip->name, count);
1019 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
1024 hscx_xpr(struct hscx_hw *hx)
1026 if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len) {
1030 dev_kfree_skb(hx->bch.tx_skb);
1031 if (get_next_bframe(&hx->bch)) {
1033 test_and_clear_bit(FLG_TX_EMPTY, &hx->bch.Flags);
1034 } else if (test_bit(FLG_TX_EMPTY, &hx->bch.Flags)) {
1041 ipac_rme(struct hscx_hw *hx)
1046 if (hx->ip->type & IPAC_TYPE_IPACX)
1047 rstab = ReadHSCX(hx, IPACX_RSTAB);
1049 rstab = ReadHSCX(hx, IPAC_RSTAB);
1050 pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab);
1051 if ((rstab & 0xf0) != 0xa0) {
1052 /* !(VFR && !RDO && CRC && !RAB) */
1053 if (!(rstab & 0x80)) {
1054 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1055 pr_notice("%s: B%1d invalid frame\n",
1056 hx->ip->name, hx->bch.nr);
1059 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1060 pr_notice("%s: B%1d RDO proto=%x\n",
1061 hx->ip->name, hx->bch.nr,
1064 if (!(rstab & 0x20)) {
1065 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1066 pr_notice("%s: B%1d CRC error\n",
1067 hx->ip->name, hx->bch.nr);
1069 hscx_cmdr(hx, 0x80); /* Do RMC */
1072 if (hx->ip->type & IPAC_TYPE_IPACX)
1073 count = ReadHSCX(hx, IPACX_RBCLB);
1075 count = ReadHSCX(hx, IPAC_RBCLB);
1076 count &= (hx->fifo_size - 1);
1078 count = hx->fifo_size;
1079 hscx_empty_fifo(hx, count);
1080 if (!hx->bch.rx_skb)
1082 if (hx->bch.rx_skb->len < 2) {
1083 pr_debug("%s: B%1d frame to short %d\n",
1084 hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len);
1085 skb_trim(hx->bch.rx_skb, 0);
1087 skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1);
1088 recv_Bchannel(&hx->bch, 0, false);
1093 ipac_irq(struct hscx_hw *hx, u8 ista)
1095 u8 istab, m, exirb = 0;
1097 if (hx->ip->type & IPAC_TYPE_IPACX)
1098 istab = ReadHSCX(hx, IPACX_ISTAB);
1099 else if (hx->ip->type & IPAC_TYPE_IPAC) {
1100 istab = ReadHSCX(hx, IPAC_ISTAB);
1101 m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB;
1103 exirb = ReadHSCX(hx, IPAC_EXIRB);
1104 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1107 } else if (hx->bch.nr & 2) { /* HSCX B */
1108 if (ista & (HSCX__EXA | HSCX__ICA))
1109 ipac_irq(&hx->ip->hscx[0], ista);
1110 if (ista & HSCX__EXB) {
1111 exirb = ReadHSCX(hx, IPAC_EXIRB);
1112 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1115 istab = ista & 0xF8;
1116 } else { /* HSCX A */
1117 istab = ReadHSCX(hx, IPAC_ISTAB);
1118 if (ista & HSCX__EXA) {
1119 exirb = ReadHSCX(hx, IPAC_EXIRB);
1120 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1123 istab = istab & 0xF8;
1125 if (exirb & IPAC_B_XDU)
1126 istab |= IPACX_B_XDU;
1127 if (exirb & IPAC_B_RFO)
1128 istab |= IPACX_B_RFO;
1129 pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab);
1131 if (!test_bit(FLG_ACTIVE, &hx->bch.Flags))
1134 if (istab & IPACX_B_RME)
1137 if (istab & IPACX_B_RPF) {
1138 hscx_empty_fifo(hx, hx->fifo_size);
1139 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags))
1140 recv_Bchannel(&hx->bch, 0, false);
1143 if (istab & IPACX_B_RFO) {
1144 pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr);
1145 hscx_cmdr(hx, 0x40); /* RRES */
1148 if (istab & IPACX_B_XPR)
1151 if (istab & IPACX_B_XDU) {
1152 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
1153 if (test_bit(FLG_FILLEMPTY, &hx->bch.Flags))
1154 test_and_set_bit(FLG_TX_EMPTY, &hx->bch.Flags);
1158 pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name,
1159 hx->bch.nr, hx->bch.tx_idx);
1161 hscx_cmdr(hx, 0x01); /* XRES */
1166 mISDNipac_irq(struct ipac_hw *ipac, int maxloop)
1168 int cnt = maxloop + 1;
1170 struct isac_hw *isac = &ipac->isac;
1172 if (ipac->type & IPAC_TYPE_IPACX) {
1173 ista = ReadIPAC(ipac, ISACX_ISTA);
1174 while (ista && --cnt) {
1175 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1176 if (ista & IPACX__ICA)
1177 ipac_irq(&ipac->hscx[0], ista);
1178 if (ista & IPACX__ICB)
1179 ipac_irq(&ipac->hscx[1], ista);
1180 if (ista & (ISACX__ICD | ISACX__CIC))
1181 mISDNisac_irq(&ipac->isac, ista);
1182 ista = ReadIPAC(ipac, ISACX_ISTA);
1184 } else if (ipac->type & IPAC_TYPE_IPAC) {
1185 ista = ReadIPAC(ipac, IPAC_ISTA);
1186 while (ista && --cnt) {
1187 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1188 if (ista & (IPAC__ICD | IPAC__EXD)) {
1189 istad = ReadISAC(isac, ISAC_ISTA);
1190 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1191 if (istad & IPAC_D_TIN2)
1192 pr_debug("%s TIN2 irq\n", ipac->name);
1193 if (ista & IPAC__EXD)
1194 istad |= 1; /* ISAC EXI */
1195 mISDNisac_irq(isac, istad);
1197 if (ista & (IPAC__ICA | IPAC__EXA))
1198 ipac_irq(&ipac->hscx[0], ista);
1199 if (ista & (IPAC__ICB | IPAC__EXB))
1200 ipac_irq(&ipac->hscx[1], ista);
1201 ista = ReadIPAC(ipac, IPAC_ISTA);
1203 } else if (ipac->type & IPAC_TYPE_HSCX) {
1205 ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off);
1206 pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista);
1208 ipac_irq(&ipac->hscx[1], ista);
1209 istad = ReadISAC(isac, ISAC_ISTA);
1210 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1212 mISDNisac_irq(isac, istad);
1213 if (0 == (ista | istad))
1217 if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */
1220 pr_debug("%s: %d irqloops cpu%d\n", ipac->name,
1221 maxloop - cnt, smp_processor_id());
1222 if (maxloop && !cnt)
1223 pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name,
1224 maxloop, smp_processor_id());
1227 EXPORT_SYMBOL(mISDNipac_irq);
1230 hscx_mode(struct hscx_hw *hscx, u32 bprotocol)
1232 pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name,
1233 '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr);
1234 if (hscx->ip->type & IPAC_TYPE_IPACX) {
1235 if (hscx->bch.nr & 1) { /* B1 and ICA */
1236 WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80);
1237 WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88);
1238 } else { /* B2 and ICB */
1239 WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81);
1240 WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88);
1242 switch (bprotocol) {
1243 case ISDN_P_NONE: /* init */
1244 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */
1245 WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */
1246 WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */
1247 hscx_cmdr(hscx, 0x41);
1248 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1249 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1252 WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */
1253 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */
1254 hscx_cmdr(hscx, 0x41);
1255 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1256 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1259 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */
1260 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */
1261 hscx_cmdr(hscx, 0x41);
1262 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1263 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1266 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1268 return -ENOPROTOOPT;
1270 } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */
1271 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1272 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1273 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1274 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1275 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1276 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1277 switch (bprotocol) {
1279 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1280 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1281 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1282 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1283 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1284 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1285 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1288 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1289 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1290 hscx_cmdr(hscx, 0x41);
1291 WriteHSCX(hscx, IPAC_MASKB, 0);
1292 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1295 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1296 WriteHSCX(hscx, IPAC_CCR1, 0x8a);
1297 hscx_cmdr(hscx, 0x41);
1298 WriteHSCX(hscx, IPAC_MASKB, 0);
1299 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1302 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1304 return -ENOPROTOOPT;
1306 } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */
1307 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1308 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1309 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1310 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1311 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1312 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1313 switch (bprotocol) {
1315 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1316 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1317 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1318 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1319 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1320 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1321 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1324 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1325 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1326 hscx_cmdr(hscx, 0x41);
1327 WriteHSCX(hscx, IPAC_MASKB, 0);
1328 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1331 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1332 WriteHSCX(hscx, IPAC_CCR1, 0x8d);
1333 hscx_cmdr(hscx, 0x41);
1334 WriteHSCX(hscx, IPAC_MASKB, 0);
1335 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1338 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1340 return -ENOPROTOOPT;
1344 hscx->bch.state = bprotocol;
1349 hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
1351 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1352 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1354 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1355 unsigned long flags;
1359 spin_lock_irqsave(hx->ip->hwlock, flags);
1360 ret = bchannel_senddata(bch, skb);
1361 if (ret > 0) { /* direct TX */
1365 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1367 case PH_ACTIVATE_REQ:
1368 spin_lock_irqsave(hx->ip->hwlock, flags);
1369 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1370 ret = hscx_mode(hx, ch->protocol);
1373 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1375 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1378 case PH_DEACTIVATE_REQ:
1379 spin_lock_irqsave(hx->ip->hwlock, flags);
1380 mISDN_clear_bchannel(bch);
1381 hscx_mode(hx, ISDN_P_NONE);
1382 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1383 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1388 pr_info("%s: %s unknown prim(%x,%x)\n",
1389 hx->ip->name, __func__, hh->prim, hh->id);
1398 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1400 return mISDN_ctrl_bchannel(bch, cq);
1404 hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1406 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1407 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1411 pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg);
1414 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1415 cancel_work_sync(&bch->workq);
1416 spin_lock_irqsave(hx->ip->hwlock, flags);
1417 mISDN_clear_bchannel(bch);
1418 hscx_mode(hx, ISDN_P_NONE);
1419 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1420 ch->protocol = ISDN_P_NONE;
1422 module_put(hx->ip->owner);
1425 case CONTROL_CHANNEL:
1426 ret = channel_bctrl(bch, arg);
1429 pr_info("%s: %s unknown prim(%x)\n",
1430 hx->ip->name, __func__, cmd);
1436 free_ipac(struct ipac_hw *ipac)
1438 isac_release(&ipac->isac);
1441 static const char *HSCXVer[] =
1442 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
1443 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
1448 hscx_init(struct hscx_hw *hx)
1452 WriteHSCX(hx, IPAC_RAH2, 0xFF);
1453 WriteHSCX(hx, IPAC_XBCH, 0x00);
1454 WriteHSCX(hx, IPAC_RLCR, 0x00);
1456 if (hx->ip->type & IPAC_TYPE_HSCX) {
1457 WriteHSCX(hx, IPAC_CCR1, 0x85);
1458 val = ReadHSCX(hx, HSCX_VSTR);
1459 pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val);
1460 if (hx->bch.debug & DEBUG_HW)
1461 pr_notice("%s: HSCX version %s\n", hx->ip->name,
1462 HSCXVer[val & 0x0f]);
1464 WriteHSCX(hx, IPAC_CCR1, 0x82);
1465 WriteHSCX(hx, IPAC_CCR2, 0x30);
1466 WriteHSCX(hx, IPAC_XCCR, 0x07);
1467 WriteHSCX(hx, IPAC_RCCR, 0x07);
1471 ipac_init(struct ipac_hw *ipac)
1475 if (ipac->type & IPAC_TYPE_HSCX) {
1476 hscx_init(&ipac->hscx[0]);
1477 hscx_init(&ipac->hscx[1]);
1478 val = ReadIPAC(ipac, IPAC_ID);
1479 } else if (ipac->type & IPAC_TYPE_IPAC) {
1480 hscx_init(&ipac->hscx[0]);
1481 hscx_init(&ipac->hscx[1]);
1482 WriteIPAC(ipac, IPAC_MASK, IPAC__ON);
1483 val = ReadIPAC(ipac, IPAC_CONF);
1484 /* conf is default 0, but can be overwritten by card setup */
1485 pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name,
1487 WriteIPAC(ipac, IPAC_CONF, ipac->conf);
1488 val = ReadIPAC(ipac, IPAC_ID);
1489 if (ipac->hscx[0].bch.debug & DEBUG_HW)
1490 pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val);
1492 /* nothing special for IPACX to do here */
1493 return isac_init(&ipac->isac);
1497 open_bchannel(struct ipac_hw *ipac, struct channel_req *rq)
1499 struct bchannel *bch;
1501 if (rq->adr.channel == 0 || rq->adr.channel > 2)
1503 if (rq->protocol == ISDN_P_NONE)
1505 bch = &ipac->hscx[rq->adr.channel - 1].bch;
1506 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1507 return -EBUSY; /* b-channel can be only open once */
1508 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1509 bch->ch.protocol = rq->protocol;
1515 channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq)
1520 case MISDN_CTRL_GETOP:
1521 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
1523 case MISDN_CTRL_LOOP:
1524 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
1525 if (cq->channel < 0 || cq->channel > 3) {
1529 ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel);
1531 case MISDN_CTRL_L1_TIMER3:
1532 ret = ipac->isac.ctrl(&ipac->isac, HW_TIMER3_VALUE, cq->p1);
1535 pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op);
1543 ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1545 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1546 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1547 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
1548 struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac);
1549 struct channel_req *rq;
1552 pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg);
1556 if (rq->protocol == ISDN_P_TE_S0)
1557 err = open_dchannel_caller(isac, rq, __builtin_return_address(0));
1559 err = open_bchannel(ipac, rq);
1562 if (!try_module_get(ipac->owner))
1563 pr_info("%s: cannot get module\n", ipac->name);
1566 pr_debug("%s: dev(%d) close from %p\n", ipac->name,
1567 dch->dev.id, __builtin_return_address(0));
1568 module_put(ipac->owner);
1570 case CONTROL_CHANNEL:
1571 err = channel_ctrl(ipac, arg);
1574 pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd);
1581 mISDNipac_init(struct ipac_hw *ipac, void *hw)
1587 if (ipac->isac.dch.debug & DEBUG_HW)
1588 pr_notice("%s: ipac type %x\n", ipac->name, ipac->type);
1589 if (ipac->type & IPAC_TYPE_HSCX) {
1590 ipac->isac.type = IPAC_TYPE_ISAC;
1591 ipac->hscx[0].off = 0;
1592 ipac->hscx[1].off = 0x40;
1593 ipac->hscx[0].fifo_size = 32;
1594 ipac->hscx[1].fifo_size = 32;
1595 } else if (ipac->type & IPAC_TYPE_IPAC) {
1596 ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC;
1597 ipac->hscx[0].off = 0;
1598 ipac->hscx[1].off = 0x40;
1599 ipac->hscx[0].fifo_size = 64;
1600 ipac->hscx[1].fifo_size = 64;
1601 } else if (ipac->type & IPAC_TYPE_IPACX) {
1602 ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX;
1603 ipac->hscx[0].off = IPACX_OFF_ICA;
1604 ipac->hscx[1].off = IPACX_OFF_ICB;
1605 ipac->hscx[0].fifo_size = 64;
1606 ipac->hscx[1].fifo_size = 64;
1610 mISDNisac_init(&ipac->isac, hw);
1612 ipac->isac.dch.dev.D.ctrl = ipac_dctrl;
1614 for (i = 0; i < 2; i++) {
1615 ipac->hscx[i].bch.nr = i + 1;
1616 set_channelmap(i + 1, ipac->isac.dch.dev.channelmap);
1617 list_add(&ipac->hscx[i].bch.ch.list,
1618 &ipac->isac.dch.dev.bchannels);
1619 mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM,
1620 ipac->hscx[i].fifo_size);
1621 ipac->hscx[i].bch.ch.nr = i + 1;
1622 ipac->hscx[i].bch.ch.send = &hscx_l2l1;
1623 ipac->hscx[i].bch.ch.ctrl = hscx_bctrl;
1624 ipac->hscx[i].bch.hw = hw;
1625 ipac->hscx[i].ip = ipac;
1626 /* default values for IOM time slots
1627 * can be overwritten by card */
1628 ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03;
1631 ipac->init = ipac_init;
1632 ipac->release = free_ipac;
1634 ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1635 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1638 EXPORT_SYMBOL(mISDNipac_init);
1643 pr_notice("mISDNipac module version %s\n", ISAC_REV);
1648 isac_mod_cleanup(void)
1650 pr_notice("mISDNipac module unloaded\n");
1652 module_init(isac_mod_init);
1653 module_exit(isac_mod_cleanup);