1 /*************************************************************************/
2 /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $ */
3 /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips */
4 /* The low layer (L1) is implemented as a loadable module for usage with */
5 /* the HiSax isdn driver for passive cards. */
7 /* Author: Werner Cornelius */
8 /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de) */
10 /* Driver maintained by Cologne Chip */
11 /* - Martin Bachem, support@colognechip.com */
13 /* This driver only works with chip revisions >= 1, older revision 0 */
14 /* engineering samples (only first manufacturer sample cards) will not */
15 /* work and are rejected by the driver. */
17 /* This file distributed under the GNU GPL. */
19 /* See Version History at the end of this file */
21 /*************************************************************************/
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/timer.h>
30 #include <linux/skbuff.h>
31 #include <linux/wait.h>
34 #include "hfc4s8s_l1.h"
36 static const char hfc4s8s_rev[] = "Revision: 1.10";
38 /***************************************************************/
39 /* adjustable transparent mode fifo threshold */
40 /* The value defines the used fifo threshold with the equation */
42 /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES */
44 /* The default value is 5 which results in a buffer size of 64 */
45 /* and an interrupt rate of 8ms. */
46 /* The maximum value is 7 due to fifo size restrictions. */
47 /* Values below 3-4 are not recommended due to high interrupt */
48 /* load of the processor. For non critical applications the */
49 /* value should be raised to 7 to reduce any interrupt overhead*/
50 /***************************************************************/
51 #define TRANS_FIFO_THRES 5
56 #define CLOCKMODE_0 0 /* ext. 24.576 MhZ clk freq, int. single clock mode */
57 #define CLOCKMODE_1 1 /* ext. 49.576 MhZ clk freq, int. single clock mode */
58 #define CHIP_ID_SHIFT 4
60 #define MAX_D_FRAME_SIZE 270
61 #define MAX_B_FRAME_SIZE 1536
62 #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf)
63 #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES)
64 #define MAX_F_CNT 0x0f
66 #define CLKDEL_NT 0x6c
71 #define L1_TIMER_T4 2 /* minimum in jiffies */
72 #define L1_TIMER_T3 (7 * HZ) /* activation timeout */
73 #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */
81 /* private driver_data */
89 static struct pci_device_id hfc4s8s_ids[] = {
90 {.vendor = PCI_VENDOR_ID_CCD,
91 .device = PCI_DEVICE_ID_4S,
95 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4,
96 "HFC-4S Evaluation Board"}),
98 {.vendor = PCI_VENDOR_ID_CCD,
99 .device = PCI_DEVICE_ID_8S,
103 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8,
104 "HFC-8S Evaluation Board"}),
106 {.vendor = PCI_VENDOR_ID_CCD,
107 .device = PCI_DEVICE_ID_4S,
111 (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4,
114 {.vendor = PCI_VENDOR_ID_CCD,
115 .device = PCI_DEVICE_ID_8S,
119 (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8,
125 MODULE_DEVICE_TABLE(pci, hfc4s8s_ids);
127 MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de");
128 MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips");
129 MODULE_LICENSE("GPL");
134 struct hfc4s8s_btype {
136 struct hisax_b_if b_if;
137 struct hfc4s8s_l1 *l1p;
138 struct sk_buff_head tx_queue;
139 struct sk_buff *tx_skb;
140 struct sk_buff *rx_skb;
151 struct _hfc4s8s_hw *hw; /* pointer to hardware area */
152 int l1_state; /* actual l1 state */
153 struct timer_list l1_timer; /* layer 1 timer structure */
154 int nt_mode; /* set to nt mode */
155 int st_num; /* own index */
156 int enabled; /* interface is enabled */
157 struct sk_buff_head d_tx_queue; /* send queue */
158 int tx_cnt; /* bytes to send */
159 struct hisax_d_if d_if; /* D-channel interface */
160 struct hfc4s8s_btype b_ch[2]; /* B-channel data */
161 struct hisax_b_if *b_table[2];
164 /**********************/
165 /* hardware structure */
166 /**********************/
167 typedef struct _hfc4s8s_hw {
178 hfc4s8s_param driver_data;
181 struct work_struct tqueue;
182 struct hfc4s8s_l1 l1[HFC_MAX_ST];
187 volatile u_char r_irq_statech; /* active isdn l1 status */
188 u_char r_irqmsk_statchg; /* enabled isdn status ints */
189 u_char r_irq_fifo_blx[8]; /* fifo status registers */
190 u_char fifo_rx_trans_enables[8]; /* mask for enabled transparent rx fifos */
191 u_char fifo_slow_timer_service[8]; /* mask for fifos needing slower timer service */
192 volatile u_char r_irq_oview; /* contents of overview register */
193 volatile u_char timer_irq;
194 int timer_usg_cnt; /* number of channels using timer */
200 /* inline functions io mapped */
202 SetRegAddr(hfc4s8s_hw *a, u_char b)
204 outb(b, (a->iobase) + 4);
208 GetRegAddr(hfc4s8s_hw *a)
210 return (inb((volatile u_int) (a->iobase + 4)));
215 Write_hfc8(hfc4s8s_hw *a, u_char b, u_char c)
222 fWrite_hfc8(hfc4s8s_hw *a, u_char c)
228 fWrite_hfc32(hfc4s8s_hw *a, u_long c)
234 Read_hfc8(hfc4s8s_hw *a, u_char b)
237 return (inb((volatile u_int) a->iobase));
241 fRead_hfc8(hfc4s8s_hw *a)
243 return (inb((volatile u_int) a->iobase));
247 static inline u_short
248 Read_hfc16(hfc4s8s_hw *a, u_char b)
251 return (inw((volatile u_int) a->iobase));
255 fRead_hfc32(hfc4s8s_hw *a)
257 return (inl((volatile u_int) a->iobase));
261 wait_busy(hfc4s8s_hw *a)
263 SetRegAddr(a, R_STATUS);
264 while (inb((volatile u_int) a->iobase) & M_BUSY);
267 #define PCI_ENA_REGIO 0x01
269 /******************************************************/
270 /* function to read critical counter registers that */
271 /* may be updated by the chip during read */
272 /******************************************************/
274 Read_hfc8_stable(hfc4s8s_hw *hw, int reg)
278 ref8 = Read_hfc8(hw, reg);
279 while (((in8 = Read_hfc8(hw, reg)) != ref8)) {
286 Read_hfc16_stable(hfc4s8s_hw *hw, int reg)
291 ref16 = Read_hfc16(hw, reg);
292 while (((in16 = Read_hfc16(hw, reg)) != ref16)) {
298 /*****************************/
299 /* D-channel call from HiSax */
300 /*****************************/
302 dch_l2l1(struct hisax_d_if *iface, int pr, void *arg)
304 struct hfc4s8s_l1 *l1 = iface->ifc.priv;
305 struct sk_buff *skb = (struct sk_buff *) arg;
310 case (PH_DATA | REQUEST):
315 spin_lock_irqsave(&l1->lock, flags);
316 skb_queue_tail(&l1->d_tx_queue, skb);
317 if ((skb_queue_len(&l1->d_tx_queue) == 1) &&
319 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
321 spin_unlock_irqrestore(&l1->lock, flags);
322 schedule_work(&l1->hw->tqueue);
324 spin_unlock_irqrestore(&l1->lock, flags);
327 case (PH_ACTIVATE | REQUEST):
331 if (l1->l1_state < 6) {
332 spin_lock_irqsave(&l1->lock,
335 Write_hfc8(l1->hw, R_ST_SEL,
337 Write_hfc8(l1->hw, A_ST_WR_STA,
339 mod_timer(&l1->l1_timer,
340 jiffies + L1_TIMER_T3);
341 spin_unlock_irqrestore(&l1->lock,
343 } else if (l1->l1_state == 7)
344 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
349 if (l1->l1_state != 3) {
350 spin_lock_irqsave(&l1->lock,
352 Write_hfc8(l1->hw, R_ST_SEL,
354 Write_hfc8(l1->hw, A_ST_WR_STA,
356 spin_unlock_irqrestore(&l1->lock,
358 } else if (l1->l1_state == 3)
359 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
368 "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
373 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
374 PH_DEACTIVATE | INDICATION, NULL);
377 /*****************************/
378 /* B-channel call from HiSax */
379 /*****************************/
381 bch_l2l1(struct hisax_if *ifc, int pr, void *arg)
383 struct hfc4s8s_btype *bch = ifc->priv;
384 struct hfc4s8s_l1 *l1 = bch->l1p;
385 struct sk_buff *skb = (struct sk_buff *) arg;
386 long mode = (long) arg;
391 case (PH_DATA | REQUEST):
392 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) {
396 spin_lock_irqsave(&l1->lock, flags);
397 skb_queue_tail(&bch->tx_queue, skb);
398 if (!bch->tx_skb && (bch->tx_cnt <= 0)) {
399 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
400 ((bch->bchan == 1) ? 1 : 4);
401 spin_unlock_irqrestore(&l1->lock, flags);
402 schedule_work(&l1->hw->tqueue);
404 spin_unlock_irqrestore(&l1->lock, flags);
407 case (PH_ACTIVATE | REQUEST):
408 case (PH_DEACTIVATE | REQUEST):
411 if (pr == (PH_DEACTIVATE | REQUEST))
416 spin_lock_irqsave(&l1->lock,
418 l1->hw->mr.timer_usg_cnt++;
420 fifo_slow_timer_service[l1->
425 Write_hfc8(l1->hw, R_FIFO,
430 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */
431 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
432 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */
433 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
436 Write_hfc8(l1->hw, R_FIFO,
441 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */
442 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
443 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */
444 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
446 Write_hfc8(l1->hw, R_ST_SEL,
448 l1->hw->mr.r_ctrl0 |=
450 Write_hfc8(l1->hw, A_ST_CTRL0,
452 bch->mode = L1_MODE_HDLC;
453 spin_unlock_irqrestore(&l1->lock,
456 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
463 spin_lock_irqsave(&l1->lock,
466 fifo_rx_trans_enables[l1->
471 l1->hw->mr.timer_usg_cnt++;
472 Write_hfc8(l1->hw, R_FIFO,
477 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */
478 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
479 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */
480 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
483 Write_hfc8(l1->hw, R_FIFO,
488 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */
489 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
490 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */
491 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
493 Write_hfc8(l1->hw, R_ST_SEL,
495 l1->hw->mr.r_ctrl0 |=
497 Write_hfc8(l1->hw, A_ST_CTRL0,
499 bch->mode = L1_MODE_TRANS;
500 spin_unlock_irqrestore(&l1->lock,
503 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
510 if (bch->mode == L1_MODE_NULL)
512 spin_lock_irqsave(&l1->lock,
515 fifo_slow_timer_service[l1->
521 fifo_rx_trans_enables[l1->
526 l1->hw->mr.timer_usg_cnt--;
527 Write_hfc8(l1->hw, R_FIFO,
532 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */
534 Write_hfc8(l1->hw, R_FIFO,
539 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */
540 Write_hfc8(l1->hw, R_ST_SEL,
542 l1->hw->mr.r_ctrl0 &=
544 Write_hfc8(l1->hw, A_ST_CTRL0,
546 spin_unlock_irqrestore(&l1->lock,
549 bch->mode = L1_MODE_NULL;
550 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
555 dev_kfree_skb(bch->tx_skb);
559 dev_kfree_skb(bch->rx_skb);
562 skb_queue_purge(&bch->tx_queue);
568 /* timer is only used when at least one b channel */
569 /* is set up to transparent mode */
570 if (l1->hw->mr.timer_usg_cnt) {
571 Write_hfc8(l1->hw, R_IRQMSK_MISC,
574 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
581 "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
586 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
587 PH_DEACTIVATE | INDICATION, NULL);
590 /**************************/
591 /* layer 1 timer function */
592 /**************************/
594 hfc_l1_timer(struct hfc4s8s_l1 *l1)
601 spin_lock_irqsave(&l1->lock, flags);
604 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
605 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11);
606 spin_unlock_irqrestore(&l1->lock, flags);
607 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
608 PH_DEACTIVATE | INDICATION, NULL);
609 spin_lock_irqsave(&l1->lock, flags);
611 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1);
612 spin_unlock_irqrestore(&l1->lock, flags);
614 /* activation timed out */
615 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
616 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13);
617 spin_unlock_irqrestore(&l1->lock, flags);
618 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
619 PH_DEACTIVATE | INDICATION, NULL);
620 spin_lock_irqsave(&l1->lock, flags);
621 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
622 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3);
623 spin_unlock_irqrestore(&l1->lock, flags);
627 /****************************************/
628 /* a complete D-frame has been received */
629 /****************************************/
631 rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
643 Write_hfc8(l1p->hw, R_FIFO,
644 (l1p->st_num * 8 + ((ech) ? 7 : 5)));
647 f1 = Read_hfc8_stable(l1p->hw, A_F1);
648 f2 = Read_hfc8(l1p->hw, A_F2);
651 df = f1 - f2 + MAX_F_CNT + 1;
655 return; /* no complete frame in fifo */
658 z1 = Read_hfc16_stable(l1p->hw, A_Z1);
659 z2 = Read_hfc16(l1p->hw, A_Z2);
665 if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) {
667 "HFC-4S/8S: Could not allocate D/E "
668 "channel receive buffer");
669 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
674 if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) {
677 /* remove errornous D frame */
680 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
684 /* read errornous D frame */
685 SetRegAddr(l1p->hw, A_FIFO_DATA0);
688 fRead_hfc32(l1p->hw);
695 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);
703 SetRegAddr(l1p->hw, A_FIFO_DATA0);
706 *((unsigned long *) cp) = fRead_hfc32(l1p->hw);
712 *cp++ = fRead_hfc8(l1p->hw);
714 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
720 skb->len = (cp - skb->data) - 2;
722 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
723 PH_DATA_E | INDICATION,
726 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
727 PH_DATA | INDICATION,
733 /*************************************************************/
734 /* a B-frame has been received (perhaps not fully completed) */
735 /*************************************************************/
737 rx_b_frame(struct hfc4s8s_btype *bch)
739 int z1, z2, hdlc_complete;
741 struct hfc4s8s_l1 *l1 = bch->l1p;
744 if (!l1->enabled || (bch->mode == L1_MODE_NULL))
749 Write_hfc8(l1->hw, R_FIFO,
750 (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3)));
753 if (bch->mode == L1_MODE_HDLC) {
754 f1 = Read_hfc8_stable(l1->hw, A_F1);
755 f2 = Read_hfc8(l1->hw, A_F2);
756 hdlc_complete = ((f1 ^ f2) & MAX_F_CNT);
759 z1 = Read_hfc16_stable(l1->hw, A_Z1);
760 z2 = Read_hfc16(l1->hw, A_Z2);
770 if (!(skb = bch->rx_skb)) {
773 dev_alloc_skb((bch->mode ==
775 : (MAX_B_FRAME_SIZE + 3)))) {
777 "HFC-4S/8S: Could not allocate B "
778 "channel receive buffer");
781 bch->rx_ptr = skb->data;
785 skb->len = (bch->rx_ptr - skb->data) + z1;
787 /* HDLC length check */
788 if ((bch->mode == L1_MODE_HDLC) &&
789 ((hdlc_complete && (skb->len < 4)) ||
790 (skb->len > (MAX_B_FRAME_SIZE + 3)))) {
793 bch->rx_ptr = skb->data;
794 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
798 SetRegAddr(l1->hw, A_FIFO_DATA0);
801 *((unsigned long *) bch->rx_ptr) =
808 *(bch->rx_ptr++) = fRead_hfc8(l1->hw);
811 /* increment f counter */
812 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
819 bch->rx_ptr = skb->data;
824 if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) {
827 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
828 PH_DATA | INDICATION, skb);
834 /********************************************/
835 /* a D-frame has been/should be transmitted */
836 /********************************************/
838 tx_d_frame(struct hfc4s8s_l1 *l1p)
845 if (l1p->l1_state != 7)
849 Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4));
852 f1 = Read_hfc8(l1p->hw, A_F1);
853 f2 = Read_hfc8_stable(l1p->hw, A_F2);
855 if ((f1 ^ f2) & MAX_F_CNT)
856 return; /* fifo is still filled */
858 if (l1p->tx_cnt > 0) {
861 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM,
865 if ((skb = skb_dequeue(&l1p->d_tx_queue))) {
868 SetRegAddr(l1p->hw, A_FIFO_DATA0);
871 SetRegAddr(l1p->hw, A_FIFO_DATA0);
872 fWrite_hfc32(l1p->hw, *(unsigned long *) cp);
878 fWrite_hfc8(l1p->hw, *cp++);
880 l1p->tx_cnt = skb->truesize;
881 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
888 /******************************************************/
889 /* a B-frame may be transmitted (or is not completed) */
890 /******************************************************/
892 tx_b_frame(struct hfc4s8s_btype *bch)
895 struct hfc4s8s_l1 *l1 = bch->l1p;
897 int cnt, max, hdlc_num;
900 if (!l1->enabled || (bch->mode == L1_MODE_NULL))
904 Write_hfc8(l1->hw, R_FIFO,
905 (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2)));
909 if (bch->mode == L1_MODE_HDLC) {
910 hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT;
912 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
916 break; /* fifo still filled up with hdlc frames */
920 if (!(skb = bch->tx_skb)) {
921 if (!(skb = skb_dequeue(&bch->tx_queue))) {
922 l1->hw->mr.fifo_slow_timer_service[l1->
924 &= ~((bch->bchan == 1) ? 1 : 4);
925 break; /* list empty */
932 l1->hw->mr.fifo_slow_timer_service[l1->st_num] |=
933 ((bch->bchan == 1) ? 1 : 4);
935 l1->hw->mr.fifo_slow_timer_service[l1->st_num] &=
936 ~((bch->bchan == 1) ? 1 : 4);
938 max = Read_hfc16_stable(l1->hw, A_Z2);
939 max -= Read_hfc16(l1->hw, A_Z1);
945 break; /* don't write to small amounts of bytes */
947 cnt = skb->len - bch->tx_cnt;
950 cp = skb->data + bch->tx_cnt;
953 SetRegAddr(l1->hw, A_FIFO_DATA0);
955 fWrite_hfc32(l1->hw, *(unsigned long *) cp);
961 fWrite_hfc8(l1->hw, *cp++);
963 if (bch->tx_cnt >= skb->len) {
964 if (bch->mode == L1_MODE_HDLC) {
965 /* increment f counter */
966 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
968 ack_len += skb->truesize;
974 Write_hfc8(l1->hw, R_FIFO,
976 ((bch->bchan == 1) ? 0 : 2)));
981 bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if,
982 PH_DATA | CONFIRM, (void *) ack_len);
985 /*************************************/
986 /* bottom half handler for interrupt */
987 /*************************************/
989 hfc4s8s_bh(struct work_struct *work)
991 hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue);
993 struct hfc4s8s_l1 *l1p;
994 volatile u_char *fifo_stat;
997 /* handle layer 1 state changes */
1001 if ((b & hw->mr.r_irq_statech)) {
1002 /* reset l1 event */
1003 hw->mr.r_irq_statech &= ~b;
1006 u_char oldstate = l1p->l1_state;
1008 Write_hfc8(l1p->hw, R_ST_SEL,
1015 && (l1p->l1_state != 3))
1016 l1p->d_if.ifc.l1l2(&l1p->
1024 if (l1p->l1_state != 2) {
1025 del_timer(&l1p->l1_timer);
1026 if (l1p->l1_state == 3) {
1036 /* allow transition */
1037 Write_hfc8(hw, A_ST_WR_STA,
1039 mod_timer(&l1p->l1_timer,
1044 "HFC-4S/8S: NT ch %d l1 state %d -> %d\n",
1045 l1p->st_num, oldstate,
1048 u_char oldstate = l1p->l1_state;
1050 Write_hfc8(l1p->hw, R_ST_SEL,
1056 if (((l1p->l1_state == 3) &&
1058 (oldstate == 8))) ||
1061 && (l1p->l1_state == 8))) {
1062 mod_timer(&l1p->l1_timer,
1066 if (l1p->l1_state == 7) {
1078 if (l1p->l1_state == 3) {
1093 "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n",
1095 l1p->st_num, oldstate,
1104 /* now handle the fifos */
1106 fifo_stat = hw->mr.r_irq_fifo_blx;
1108 while (idx < hw->driver_data.max_st_ports) {
1110 if (hw->mr.timer_irq) {
1111 *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx];
1112 if (hw->fifo_sched_cnt <= 0) {
1114 hw->mr.fifo_slow_timer_service[l1p->
1118 /* ignore fifo 6 (TX E fifo) */
1119 *fifo_stat &= 0xff - 0x40;
1121 while (*fifo_stat) {
1123 if (!l1p->nt_mode) {
1124 /* RX Fifo has data to read */
1125 if ((*fifo_stat & 0x20)) {
1126 *fifo_stat &= ~0x20;
1129 /* E Fifo has data to read */
1130 if ((*fifo_stat & 0x80)) {
1131 *fifo_stat &= ~0x80;
1134 /* TX Fifo completed send */
1135 if ((*fifo_stat & 0x10)) {
1136 *fifo_stat &= ~0x10;
1140 /* B1 RX Fifo has data to read */
1141 if ((*fifo_stat & 0x2)) {
1143 rx_b_frame(l1p->b_ch);
1145 /* B1 TX Fifo has send completed */
1146 if ((*fifo_stat & 0x1)) {
1148 tx_b_frame(l1p->b_ch);
1150 /* B2 RX Fifo has data to read */
1151 if ((*fifo_stat & 0x8)) {
1153 rx_b_frame(l1p->b_ch + 1);
1155 /* B2 TX Fifo has send completed */
1156 if ((*fifo_stat & 0x4)) {
1158 tx_b_frame(l1p->b_ch + 1);
1166 if (hw->fifo_sched_cnt <= 0)
1167 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE));
1168 hw->mr.timer_irq = 0; /* clear requested timer irq */
1171 /*********************/
1172 /* interrupt handler */
1173 /*********************/
1175 hfc4s8s_interrupt(int intno, void *dev_id)
1177 hfc4s8s_hw *hw = dev_id;
1179 volatile u_char *ovp;
1183 if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN))
1186 /* read current selected regsister */
1187 old_ioreg = GetRegAddr(hw);
1189 /* Layer 1 State change */
1190 hw->mr.r_irq_statech |=
1191 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
1193 (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA)))
1194 && !hw->mr.r_irq_statech) {
1195 SetRegAddr(hw, old_ioreg);
1200 if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) {
1201 hw->mr.timer_irq = 1;
1202 hw->fifo_sched_cnt--;
1206 if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) {
1207 hw->mr.r_irq_oview |= ovr;
1208 idx = R_IRQ_FIFO_BL0;
1209 ovp = hw->mr.r_irq_fifo_blx;
1212 *ovp |= Read_hfc8(hw, idx);
1220 /* queue the request to allow other cards to interrupt */
1221 schedule_work(&hw->tqueue);
1223 SetRegAddr(hw, old_ioreg);
1225 } /* hfc4s8s_interrupt */
1227 /***********************************************************************/
1228 /* reset the complete chip, don't release the chips irq but disable it */
1229 /***********************************************************************/
1231 chipreset(hfc4s8s_hw *hw)
1235 spin_lock_irqsave(&hw->lock, flags);
1236 Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */
1237 Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */
1238 Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */
1239 Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */
1240 hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */
1241 spin_unlock_irqrestore(&hw->lock, flags);
1244 Write_hfc8(hw, R_CIRM, 0); /* disable reset */
1247 Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */
1248 Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */
1249 if (hw->driver_data.clock_mode == 1)
1250 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */
1251 Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */
1253 memset(&hw->mr, 0, sizeof(hw->mr));
1256 /********************************************/
1257 /* disable/enable hardware in nt or te mode */
1258 /********************************************/
1260 hfc_hardware_enable(hfc4s8s_hw *hw, int enable, int nt_mode)
1267 /* save system vars */
1268 hw->nt_mode = nt_mode;
1270 /* enable fifo and state irqs, but not global irq enable */
1271 hw->mr.r_irq_ctrl = M_FIFO_IRQ;
1272 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1273 hw->mr.r_irqmsk_statchg = 0;
1274 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1275 Write_hfc8(hw, R_PWM_MD, 0x80);
1276 Write_hfc8(hw, R_PWM1, 26);
1278 Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC);
1280 /* enable the line interfaces and fifos */
1281 for (i = 0; i < hw->driver_data.max_st_ports; i++) {
1282 hw->mr.r_irqmsk_statchg |= (1 << i);
1283 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1284 Write_hfc8(hw, R_ST_SEL, i);
1285 Write_hfc8(hw, A_ST_CLK_DLY,
1286 ((nt_mode) ? CLKDEL_NT : CLKDEL_TE));
1287 hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE);
1288 Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0);
1289 Write_hfc8(hw, A_ST_CTRL2, 3);
1290 Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */
1292 hw->l1[i].enabled = 1;
1293 hw->l1[i].nt_mode = nt_mode;
1297 Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */
1299 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1300 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1301 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1302 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1305 /* setup D RX-fifo */
1306 Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */
1308 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1309 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1310 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1311 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1314 /* setup D TX-fifo */
1315 Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */
1317 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1318 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1319 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1320 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1324 sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i);
1327 (&hw->l1[i].d_if, hw->l1[i].b_table, if_name,
1328 ((nt_mode) ? 3 : 2))) {
1330 hw->l1[i].enabled = 0;
1331 hw->mr.r_irqmsk_statchg &= ~(1 << i);
1332 Write_hfc8(hw, R_SCI_MSK,
1333 hw->mr.r_irqmsk_statchg);
1335 "HFC-4S/8S: Unable to register S/T device %s, break\n",
1340 spin_lock_irqsave(&hw->lock, flags);
1341 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN;
1342 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1343 spin_unlock_irqrestore(&hw->lock, flags);
1345 /* disable hardware */
1346 spin_lock_irqsave(&hw->lock, flags);
1347 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN;
1348 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1349 spin_unlock_irqrestore(&hw->lock, flags);
1351 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) {
1352 hw->l1[i].enabled = 0;
1353 hisax_unregister(&hw->l1[i].d_if);
1354 del_timer(&hw->l1[i].l1_timer);
1355 skb_queue_purge(&hw->l1[i].d_tx_queue);
1356 skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue);
1357 skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue);
1361 } /* hfc_hardware_enable */
1363 /******************************************/
1364 /* disable memory mapped ports / io ports */
1365 /******************************************/
1367 release_pci_ports(hfc4s8s_hw *hw)
1369 pci_write_config_word(hw->pdev, PCI_COMMAND, 0);
1371 release_region(hw->iobase, 8);
1374 /*****************************************/
1375 /* enable memory mapped ports / io ports */
1376 /*****************************************/
1378 enable_pci_ports(hfc4s8s_hw *hw)
1380 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO);
1383 /*************************************/
1384 /* initialise the HFC-4s/8s hardware */
1385 /* return 0 on success. */
1386 /*************************************/
1388 setup_instance(hfc4s8s_hw *hw)
1393 for (i = 0; i < HFC_MAX_ST; i++) {
1394 struct hfc4s8s_l1 *l1p;
1397 spin_lock_init(&l1p->lock);
1399 l1p->l1_timer.function = (void *) hfc_l1_timer;
1400 l1p->l1_timer.data = (long) (l1p);
1401 init_timer(&l1p->l1_timer);
1403 skb_queue_head_init(&l1p->d_tx_queue);
1404 l1p->d_if.ifc.priv = hw->l1 + i;
1405 l1p->d_if.ifc.l2l1 = (void *) dch_l2l1;
1407 spin_lock_init(&l1p->b_ch[0].lock);
1408 l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1;
1409 l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0];
1410 l1p->b_ch[0].l1p = hw->l1 + i;
1411 l1p->b_ch[0].bchan = 1;
1412 l1p->b_table[0] = &l1p->b_ch[0].b_if;
1413 skb_queue_head_init(&l1p->b_ch[0].tx_queue);
1415 spin_lock_init(&l1p->b_ch[1].lock);
1416 l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1;
1417 l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1];
1418 l1p->b_ch[1].l1p = hw->l1 + i;
1419 l1p->b_ch[1].bchan = 2;
1420 l1p->b_table[1] = &l1p->b_ch[1].b_if;
1421 skb_queue_head_init(&l1p->b_ch[1].tx_queue);
1424 enable_pci_ports(hw);
1427 i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT;
1428 if (i != hw->driver_data.chip_id) {
1430 "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n",
1431 i, hw->driver_data.chip_id);
1435 i = Read_hfc8(hw, R_CHIP_RV) & 0xf;
1438 "HFC-4S/8S: chip revision 0 not supported, card ignored\n");
1442 INIT_WORK(&hw->tqueue, hfc4s8s_bh);
1445 (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) {
1447 "HFC-4S/8S: unable to alloc irq %d, card ignored\n",
1452 "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n",
1453 hw->iobase, hw->irq);
1455 hfc_hardware_enable(hw, 1, 0);
1461 release_pci_ports(hw);
1466 /*****************************************/
1467 /* PCI hotplug interface: probe new card */
1468 /*****************************************/
1470 hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1473 hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data;
1476 if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) {
1477 printk(KERN_ERR "No kmem for HFC-4S/8S card\n");
1482 err = pci_enable_device(pdev);
1487 hw->cardnum = card_cnt;
1488 sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum);
1489 printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n",
1490 driver_data->device_name, hw->card_name, pci_name(pdev));
1492 spin_lock_init(&hw->lock);
1494 hw->driver_data = *driver_data;
1495 hw->irq = pdev->irq;
1496 hw->iobase = pci_resource_start(pdev, 0);
1498 if (!request_region(hw->iobase, 8, hw->card_name)) {
1500 "HFC-4S/8S: failed to request address space at 0x%04x\n",
1505 pci_set_drvdata(pdev, hw);
1506 err = setup_instance(hw);
1516 /**************************************/
1517 /* PCI hotplug interface: remove card */
1518 /**************************************/
1520 hfc4s8s_remove(struct pci_dev *pdev)
1522 hfc4s8s_hw *hw = pci_get_drvdata(pdev);
1524 printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum);
1525 hfc_hardware_enable(hw, 0, 0);
1528 free_irq(hw->irq, hw);
1530 release_pci_ports(hw);
1533 pci_disable_device(pdev);
1538 static struct pci_driver hfc4s8s_driver = {
1539 .name = "hfc4s8s_l1",
1540 .probe = hfc4s8s_probe,
1541 .remove = hfc4s8s_remove,
1542 .id_table = hfc4s8s_ids,
1545 /**********************/
1546 /* driver Module init */
1547 /**********************/
1549 hfc4s8s_module_init(void)
1554 "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n",
1557 "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n");
1561 err = pci_register_driver(&hfc4s8s_driver);
1565 printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt);
1570 } /* hfc4s8s_init_hw */
1572 /*************************************/
1573 /* driver module exit : */
1574 /* release the HFC-4s/8s hardware */
1575 /*************************************/
1577 hfc4s8s_module_exit(void)
1579 pci_unregister_driver(&hfc4s8s_driver);
1580 printk(KERN_INFO "HFC-4S/8S: module removed\n");
1581 } /* hfc4s8s_release_hw */
1583 module_init(hfc4s8s_module_init);
1584 module_exit(hfc4s8s_module_exit);