drivers/media/dvb/frontends/cxd2820r_core.c

   1 /*
   2  * Sony CXD2820R demodulator driver
   3  *
   4  * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2 of the License, or
   9  *    (at your option) any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License along
  17  *    with this program; if not, write to the Free Software Foundation, Inc.,
  18  *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21
  22 #include "cxd2820r_priv.h"
  23
  24 int cxd2820r_debug;
  25 module_param_named(debug, cxd2820r_debug, int, 0644);
  26 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  27
  28 /* write multiple registers */
  29 static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
  30         u8 *val, int len)
  31 {
  32         int ret;
  33         u8 buf[len+1];
  34         struct i2c_msg msg[1] = {
  35                 {
  36                         .addr = i2c,
  37                         .flags = 0,
  38                         .len = sizeof(buf),
  39                         .buf = buf,
  40                 }
  41         };
  42
  43         buf[0] = reg;
  44         memcpy(&buf[1], val, len);
  45
  46         ret = i2c_transfer(priv->i2c, msg, 1);
  47         if (ret == 1) {
  48                 ret = 0;
  49         } else {
  50                 warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len);
  51                 ret = -EREMOTEIO;
  52         }
  53         return ret;
  54 }
  55
  56 /* read multiple registers */
  57 static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
  58         u8 *val, int len)
  59 {
  60         int ret;
  61         u8 buf[len];
  62         struct i2c_msg msg[2] = {
  63                 {
  64                         .addr = i2c,
  65                         .flags = 0,
  66                         .len = 1,
  67                         .buf = &reg,
  68                 }, {
  69                         .addr = i2c,
  70                         .flags = I2C_M_RD,
  71                         .len = sizeof(buf),
  72                         .buf = buf,
  73                 }
  74         };
  75
  76         ret = i2c_transfer(priv->i2c, msg, 2);
  77         if (ret == 2) {
  78                 memcpy(val, buf, len);
  79                 ret = 0;
  80         } else {
  81                 warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len);
  82                 ret = -EREMOTEIO;
  83         }
  84
  85         return ret;
  86 }
  87
  88 /* write multiple registers */
  89 int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
  90         int len)
  91 {
  92         int ret;
  93         u8 i2c_addr;
  94         u8 reg = (reginfo >> 0) & 0xff;
  95         u8 bank = (reginfo >> 8) & 0xff;
  96         u8 i2c = (reginfo >> 16) & 0x01;
  97
  98         /* select I2C */
  99         if (i2c)
 100                 i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
 101         else
 102                 i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
 103
 104         /* switch bank if needed */
 105         if (bank != priv->bank[i2c]) {
 106                 ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
 107                 if (ret)
 108                         return ret;
 109                 priv->bank[i2c] = bank;
 110         }
 111         return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len);
 112 }
 113
 114 /* read multiple registers */
 115 int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
 116         int len)
 117 {
 118         int ret;
 119         u8 i2c_addr;
 120         u8 reg = (reginfo >> 0) & 0xff;
 121         u8 bank = (reginfo >> 8) & 0xff;
 122         u8 i2c = (reginfo >> 16) & 0x01;
 123
 124         /* select I2C */
 125         if (i2c)
 126                 i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
 127         else
 128                 i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
 129
 130         /* switch bank if needed */
 131         if (bank != priv->bank[i2c]) {
 132                 ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
 133                 if (ret)
 134                         return ret;
 135                 priv->bank[i2c] = bank;
 136         }
 137         return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len);
 138 }
 139
 140 /* write single register */
 141 int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val)
 142 {
 143         return cxd2820r_wr_regs(priv, reg, &val, 1);
 144 }
 145
 146 /* read single register */
 147 int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val)
 148 {
 149         return cxd2820r_rd_regs(priv, reg, val, 1);
 150 }
 151
 152 /* write single register with mask */
 153 int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val,
 154         u8 mask)
 155 {
 156         int ret;
 157         u8 tmp;
 158
 159         /* no need for read if whole reg is written */
 160         if (mask != 0xff) {
 161                 ret = cxd2820r_rd_reg(priv, reg, &tmp);
 162                 if (ret)
 163                         return ret;
 164
 165                 val &= mask;
 166                 tmp &= ~mask;
 167                 val |= tmp;
 168         }
 169
 170         return cxd2820r_wr_reg(priv, reg, val);
 171 }
 172
 173 int cxd2820r_gpio(struct dvb_frontend *fe)
 174 {
 175         struct cxd2820r_priv *priv = fe->demodulator_priv;
 176         int ret, i;
 177         u8 *gpio, tmp0, tmp1;
 178         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 179
 180         switch (fe->dtv_property_cache.delivery_system) {
 181         case SYS_DVBT:
 182                 gpio = priv->cfg.gpio_dvbt;
 183                 break;
 184         case SYS_DVBT2:
 185                 gpio = priv->cfg.gpio_dvbt2;
 186                 break;
 187         case SYS_DVBC_ANNEX_AC:
 188                 gpio = priv->cfg.gpio_dvbc;
 189                 break;
 190         default:
 191                 ret = -EINVAL;
 192                 goto error;
 193         }
 194
 195         /* update GPIOs only when needed */
 196         if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio)))
 197                 return 0;
 198
 199         tmp0 = 0x00;
 200         tmp1 = 0x00;
 201         for (i = 0; i < sizeof(priv->gpio); i++) {
 202                 /* enable / disable */
 203                 if (gpio[i] & CXD2820R_GPIO_E)
 204                         tmp0 |= (2 << 6) >> (2 * i);
 205                 else
 206                         tmp0 |= (1 << 6) >> (2 * i);
 207
 208                 /* input / output */
 209                 if (gpio[i] & CXD2820R_GPIO_I)
 210                         tmp1 |= (1 << (3 + i));
 211                 else
 212                         tmp1 |= (0 << (3 + i));
 213
 214                 /* high / low */
 215                 if (gpio[i] & CXD2820R_GPIO_H)
 216                         tmp1 |= (1 << (0 + i));
 217                 else
 218                         tmp1 |= (0 << (0 + i));
 219
 220                 dbg("%s: GPIO i=%d %02x %02x", __func__, i, tmp0, tmp1);
 221         }
 222
 223         dbg("%s: wr gpio=%02x %02x", __func__, tmp0, tmp1);
 224
 225         /* write bits [7:2] */
 226         ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc);
 227         if (ret)
 228                 goto error;
 229
 230         /* write bits [5:0] */
 231         ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f);
 232         if (ret)
 233                 goto error;
 234
 235         memcpy(priv->gpio, gpio, sizeof(priv->gpio));
 236
 237         return ret;
 238 error:
 239         dbg("%s: failed:%d", __func__, ret);
 240         return ret;
 241 }
 242
 243 /* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */
 244 u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor)
 245 {
 246         return div_u64(dividend + (divisor / 2), divisor);
 247 }
 248
 249 static int cxd2820r_set_frontend(struct dvb_frontend *fe)
 250 {
 251         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 252         int ret;
 253
 254         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 255         switch (c->delivery_system) {
 256         case SYS_DVBT:
 257                 ret = cxd2820r_init_t(fe);
 258                 if (ret < 0)
 259                         goto err;
 260                 ret = cxd2820r_set_frontend_t(fe);
 261                 if (ret < 0)
 262                         goto err;
 263                 break;
 264         case SYS_DVBT2:
 265                 ret = cxd2820r_init_t(fe);
 266                 if (ret < 0)
 267                         goto err;
 268                 ret = cxd2820r_set_frontend_t2(fe);
 269                 if (ret < 0)
 270                         goto err;
 271                 break;
 272         case SYS_DVBC_ANNEX_A:
 273                 ret = cxd2820r_init_c(fe);
 274                 if (ret < 0)
 275                         goto err;
 276                 ret = cxd2820r_set_frontend_c(fe);
 277                 if (ret < 0)
 278                         goto err;
 279                 break;
 280         default:
 281                 dbg("%s: error state=%d", __func__, fe->dtv_property_cache.delivery_system);
 282                 ret = -EINVAL;
 283                 break;
 284         }
 285 err:
 286         return ret;
 287 }
 288 static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status)
 289 {
 290         int ret;
 291
 292         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 293         switch (fe->dtv_property_cache.delivery_system) {
 294         case SYS_DVBT:
 295                 ret = cxd2820r_read_status_t(fe, status);
 296                 break;
 297         case SYS_DVBT2:
 298                 ret = cxd2820r_read_status_t2(fe, status);
 299                 break;
 300         case SYS_DVBC_ANNEX_A:
 301                 ret = cxd2820r_read_status_c(fe, status);
 302                 break;
 303         default:
 304                 ret = -EINVAL;
 305                 break;
 306         }
 307         return ret;
 308 }
 309
 310 static int cxd2820r_get_frontend(struct dvb_frontend *fe,
 311                                  struct dtv_frontend_properties *c)
 312 {
 313         int ret;
 314
 315         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 316         switch (fe->dtv_property_cache.delivery_system) {
 317         case SYS_DVBT:
 318                 ret = cxd2820r_get_frontend_t(fe);
 319                 break;
 320         case SYS_DVBT2:
 321                 ret = cxd2820r_get_frontend_t2(fe);
 322                 break;
 323         case SYS_DVBC_ANNEX_A:
 324                 ret = cxd2820r_get_frontend_c(fe);
 325                 break;
 326         default:
 327                 ret = -EINVAL;
 328                 break;
 329         }
 330         return ret;
 331 }
 332
 333 static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber)
 334 {
 335         int ret;
 336
 337         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 338         switch (fe->dtv_property_cache.delivery_system) {
 339         case SYS_DVBT:
 340                 ret = cxd2820r_read_ber_t(fe, ber);
 341                 break;
 342         case SYS_DVBT2:
 343                 ret = cxd2820r_read_ber_t2(fe, ber);
 344                 break;
 345         case SYS_DVBC_ANNEX_A:
 346                 ret = cxd2820r_read_ber_c(fe, ber);
 347                 break;
 348         default:
 349                 ret = -EINVAL;
 350                 break;
 351         }
 352         return ret;
 353 }
 354
 355 static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
 356 {
 357         int ret;
 358
 359         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 360         switch (fe->dtv_property_cache.delivery_system) {
 361         case SYS_DVBT:
 362                 ret = cxd2820r_read_signal_strength_t(fe, strength);
 363                 break;
 364         case SYS_DVBT2:
 365                 ret = cxd2820r_read_signal_strength_t2(fe, strength);
 366                 break;
 367         case SYS_DVBC_ANNEX_A:
 368                 ret = cxd2820r_read_signal_strength_c(fe, strength);
 369                 break;
 370         default:
 371                 ret = -EINVAL;
 372                 break;
 373         }
 374         return ret;
 375 }
 376
 377 static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr)
 378 {
 379         int ret;
 380
 381         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 382         switch (fe->dtv_property_cache.delivery_system) {
 383         case SYS_DVBT:
 384                 ret = cxd2820r_read_snr_t(fe, snr);
 385                 break;
 386         case SYS_DVBT2:
 387                 ret = cxd2820r_read_snr_t2(fe, snr);
 388                 break;
 389         case SYS_DVBC_ANNEX_A:
 390                 ret = cxd2820r_read_snr_c(fe, snr);
 391                 break;
 392         default:
 393                 ret = -EINVAL;
 394                 break;
 395         }
 396         return ret;
 397 }
 398
 399 static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 400 {
 401         int ret;
 402
 403         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 404         switch (fe->dtv_property_cache.delivery_system) {
 405         case SYS_DVBT:
 406                 ret = cxd2820r_read_ucblocks_t(fe, ucblocks);
 407                 break;
 408         case SYS_DVBT2:
 409                 ret = cxd2820r_read_ucblocks_t2(fe, ucblocks);
 410                 break;
 411         case SYS_DVBC_ANNEX_A:
 412                 ret = cxd2820r_read_ucblocks_c(fe, ucblocks);
 413                 break;
 414         default:
 415                 ret = -EINVAL;
 416                 break;
 417         }
 418         return ret;
 419 }
 420
 421 static int cxd2820r_init(struct dvb_frontend *fe)
 422 {
 423         return 0;
 424 }
 425
 426 static int cxd2820r_sleep(struct dvb_frontend *fe)
 427 {
 428         int ret;
 429
 430         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 431         switch (fe->dtv_property_cache.delivery_system) {
 432         case SYS_DVBT:
 433                 ret = cxd2820r_sleep_t(fe);
 434                 break;
 435         case SYS_DVBT2:
 436                 ret = cxd2820r_sleep_t2(fe);
 437                 break;
 438         case SYS_DVBC_ANNEX_A:
 439                 ret = cxd2820r_sleep_c(fe);
 440                 break;
 441         default:
 442                 ret = -EINVAL;
 443                 break;
 444         }
 445         return ret;
 446 }
 447
 448 static int cxd2820r_get_tune_settings(struct dvb_frontend *fe,
 449                                       struct dvb_frontend_tune_settings *s)
 450 {
 451         int ret;
 452
 453         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 454         switch (fe->dtv_property_cache.delivery_system) {
 455         case SYS_DVBT:
 456                 ret = cxd2820r_get_tune_settings_t(fe, s);
 457                 break;
 458         case SYS_DVBT2:
 459                 ret = cxd2820r_get_tune_settings_t2(fe, s);
 460                 break;
 461         case SYS_DVBC_ANNEX_A:
 462                 ret = cxd2820r_get_tune_settings_c(fe, s);
 463                 break;
 464         default:
 465                 ret = -EINVAL;
 466                 break;
 467         }
 468         return ret;
 469 }
 470
 471 static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe,
 472                                          struct dvb_frontend_parameters *p)
 473 {
 474         struct cxd2820r_priv *priv = fe->demodulator_priv;
 475         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 476         int ret, i;
 477         fe_status_t status = 0;
 478         dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
 479
 480         /* switch between DVB-T and DVB-T2 when tune fails */
 481         if (priv->last_tune_failed && (priv->delivery_system != SYS_DVBC_ANNEX_A)) {
 482                 if (priv->delivery_system == SYS_DVBT)
 483                         c->delivery_system = SYS_DVBT2;
 484                 else
 485                         c->delivery_system = SYS_DVBT;
 486         }
 487
 488         /* set frontend */
 489         ret = cxd2820r_set_frontend(fe);
 490         if (ret)
 491                 goto error;
 492
 493
 494         /* frontend lock wait loop count */
 495         switch (priv->delivery_system) {
 496         case SYS_DVBT:
 497                 i = 20;
 498                 break;
 499         case SYS_DVBT2:
 500                 i = 40;
 501                 break;
 502         case SYS_UNDEFINED:
 503         default:
 504                 i = 0;
 505                 break;
 506         }
 507
 508         /* wait frontend lock */
 509         for (; i > 0; i--) {
 510                 dbg("%s: LOOP=%d", __func__, i);
 511                 msleep(50);
 512                 ret = cxd2820r_read_status(fe, &status);
 513                 if (ret)
 514                         goto error;
 515
 516                 if (status & FE_HAS_SIGNAL)
 517                         break;
 518         }
 519
 520         /* check if we have a valid signal */
 521         if (status) {
 522                 priv->last_tune_failed = 0;
 523                 return DVBFE_ALGO_SEARCH_SUCCESS;
 524         } else {
 525                 priv->last_tune_failed = 1;
 526                 return DVBFE_ALGO_SEARCH_AGAIN;
 527         }
 528
 529 error:
 530         dbg("%s: failed:%d", __func__, ret);
 531         return DVBFE_ALGO_SEARCH_ERROR;
 532 }
 533
 534 static int cxd2820r_get_frontend_algo(struct dvb_frontend *fe)
 535 {
 536         return DVBFE_ALGO_CUSTOM;
 537 }
 538
 539 static void cxd2820r_release(struct dvb_frontend *fe)
 540 {
 541         struct cxd2820r_priv *priv = fe->demodulator_priv;
 542         dbg("%s", __func__);
 543
 544         kfree(priv);
 545         return;
 546 }
 547
 548 static int cxd2820r_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 549 {
 550         struct cxd2820r_priv *priv = fe->demodulator_priv;
 551         dbg("%s: %d", __func__, enable);
 552
 553         /* Bit 0 of reg 0xdb in bank 0x00 controls I2C repeater */
 554         return cxd2820r_wr_reg_mask(priv, 0xdb, enable ? 1 : 0, 0x1);
 555 }
 556
 557 static const struct dvb_frontend_ops cxd2820r_ops = {
 558         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
 559
 560         /* default: DVB-T/T2 */
 561         .info = {
 562                 .name = "Sony CXD2820R (DVB-T/T2)",
 563                 .type = FE_OFDM,
 564
 565                 .caps = FE_CAN_FEC_1_2                  |
 566                         FE_CAN_FEC_2_3                  |
 567                         FE_CAN_FEC_3_4                  |
 568                         FE_CAN_FEC_5_6                  |
 569                         FE_CAN_FEC_7_8                  |
 570                         FE_CAN_FEC_AUTO                 |
 571                         FE_CAN_QPSK                     |
 572                         FE_CAN_QAM_16                   |
 573                         FE_CAN_QAM_64                   |
 574                         FE_CAN_QAM_256                  |
 575                         FE_CAN_QAM_AUTO                 |
 576                         FE_CAN_TRANSMISSION_MODE_AUTO   |
 577                         FE_CAN_GUARD_INTERVAL_AUTO      |
 578                         FE_CAN_HIERARCHY_AUTO           |
 579                         FE_CAN_MUTE_TS                  |
 580                         FE_CAN_2G_MODULATION
 581                 },
 582
 583         .release                = cxd2820r_release,
 584         .init                   = cxd2820r_init,
 585         .sleep                  = cxd2820r_sleep,
 586
 587         .get_tune_settings      = cxd2820r_get_tune_settings,
 588         .i2c_gate_ctrl          = cxd2820r_i2c_gate_ctrl,
 589
 590         .get_frontend           = cxd2820r_get_frontend,
 591
 592         .get_frontend_algo      = cxd2820r_get_frontend_algo,
 593         .search                 = cxd2820r_search,
 594
 595         .read_status            = cxd2820r_read_status,
 596         .read_snr               = cxd2820r_read_snr,
 597         .read_ber               = cxd2820r_read_ber,
 598         .read_ucblocks          = cxd2820r_read_ucblocks,
 599         .read_signal_strength   = cxd2820r_read_signal_strength,
 600 };
 601
 602 struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg,
 603                                      struct i2c_adapter *i2c,
 604                                      struct dvb_frontend *fe)
 605 {
 606         struct cxd2820r_priv *priv = NULL;
 607         int ret;
 608         u8 tmp;
 609
 610         priv = kzalloc(sizeof (struct cxd2820r_priv), GFP_KERNEL);
 611         if (!priv)
 612                 goto error;
 613
 614         priv->i2c = i2c;
 615         memcpy(&priv->cfg, cfg, sizeof (struct cxd2820r_config));
 616
 617         priv->bank[0] = priv->bank[1] = 0xff;
 618         ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp);
 619         dbg("%s: chip id=%02x", __func__, tmp);
 620         if (ret || tmp != 0xe1)
 621                 goto error;
 622
 623         memcpy(&priv->fe.ops, &cxd2820r_ops, sizeof (struct dvb_frontend_ops));
 624         priv->fe.demodulator_priv = priv;
 625         return &priv->fe;
 626 error:
 627         kfree(priv);
 628         return NULL;
 629 }
 630 EXPORT_SYMBOL(cxd2820r_attach);
 631
 632 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
 633 MODULE_DESCRIPTION("Sony CXD2820R demodulator driver");
 634 MODULE_LICENSE("GPL");