2 * Coda multi-standard codec IP - BIT processor functions
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
7 * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/clk.h>
16 #include <linux/irqreturn.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
23 #include <media/v4l2-common.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-fh.h>
26 #include <media/v4l2-mem2mem.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
29 #include <media/videobuf2-vmalloc.h>
33 #define CODA7_PS_BUF_SIZE 0x28000
34 #define CODA9_PS_SAVE_SIZE (512 * 1024)
36 #define CODA_DEFAULT_GAMMA 4096
37 #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
39 static inline int coda_is_initialized(struct coda_dev *dev)
41 return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
44 static inline unsigned long coda_isbusy(struct coda_dev *dev)
46 return coda_read(dev, CODA_REG_BIT_BUSY);
49 static int coda_wait_timeout(struct coda_dev *dev)
51 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
53 while (coda_isbusy(dev)) {
54 if (time_after(jiffies, timeout))
60 static void coda_command_async(struct coda_ctx *ctx, int cmd)
62 struct coda_dev *dev = ctx->dev;
64 if (dev->devtype->product == CODA_960 ||
65 dev->devtype->product == CODA_7541) {
66 /* Restore context related registers to CODA */
67 coda_write(dev, ctx->bit_stream_param,
68 CODA_REG_BIT_BIT_STREAM_PARAM);
69 coda_write(dev, ctx->frm_dis_flg,
70 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
71 coda_write(dev, ctx->frame_mem_ctrl,
72 CODA_REG_BIT_FRAME_MEM_CTRL);
73 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
76 if (dev->devtype->product == CODA_960) {
77 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
78 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
81 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
83 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
84 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
85 coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
87 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
90 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
92 struct coda_dev *dev = ctx->dev;
94 coda_command_async(ctx, cmd);
95 return coda_wait_timeout(dev);
98 int coda_hw_reset(struct coda_ctx *ctx)
100 struct coda_dev *dev = ctx->dev;
101 unsigned long timeout;
108 idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
110 if (dev->devtype->product == CODA_960) {
111 timeout = jiffies + msecs_to_jiffies(100);
112 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
113 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
114 if (time_after(jiffies, timeout))
120 ret = reset_control_reset(dev->rstc);
124 if (dev->devtype->product == CODA_960)
125 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
126 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
127 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
128 ret = coda_wait_timeout(dev);
129 coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
134 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
136 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
137 struct coda_dev *dev = ctx->dev;
140 rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
141 kfifo->out = (kfifo->in & ~kfifo->mask) |
142 (rd_ptr - ctx->bitstream.paddr);
143 if (kfifo->out > kfifo->in)
144 kfifo->out -= kfifo->mask + 1;
147 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
149 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
150 struct coda_dev *dev = ctx->dev;
153 rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
154 coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
155 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
156 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
159 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
161 struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
162 struct coda_dev *dev = ctx->dev;
165 wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
166 coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
169 static int coda_bitstream_queue(struct coda_ctx *ctx,
170 struct vb2_buffer *src_buf)
172 u32 src_size = vb2_get_plane_payload(src_buf, 0);
175 n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
180 dma_sync_single_for_device(&ctx->dev->plat_dev->dev,
181 ctx->bitstream.paddr, ctx->bitstream.size,
184 src_buf->v4l2_buf.sequence = ctx->qsequence++;
189 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
190 struct vb2_buffer *src_buf)
194 if (coda_get_bitstream_payload(ctx) +
195 vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
198 if (vb2_plane_vaddr(src_buf, 0) == NULL) {
199 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
203 ret = coda_bitstream_queue(ctx, src_buf);
205 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
208 /* Sync read pointer to device */
209 if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
210 coda_kfifo_sync_to_device_write(ctx);
217 void coda_fill_bitstream(struct coda_ctx *ctx)
219 struct vb2_buffer *src_buf;
220 struct coda_buffer_meta *meta;
223 while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
225 * Only queue a single JPEG into the bitstream buffer, except
226 * to increase payload over 512 bytes or if in hold state.
228 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
229 (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
232 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
234 /* Drop frames that do not start/end with a SOI/EOI markers */
235 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
236 !coda_jpeg_check_buffer(ctx, src_buf)) {
237 v4l2_err(&ctx->dev->v4l2_dev,
238 "dropping invalid JPEG frame\n");
239 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
240 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
244 /* Buffer start position */
245 start = ctx->bitstream_fifo.kfifo.in &
246 ctx->bitstream_fifo.kfifo.mask;
248 if (coda_bitstream_try_queue(ctx, src_buf)) {
250 * Source buffer is queued in the bitstream ringbuffer;
251 * queue the timestamp and mark source buffer as done
253 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
255 meta = kmalloc(sizeof(*meta), GFP_KERNEL);
257 meta->sequence = src_buf->v4l2_buf.sequence;
258 meta->timecode = src_buf->v4l2_buf.timecode;
259 meta->timestamp = src_buf->v4l2_buf.timestamp;
261 meta->end = ctx->bitstream_fifo.kfifo.in &
262 ctx->bitstream_fifo.kfifo.mask;
263 list_add_tail(&meta->list,
264 &ctx->buffer_meta_list);
267 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
274 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
276 struct coda_dev *dev = ctx->dev;
278 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
280 /* If this context is currently running, update the hardware flag */
281 if ((dev->devtype->product == CODA_960) &&
283 (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
284 coda_write(dev, ctx->bit_stream_param,
285 CODA_REG_BIT_BIT_STREAM_PARAM);
289 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
291 struct coda_dev *dev = ctx->dev;
292 u32 *p = ctx->parabuf.vaddr;
294 if (dev->devtype->product == CODA_DX6)
297 p[index ^ 1] = value;
300 static void coda_free_framebuffers(struct coda_ctx *ctx)
304 for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
305 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
308 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
309 struct coda_q_data *q_data, u32 fourcc)
311 struct coda_dev *dev = ctx->dev;
318 if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
319 ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
320 width = round_up(q_data->width, 16);
321 height = round_up(q_data->height, 16);
323 width = round_up(q_data->width, 8);
324 height = q_data->height;
326 ysize = width * height;
328 /* Allocate frame buffers */
329 for (i = 0; i < ctx->num_internal_frames; i++) {
333 size = ysize + ysize / 2;
334 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
335 dev->devtype->product != CODA_DX6)
337 name = kasprintf(GFP_KERNEL, "fb%d", i);
338 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
342 coda_free_framebuffers(ctx);
347 /* Register frame buffers in the parameter buffer */
348 for (i = 0; i < ctx->num_internal_frames; i++) {
349 paddr = ctx->internal_frames[i].paddr;
350 /* Start addresses of Y, Cb, Cr planes */
351 coda_parabuf_write(ctx, i * 3 + 0, paddr);
352 coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize);
353 coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize / 4);
355 /* mvcol buffer for h.264 */
356 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
357 dev->devtype->product != CODA_DX6)
358 coda_parabuf_write(ctx, 96 + i,
359 ctx->internal_frames[i].paddr +
360 ysize + ysize/4 + ysize/4);
363 /* mvcol buffer for mpeg4 */
364 if ((dev->devtype->product != CODA_DX6) &&
365 (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
366 coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
367 ysize + ysize/4 + ysize/4);
372 static void coda_free_context_buffers(struct coda_ctx *ctx)
374 struct coda_dev *dev = ctx->dev;
376 coda_free_aux_buf(dev, &ctx->slicebuf);
377 coda_free_aux_buf(dev, &ctx->psbuf);
378 if (dev->devtype->product != CODA_DX6)
379 coda_free_aux_buf(dev, &ctx->workbuf);
382 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
383 struct coda_q_data *q_data)
385 struct coda_dev *dev = ctx->dev;
389 if (dev->devtype->product == CODA_DX6)
392 if (ctx->psbuf.vaddr) {
393 v4l2_err(&dev->v4l2_dev, "psmembuf still allocated\n");
396 if (ctx->slicebuf.vaddr) {
397 v4l2_err(&dev->v4l2_dev, "slicebuf still allocated\n");
400 if (ctx->workbuf.vaddr) {
401 v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
406 if (q_data->fourcc == V4L2_PIX_FMT_H264) {
407 /* worst case slice size */
408 size = (DIV_ROUND_UP(q_data->width, 16) *
409 DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
410 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
413 v4l2_err(&dev->v4l2_dev,
414 "failed to allocate %d byte slice buffer",
420 if (dev->devtype->product == CODA_7541) {
421 ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
422 CODA7_PS_BUF_SIZE, "psbuf");
424 v4l2_err(&dev->v4l2_dev,
425 "failed to allocate psmem buffer");
430 size = dev->devtype->workbuf_size;
431 if (dev->devtype->product == CODA_960 &&
432 q_data->fourcc == V4L2_PIX_FMT_H264)
433 size += CODA9_PS_SAVE_SIZE;
434 ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size, "workbuf");
436 v4l2_err(&dev->v4l2_dev,
437 "failed to allocate %d byte context buffer",
445 coda_free_context_buffers(ctx);
449 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
450 int header_code, u8 *header, int *size)
452 struct coda_dev *dev = ctx->dev;
457 if (dev->devtype->product == CODA_960)
458 memset(vb2_plane_vaddr(buf, 0), 0, 64);
460 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
461 CODA_CMD_ENC_HEADER_BB_START);
462 bufsize = vb2_plane_size(buf, 0);
463 if (dev->devtype->product == CODA_960)
465 coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
466 coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
467 ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
469 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
473 if (dev->devtype->product == CODA_960) {
474 for (i = 63; i > 0; i--)
475 if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
479 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
480 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
482 memcpy(header, vb2_plane_vaddr(buf, 0), *size);
487 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
491 size = round_up(size, 1024);
492 if (size > iram->remaining)
494 iram->remaining -= size;
496 ret = iram->next_paddr;
497 iram->next_paddr += size;
502 static void coda_setup_iram(struct coda_ctx *ctx)
504 struct coda_iram_info *iram_info = &ctx->iram_info;
505 struct coda_dev *dev = ctx->dev;
512 memset(iram_info, 0, sizeof(*iram_info));
513 iram_info->next_paddr = dev->iram.paddr;
514 iram_info->remaining = dev->iram.size;
516 if (!dev->iram.vaddr)
519 switch (dev->devtype->product) {
521 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
522 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
523 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
526 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
527 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
528 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
530 default: /* CODA_DX6 */
534 if (ctx->inst_type == CODA_INST_ENCODER) {
535 struct coda_q_data *q_data_src;
537 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
538 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
539 w128 = mb_width * 128;
542 /* Prioritize in case IRAM is too small for everything */
543 if (dev->devtype->product == CODA_7541) {
544 iram_info->search_ram_size = round_up(mb_width * 16 *
546 iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
547 iram_info->search_ram_size);
548 if (!iram_info->search_ram_paddr) {
549 pr_err("IRAM is smaller than the search ram size\n");
552 iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
556 /* Only H.264BP and H.263P3 are considered */
557 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
558 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
559 if (!iram_info->buf_dbk_c_use)
561 iram_info->axi_sram_use |= dbk_bits;
563 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
564 if (!iram_info->buf_bit_use)
566 iram_info->axi_sram_use |= bit_bits;
568 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
569 if (!iram_info->buf_ip_ac_dc_use)
571 iram_info->axi_sram_use |= ip_bits;
573 /* OVL and BTP disabled for encoder */
574 } else if (ctx->inst_type == CODA_INST_DECODER) {
575 struct coda_q_data *q_data_dst;
577 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
578 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
579 w128 = mb_width * 128;
581 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
582 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
583 if (!iram_info->buf_dbk_c_use)
585 iram_info->axi_sram_use |= dbk_bits;
587 iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
588 if (!iram_info->buf_bit_use)
590 iram_info->axi_sram_use |= bit_bits;
592 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
593 if (!iram_info->buf_ip_ac_dc_use)
595 iram_info->axi_sram_use |= ip_bits;
597 /* OVL and BTP unused as there is no VC1 support yet */
601 if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
602 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
603 "IRAM smaller than needed\n");
605 if (dev->devtype->product == CODA_7541) {
606 /* TODO - Enabling these causes picture errors on CODA7541 */
607 if (ctx->inst_type == CODA_INST_DECODER) {
609 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
610 CODA7_USE_IP_ENABLE);
613 iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
614 CODA7_USE_HOST_DBK_ENABLE |
615 CODA7_USE_IP_ENABLE |
616 CODA7_USE_DBK_ENABLE);
621 static u32 coda_supported_firmwares[] = {
622 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
623 CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
624 CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
627 static bool coda_firmware_supported(u32 vernum)
631 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
632 if (vernum == coda_supported_firmwares[i])
637 int coda_check_firmware(struct coda_dev *dev)
639 u16 product, major, minor, release;
643 ret = clk_prepare_enable(dev->clk_per);
647 ret = clk_prepare_enable(dev->clk_ahb);
651 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
652 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
653 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
654 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
655 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
656 if (coda_wait_timeout(dev)) {
657 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
662 if (dev->devtype->product == CODA_960) {
663 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
664 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
668 /* Check we are compatible with the loaded firmware */
669 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
670 product = CODA_FIRMWARE_PRODUCT(data);
671 major = CODA_FIRMWARE_MAJOR(data);
672 minor = CODA_FIRMWARE_MINOR(data);
673 release = CODA_FIRMWARE_RELEASE(data);
675 clk_disable_unprepare(dev->clk_per);
676 clk_disable_unprepare(dev->clk_ahb);
678 if (product != dev->devtype->product) {
679 v4l2_err(&dev->v4l2_dev,
680 "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
681 coda_product_name(dev->devtype->product),
682 coda_product_name(product), major, minor, release);
686 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
687 coda_product_name(product));
689 if (coda_firmware_supported(data)) {
690 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
691 major, minor, release);
693 v4l2_warn(&dev->v4l2_dev,
694 "Unsupported firmware version: %u.%u.%u\n",
695 major, minor, release);
701 clk_disable_unprepare(dev->clk_ahb);
703 clk_disable_unprepare(dev->clk_per);
709 * Encoder context operations
712 static int coda_start_encoding(struct coda_ctx *ctx)
714 struct coda_dev *dev = ctx->dev;
715 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
716 struct coda_q_data *q_data_src, *q_data_dst;
717 u32 bitstream_buf, bitstream_size;
718 struct vb2_buffer *buf;
719 int gamma, ret, value;
723 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
724 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
725 dst_fourcc = q_data_dst->fourcc;
727 /* Allocate per-instance buffers */
728 ret = coda_alloc_context_buffers(ctx, q_data_src);
732 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
733 bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
734 bitstream_size = q_data_dst->sizeimage;
736 if (!coda_is_initialized(dev)) {
737 v4l2_err(v4l2_dev, "coda is not initialized.\n");
741 if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
742 if (!ctx->params.jpeg_qmat_tab[0])
743 ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
744 if (!ctx->params.jpeg_qmat_tab[1])
745 ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
746 coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
749 mutex_lock(&dev->coda_mutex);
751 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
752 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
753 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
754 switch (dev->devtype->product) {
756 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
757 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
760 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
763 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
764 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
768 ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
769 if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
770 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
771 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
773 if (dev->devtype->product == CODA_DX6) {
774 /* Configure the coda */
775 coda_write(dev, dev->iram.paddr,
776 CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
779 /* Could set rotation here if needed */
781 switch (dev->devtype->product) {
783 value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
784 << CODADX6_PICWIDTH_OFFSET;
785 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
786 << CODA_PICHEIGHT_OFFSET;
789 if (dst_fourcc == V4L2_PIX_FMT_H264) {
790 value = (round_up(q_data_src->width, 16) &
791 CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
792 value |= (round_up(q_data_src->height, 16) &
793 CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
798 value = (q_data_src->width & CODA7_PICWIDTH_MASK)
799 << CODA7_PICWIDTH_OFFSET;
800 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
801 << CODA_PICHEIGHT_OFFSET;
803 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
804 if (dst_fourcc == V4L2_PIX_FMT_JPEG)
805 ctx->params.framerate = 0;
806 coda_write(dev, ctx->params.framerate,
807 CODA_CMD_ENC_SEQ_SRC_F_RATE);
809 ctx->params.codec_mode = ctx->codec->mode;
810 switch (dst_fourcc) {
811 case V4L2_PIX_FMT_MPEG4:
812 if (dev->devtype->product == CODA_960)
813 coda_write(dev, CODA9_STD_MPEG4,
814 CODA_CMD_ENC_SEQ_COD_STD);
816 coda_write(dev, CODA_STD_MPEG4,
817 CODA_CMD_ENC_SEQ_COD_STD);
818 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
820 case V4L2_PIX_FMT_H264:
821 if (dev->devtype->product == CODA_960)
822 coda_write(dev, CODA9_STD_H264,
823 CODA_CMD_ENC_SEQ_COD_STD);
825 coda_write(dev, CODA_STD_H264,
826 CODA_CMD_ENC_SEQ_COD_STD);
827 if (ctx->params.h264_deblk_enabled) {
828 value = ((ctx->params.h264_deblk_alpha &
829 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
830 CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
831 ((ctx->params.h264_deblk_beta &
832 CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
833 CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
835 value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
837 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
839 case V4L2_PIX_FMT_JPEG:
840 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
841 coda_write(dev, ctx->params.jpeg_restart_interval,
842 CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
843 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
844 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
845 coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
847 coda_jpeg_write_tables(ctx);
851 "dst format (0x%08x) invalid.\n", dst_fourcc);
857 * slice mode and GOP size registers are used for thumb size/offset
860 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
861 switch (ctx->params.slice_mode) {
862 case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
865 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
866 value = (ctx->params.slice_max_mb &
867 CODA_SLICING_SIZE_MASK)
868 << CODA_SLICING_SIZE_OFFSET;
869 value |= (1 & CODA_SLICING_UNIT_MASK)
870 << CODA_SLICING_UNIT_OFFSET;
871 value |= 1 & CODA_SLICING_MODE_MASK;
873 case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
874 value = (ctx->params.slice_max_bits &
875 CODA_SLICING_SIZE_MASK)
876 << CODA_SLICING_SIZE_OFFSET;
877 value |= (0 & CODA_SLICING_UNIT_MASK)
878 << CODA_SLICING_UNIT_OFFSET;
879 value |= 1 & CODA_SLICING_MODE_MASK;
882 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
883 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
884 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
887 if (ctx->params.bitrate) {
888 /* Rate control enabled */
889 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
890 << CODA_RATECONTROL_BITRATE_OFFSET;
891 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
892 if (dev->devtype->product == CODA_960)
893 value |= BIT(31); /* disable autoskip */
897 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
899 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
900 coda_write(dev, ctx->params.intra_refresh,
901 CODA_CMD_ENC_SEQ_INTRA_REFRESH);
903 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
904 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
908 if (dev->devtype->product == CODA_960)
909 gamma = CODA9_DEFAULT_GAMMA;
911 gamma = CODA_DEFAULT_GAMMA;
913 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
914 CODA_CMD_ENC_SEQ_RC_GAMMA);
917 if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
919 ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
920 ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
921 CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
923 if (dev->devtype->product == CODA_960) {
924 if (ctx->params.h264_max_qp)
925 value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
926 if (CODA_DEFAULT_GAMMA > 0)
927 value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
929 if (CODA_DEFAULT_GAMMA > 0) {
930 if (dev->devtype->product == CODA_DX6)
931 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
933 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
935 if (ctx->params.h264_min_qp)
936 value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
937 if (ctx->params.h264_max_qp)
938 value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
940 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
942 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
944 coda_setup_iram(ctx);
946 if (dst_fourcc == V4L2_PIX_FMT_H264) {
947 switch (dev->devtype->product) {
949 value = FMO_SLICE_SAVE_BUF_SIZE << 7;
950 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
953 coda_write(dev, ctx->iram_info.search_ram_paddr,
954 CODA7_CMD_ENC_SEQ_SEARCH_BASE);
955 coda_write(dev, ctx->iram_info.search_ram_size,
956 CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
959 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
960 coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
964 ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
966 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
970 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
971 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
976 if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
977 if (dev->devtype->product == CODA_960)
978 ctx->num_internal_frames = 4;
980 ctx->num_internal_frames = 2;
981 ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
983 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
986 stride = q_data_src->bytesperline;
988 ctx->num_internal_frames = 0;
991 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
992 coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
994 if (dev->devtype->product == CODA_7541) {
995 coda_write(dev, q_data_src->bytesperline,
996 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
998 if (dev->devtype->product != CODA_DX6) {
999 coda_write(dev, ctx->iram_info.buf_bit_use,
1000 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1001 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1002 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1003 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1004 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1005 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1006 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1007 coda_write(dev, ctx->iram_info.buf_ovl_use,
1008 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1009 if (dev->devtype->product == CODA_960) {
1010 coda_write(dev, ctx->iram_info.buf_btp_use,
1011 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1014 coda_write(dev, ctx->internal_frames[2].paddr,
1015 CODA9_CMD_SET_FRAME_SUBSAMP_A);
1016 coda_write(dev, ctx->internal_frames[3].paddr,
1017 CODA9_CMD_SET_FRAME_SUBSAMP_B);
1021 ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1023 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1027 /* Save stream headers */
1028 buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1029 switch (dst_fourcc) {
1030 case V4L2_PIX_FMT_H264:
1032 * Get SPS in the first frame and copy it to an
1033 * intermediate buffer.
1035 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1036 &ctx->vpu_header[0][0],
1037 &ctx->vpu_header_size[0]);
1042 * Get PPS in the first frame and copy it to an
1043 * intermediate buffer.
1045 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1046 &ctx->vpu_header[1][0],
1047 &ctx->vpu_header_size[1]);
1052 * Length of H.264 headers is variable and thus it might not be
1053 * aligned for the coda to append the encoded frame. In that is
1054 * the case a filler NAL must be added to header 2.
1056 ctx->vpu_header_size[2] = coda_h264_padding(
1057 (ctx->vpu_header_size[0] +
1058 ctx->vpu_header_size[1]),
1059 ctx->vpu_header[2]);
1061 case V4L2_PIX_FMT_MPEG4:
1063 * Get VOS in the first frame and copy it to an
1064 * intermediate buffer
1066 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1067 &ctx->vpu_header[0][0],
1068 &ctx->vpu_header_size[0]);
1072 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1073 &ctx->vpu_header[1][0],
1074 &ctx->vpu_header_size[1]);
1078 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1079 &ctx->vpu_header[2][0],
1080 &ctx->vpu_header_size[2]);
1085 /* No more formats need to save headers at the moment */
1090 mutex_unlock(&dev->coda_mutex);
1094 static int coda_prepare_encode(struct coda_ctx *ctx)
1096 struct coda_q_data *q_data_src, *q_data_dst;
1097 struct vb2_buffer *src_buf, *dst_buf;
1098 struct coda_dev *dev = ctx->dev;
1100 int quant_param = 0;
1101 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1106 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1107 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1108 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1109 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1110 dst_fourcc = q_data_dst->fourcc;
1112 src_buf->v4l2_buf.sequence = ctx->osequence;
1113 dst_buf->v4l2_buf.sequence = ctx->osequence;
1117 * Workaround coda firmware BUG that only marks the first
1118 * frame as IDR. This is a problem for some decoders that can't
1119 * recover when a frame is lost.
1121 if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
1122 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1123 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1125 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1126 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1129 if (dev->devtype->product == CODA_960)
1130 coda_set_gdi_regs(ctx);
1133 * Copy headers at the beginning of the first frame for H.264 only.
1134 * In MPEG4 they are already copied by the coda.
1136 if (src_buf->v4l2_buf.sequence == 0) {
1137 pic_stream_buffer_addr =
1138 vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
1139 ctx->vpu_header_size[0] +
1140 ctx->vpu_header_size[1] +
1141 ctx->vpu_header_size[2];
1142 pic_stream_buffer_size = q_data_dst->sizeimage -
1143 ctx->vpu_header_size[0] -
1144 ctx->vpu_header_size[1] -
1145 ctx->vpu_header_size[2];
1146 memcpy(vb2_plane_vaddr(dst_buf, 0),
1147 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1148 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
1149 &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
1150 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
1151 ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
1152 ctx->vpu_header_size[2]);
1154 pic_stream_buffer_addr =
1155 vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1156 pic_stream_buffer_size = q_data_dst->sizeimage;
1159 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1161 switch (dst_fourcc) {
1162 case V4L2_PIX_FMT_H264:
1163 quant_param = ctx->params.h264_intra_qp;
1165 case V4L2_PIX_FMT_MPEG4:
1166 quant_param = ctx->params.mpeg4_intra_qp;
1168 case V4L2_PIX_FMT_JPEG:
1172 v4l2_warn(&ctx->dev->v4l2_dev,
1173 "cannot set intra qp, fmt not supported\n");
1178 switch (dst_fourcc) {
1179 case V4L2_PIX_FMT_H264:
1180 quant_param = ctx->params.h264_inter_qp;
1182 case V4L2_PIX_FMT_MPEG4:
1183 quant_param = ctx->params.mpeg4_inter_qp;
1186 v4l2_warn(&ctx->dev->v4l2_dev,
1187 "cannot set inter qp, fmt not supported\n");
1193 if (ctx->params.rot_mode)
1194 rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
1195 coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1196 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1198 if (dev->devtype->product == CODA_960) {
1199 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1200 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1201 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1203 reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
1205 reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
1207 coda_write_base(ctx, q_data_src, src_buf, reg);
1209 coda_write(dev, force_ipicture << 1 & 0x2,
1210 CODA_CMD_ENC_PIC_OPTION);
1212 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1213 coda_write(dev, pic_stream_buffer_size / 1024,
1214 CODA_CMD_ENC_PIC_BB_SIZE);
1216 if (!ctx->streamon_out) {
1217 /* After streamoff on the output side, set stream end flag */
1218 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1219 coda_write(dev, ctx->bit_stream_param,
1220 CODA_REG_BIT_BIT_STREAM_PARAM);
1223 if (dev->devtype->product != CODA_DX6)
1224 coda_write(dev, ctx->iram_info.axi_sram_use,
1225 CODA7_REG_BIT_AXI_SRAM_USE);
1227 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1232 static void coda_finish_encode(struct coda_ctx *ctx)
1234 struct vb2_buffer *src_buf, *dst_buf;
1235 struct coda_dev *dev = ctx->dev;
1236 u32 wr_ptr, start_ptr;
1238 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1239 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1241 /* Get results from the coda */
1242 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1243 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1245 /* Calculate bytesused field */
1246 if (dst_buf->v4l2_buf.sequence == 0) {
1247 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
1248 ctx->vpu_header_size[0] +
1249 ctx->vpu_header_size[1] +
1250 ctx->vpu_header_size[2]);
1252 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
1255 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1256 wr_ptr - start_ptr);
1258 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1259 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1261 if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1262 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1263 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1265 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1266 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1269 dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
1270 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1271 dst_buf->v4l2_buf.flags |=
1272 src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1273 dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
1275 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1277 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1278 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1281 if (ctx->gopcounter < 0)
1282 ctx->gopcounter = ctx->params.gop_size - 1;
1284 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1285 "job finished: encoding frame (%d) (%s)\n",
1286 dst_buf->v4l2_buf.sequence,
1287 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1288 "KEYFRAME" : "PFRAME");
1291 static void coda_seq_end_work(struct work_struct *work)
1293 struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1294 struct coda_dev *dev = ctx->dev;
1296 mutex_lock(&ctx->buffer_mutex);
1297 mutex_lock(&dev->coda_mutex);
1299 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1300 "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
1302 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1303 v4l2_err(&dev->v4l2_dev,
1304 "CODA_COMMAND_SEQ_END failed\n");
1307 kfifo_init(&ctx->bitstream_fifo,
1308 ctx->bitstream.vaddr, ctx->bitstream.size);
1310 coda_free_framebuffers(ctx);
1311 coda_free_context_buffers(ctx);
1313 mutex_unlock(&dev->coda_mutex);
1314 mutex_unlock(&ctx->buffer_mutex);
1317 static void coda_bit_release(struct coda_ctx *ctx)
1319 coda_free_framebuffers(ctx);
1320 coda_free_context_buffers(ctx);
1323 const struct coda_context_ops coda_bit_encode_ops = {
1324 .queue_init = coda_encoder_queue_init,
1325 .start_streaming = coda_start_encoding,
1326 .prepare_run = coda_prepare_encode,
1327 .finish_run = coda_finish_encode,
1328 .seq_end_work = coda_seq_end_work,
1329 .release = coda_bit_release,
1333 * Decoder context operations
1336 static int __coda_start_decoding(struct coda_ctx *ctx)
1338 struct coda_q_data *q_data_src, *q_data_dst;
1339 u32 bitstream_buf, bitstream_size;
1340 struct coda_dev *dev = ctx->dev;
1342 u32 src_fourcc, dst_fourcc;
1346 /* Start decoding */
1347 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1348 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1349 bitstream_buf = ctx->bitstream.paddr;
1350 bitstream_size = ctx->bitstream.size;
1351 src_fourcc = q_data_src->fourcc;
1352 dst_fourcc = q_data_dst->fourcc;
1354 /* Allocate per-instance buffers */
1355 ret = coda_alloc_context_buffers(ctx, q_data_src);
1359 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1361 /* Update coda bitstream read and write pointers from kfifo */
1362 coda_kfifo_sync_to_device_full(ctx);
1364 ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
1365 if (dst_fourcc == V4L2_PIX_FMT_NV12)
1366 ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
1367 coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
1369 ctx->display_idx = -1;
1370 ctx->frm_dis_flg = 0;
1371 coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1373 coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1374 CODA_REG_BIT_BIT_STREAM_PARAM);
1376 coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1377 coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1379 if ((dev->devtype->product == CODA_7541) ||
1380 (dev->devtype->product == CODA_960))
1381 val |= CODA_REORDER_ENABLE;
1382 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
1383 val |= CODA_NO_INT_ENABLE;
1384 coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1386 ctx->params.codec_mode = ctx->codec->mode;
1387 if (dev->devtype->product == CODA_960 &&
1388 src_fourcc == V4L2_PIX_FMT_MPEG4)
1389 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1391 ctx->params.codec_mode_aux = 0;
1392 if (src_fourcc == V4L2_PIX_FMT_H264) {
1393 if (dev->devtype->product == CODA_7541) {
1394 coda_write(dev, ctx->psbuf.paddr,
1395 CODA_CMD_DEC_SEQ_PS_BB_START);
1396 coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1397 CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1399 if (dev->devtype->product == CODA_960) {
1400 coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1401 coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1404 if (dev->devtype->product != CODA_960)
1405 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1407 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1408 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1409 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1413 /* Update kfifo out pointer from coda bitstream read pointer */
1414 coda_kfifo_sync_from_device(ctx);
1416 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1418 if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1419 v4l2_err(&dev->v4l2_dev,
1420 "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1421 coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1425 val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1426 if (dev->devtype->product == CODA_DX6) {
1427 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1428 height = val & CODADX6_PICHEIGHT_MASK;
1430 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1431 height = val & CODA7_PICHEIGHT_MASK;
1434 if (width > q_data_dst->width || height > q_data_dst->height) {
1435 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1436 width, height, q_data_dst->width, q_data_dst->height);
1440 width = round_up(width, 16);
1441 height = round_up(height, 16);
1443 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1444 __func__, ctx->idx, width, height);
1446 ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1447 if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1448 v4l2_err(&dev->v4l2_dev,
1449 "not enough framebuffers to decode (%d < %d)\n",
1450 CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1454 if (src_fourcc == V4L2_PIX_FMT_H264) {
1458 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1459 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1461 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1462 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1463 q_data_dst->rect.width = width - q_data_dst->rect.left -
1464 (left_right & 0x3ff);
1465 q_data_dst->rect.height = height - q_data_dst->rect.top -
1466 (top_bottom & 0x3ff);
1469 ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1471 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1475 /* Tell the decoder how many frame buffers we allocated. */
1476 coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1477 coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1479 if (dev->devtype->product != CODA_DX6) {
1480 /* Set secondary AXI IRAM */
1481 coda_setup_iram(ctx);
1483 coda_write(dev, ctx->iram_info.buf_bit_use,
1484 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1485 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1486 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1487 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1488 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1489 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1490 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1491 coda_write(dev, ctx->iram_info.buf_ovl_use,
1492 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1493 if (dev->devtype->product == CODA_960)
1494 coda_write(dev, ctx->iram_info.buf_btp_use,
1495 CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1498 if (dev->devtype->product == CODA_960) {
1499 int cbb_size, crb_size;
1501 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1502 /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
1503 coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
1505 if (dst_fourcc == V4L2_PIX_FMT_NV12) {
1512 coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
1513 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
1514 cbb_size << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
1515 crb_size << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
1516 CODA9_CMD_SET_FRAME_CACHE_CONFIG);
1519 if (src_fourcc == V4L2_PIX_FMT_H264) {
1520 coda_write(dev, ctx->slicebuf.paddr,
1521 CODA_CMD_SET_FRAME_SLICE_BB_START);
1522 coda_write(dev, ctx->slicebuf.size / 1024,
1523 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1526 if (dev->devtype->product == CODA_7541) {
1527 int max_mb_x = 1920 / 16;
1528 int max_mb_y = 1088 / 16;
1529 int max_mb_num = max_mb_x * max_mb_y;
1531 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1532 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1533 } else if (dev->devtype->product == CODA_960) {
1534 int max_mb_x = 1920 / 16;
1535 int max_mb_y = 1088 / 16;
1536 int max_mb_num = max_mb_x * max_mb_y;
1538 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1539 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1542 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1543 v4l2_err(&ctx->dev->v4l2_dev,
1544 "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1551 static int coda_start_decoding(struct coda_ctx *ctx)
1553 struct coda_dev *dev = ctx->dev;
1556 mutex_lock(&dev->coda_mutex);
1557 ret = __coda_start_decoding(ctx);
1558 mutex_unlock(&dev->coda_mutex);
1563 static int coda_prepare_decode(struct coda_ctx *ctx)
1565 struct vb2_buffer *dst_buf;
1566 struct coda_dev *dev = ctx->dev;
1567 struct coda_q_data *q_data_dst;
1568 struct coda_buffer_meta *meta;
1569 u32 reg_addr, reg_stride;
1571 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1572 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1574 /* Try to copy source buffer contents into the bitstream ringbuffer */
1575 mutex_lock(&ctx->bitstream_mutex);
1576 coda_fill_bitstream(ctx);
1577 mutex_unlock(&ctx->bitstream_mutex);
1579 if (coda_get_bitstream_payload(ctx) < 512 &&
1580 (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1581 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1582 "bitstream payload: %d, skipping\n",
1583 coda_get_bitstream_payload(ctx));
1584 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1588 /* Run coda_start_decoding (again) if not yet initialized */
1589 if (!ctx->initialized) {
1590 int ret = __coda_start_decoding(ctx);
1593 v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1594 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1597 ctx->initialized = 1;
1601 if (dev->devtype->product == CODA_960)
1602 coda_set_gdi_regs(ctx);
1604 if (dev->devtype->product == CODA_960) {
1606 * The CODA960 seems to have an internal list of buffers with
1607 * 64 entries that includes the registered frame buffers as
1608 * well as the rotator buffer output.
1609 * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
1611 coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
1612 CODA9_CMD_DEC_PIC_ROT_INDEX);
1614 reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
1615 reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
1617 reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
1618 reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
1620 coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
1621 coda_write(dev, q_data_dst->bytesperline, reg_stride);
1623 coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1624 CODA_CMD_DEC_PIC_ROT_MODE);
1626 switch (dev->devtype->product) {
1630 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1633 /* 'hardcode to use interrupt disable mode'? */
1634 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
1638 coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1640 coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1641 coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1643 if (dev->devtype->product != CODA_DX6)
1644 coda_write(dev, ctx->iram_info.axi_sram_use,
1645 CODA7_REG_BIT_AXI_SRAM_USE);
1647 meta = list_first_entry_or_null(&ctx->buffer_meta_list,
1648 struct coda_buffer_meta, list);
1650 if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
1652 /* If this is the last buffer in the bitstream, add padding */
1653 if (meta->end == (ctx->bitstream_fifo.kfifo.in &
1654 ctx->bitstream_fifo.kfifo.mask)) {
1655 static unsigned char buf[512];
1658 /* Pad to multiple of 256 and then add 256 more */
1659 pad = ((0 - meta->end) & 0xff) + 256;
1661 memset(buf, 0xff, sizeof(buf));
1663 kfifo_in(&ctx->bitstream_fifo, buf, pad);
1667 coda_kfifo_sync_to_device_full(ctx);
1669 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1674 static void coda_finish_decode(struct coda_ctx *ctx)
1676 struct coda_dev *dev = ctx->dev;
1677 struct coda_q_data *q_data_src;
1678 struct coda_q_data *q_data_dst;
1679 struct vb2_buffer *dst_buf;
1680 struct coda_buffer_meta *meta;
1681 unsigned long payload;
1690 /* Update kfifo out pointer from coda bitstream read pointer */
1691 coda_kfifo_sync_from_device(ctx);
1694 * in stream-end mode, the read pointer can overshoot the write pointer
1695 * by up to 512 bytes
1697 if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1698 if (coda_get_bitstream_payload(ctx) >= CODA_MAX_FRAME_SIZE - 512)
1699 kfifo_init(&ctx->bitstream_fifo,
1700 ctx->bitstream.vaddr, ctx->bitstream.size);
1703 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1704 src_fourcc = q_data_src->fourcc;
1706 val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1708 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1710 success = val & 0x1;
1712 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1714 if (src_fourcc == V4L2_PIX_FMT_H264) {
1716 v4l2_err(&dev->v4l2_dev,
1717 "insufficient PS buffer space (%d bytes)\n",
1720 v4l2_err(&dev->v4l2_dev,
1721 "insufficient slice buffer space (%d bytes)\n",
1722 ctx->slicebuf.size);
1725 val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
1726 width = (val >> 16) & 0xffff;
1727 height = val & 0xffff;
1729 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1731 /* frame crop information */
1732 if (src_fourcc == V4L2_PIX_FMT_H264) {
1736 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
1737 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
1739 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
1740 /* Keep current crop information */
1742 struct v4l2_rect *rect = &q_data_dst->rect;
1744 rect->left = left_right >> 16 & 0xffff;
1745 rect->top = top_bottom >> 16 & 0xffff;
1746 rect->width = width - rect->left -
1747 (left_right & 0xffff);
1748 rect->height = height - rect->top -
1749 (top_bottom & 0xffff);
1755 err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
1757 v4l2_err(&dev->v4l2_dev,
1758 "errors in %d macroblocks\n", err_mb);
1760 if (dev->devtype->product == CODA_7541) {
1761 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
1763 /* not enough bitstream data */
1764 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1765 "prescan failed: %d\n", val);
1771 ctx->frm_dis_flg = coda_read(dev,
1772 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1775 * The previous display frame was copied out by the rotator,
1776 * now it can be overwritten again
1778 if (ctx->display_idx >= 0 &&
1779 ctx->display_idx < ctx->num_internal_frames) {
1780 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
1781 coda_write(dev, ctx->frm_dis_flg,
1782 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1786 * The index of the last decoded frame, not necessarily in
1787 * display order, and the index of the next display frame.
1788 * The latter could have been decoded in a previous run.
1790 decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
1791 display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
1793 if (decoded_idx == -1) {
1794 /* no frame was decoded, but we might have a display frame */
1795 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
1796 ctx->sequence_offset++;
1797 else if (ctx->display_idx < 0)
1799 } else if (decoded_idx == -2) {
1800 /* no frame was decoded, we still return remaining buffers */
1801 } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
1802 v4l2_err(&dev->v4l2_dev,
1803 "decoded frame index out of range: %d\n", decoded_idx);
1805 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
1806 val -= ctx->sequence_offset;
1807 mutex_lock(&ctx->bitstream_mutex);
1808 if (!list_empty(&ctx->buffer_meta_list)) {
1809 meta = list_first_entry(&ctx->buffer_meta_list,
1810 struct coda_buffer_meta, list);
1811 list_del(&meta->list);
1812 if (val != (meta->sequence & 0xffff)) {
1813 v4l2_err(&dev->v4l2_dev,
1814 "sequence number mismatch (%d(%d) != %d)\n",
1815 val, ctx->sequence_offset,
1818 ctx->frame_metas[decoded_idx] = *meta;
1821 v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
1822 memset(&ctx->frame_metas[decoded_idx], 0,
1823 sizeof(struct coda_buffer_meta));
1824 ctx->frame_metas[decoded_idx].sequence = val;
1825 ctx->sequence_offset++;
1827 mutex_unlock(&ctx->bitstream_mutex);
1829 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
1831 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
1833 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
1835 ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
1837 ctx->frame_errors[decoded_idx] = err_mb;
1840 if (display_idx == -1) {
1842 * no more frames to be decoded, but there could still
1843 * be rotator output to dequeue
1846 } else if (display_idx == -3) {
1847 /* possibly prescan failure */
1848 } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
1849 v4l2_err(&dev->v4l2_dev,
1850 "presentation frame index out of range: %d\n",
1854 /* If a frame was copied out, return it */
1855 if (ctx->display_idx >= 0 &&
1856 ctx->display_idx < ctx->num_internal_frames) {
1857 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1858 dst_buf->v4l2_buf.sequence = ctx->osequence++;
1860 dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
1861 V4L2_BUF_FLAG_PFRAME |
1862 V4L2_BUF_FLAG_BFRAME);
1863 dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
1864 meta = &ctx->frame_metas[ctx->display_idx];
1865 dst_buf->v4l2_buf.timecode = meta->timecode;
1866 dst_buf->v4l2_buf.timestamp = meta->timestamp;
1868 switch (q_data_dst->fourcc) {
1869 case V4L2_PIX_FMT_YUV420:
1870 case V4L2_PIX_FMT_YVU420:
1871 case V4L2_PIX_FMT_NV12:
1873 payload = width * height * 3 / 2;
1875 case V4L2_PIX_FMT_YUV422P:
1876 payload = width * height * 2;
1879 vb2_set_plane_payload(dst_buf, 0, payload);
1881 v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
1882 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
1884 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1885 "job finished: decoding frame (%d) (%s)\n",
1886 dst_buf->v4l2_buf.sequence,
1887 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1888 "KEYFRAME" : "PFRAME");
1890 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1891 "job finished: no frame decoded\n");
1894 /* The rotator will copy the current display frame next time */
1895 ctx->display_idx = display_idx;
1898 const struct coda_context_ops coda_bit_decode_ops = {
1899 .queue_init = coda_decoder_queue_init,
1900 .start_streaming = coda_start_decoding,
1901 .prepare_run = coda_prepare_decode,
1902 .finish_run = coda_finish_decode,
1903 .seq_end_work = coda_seq_end_work,
1904 .release = coda_bit_release,
1907 irqreturn_t coda_irq_handler(int irq, void *data)
1909 struct coda_dev *dev = data;
1910 struct coda_ctx *ctx;
1912 /* read status register to attend the IRQ */
1913 coda_read(dev, CODA_REG_BIT_INT_STATUS);
1914 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
1915 CODA_REG_BIT_INT_CLEAR);
1917 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1919 v4l2_err(&dev->v4l2_dev,
1920 "Instance released before the end of transaction\n");
1921 mutex_unlock(&dev->coda_mutex);
1925 if (ctx->aborting) {
1926 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1927 "task has been aborted\n");
1930 if (coda_isbusy(ctx->dev)) {
1931 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1932 "coda is still busy!!!!\n");
1936 complete(&ctx->completion);