drivers/media/platform/s5p-fimc/fimc-core.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver
   3  *
   4  * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd.
   5  * Sylwester Nawrocki <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published
   9  * by the Free Software Foundation, either version 2 of the License,
  10  * or (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/bug.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/list.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/clk.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/videobuf2-core.h>
  28 #include <media/videobuf2-dma-contig.h>
  29
  30 #include "fimc-core.h"
  31 #include "fimc-reg.h"
  32 #include "fimc-mdevice.h"
  33
  34 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  35         "sclk_fimc", "fimc"
  36 };
  37
  38 static struct fimc_fmt fimc_formats[] = {
  39         {
  40                 .name           = "RGB565",
  41                 .fourcc         = V4L2_PIX_FMT_RGB565,
  42                 .depth          = { 16 },
  43                 .color          = FIMC_FMT_RGB565,
  44                 .memplanes      = 1,
  45                 .colplanes      = 1,
  46                 .flags          = FMT_FLAGS_M2M,
  47         }, {
  48                 .name           = "BGR666",
  49                 .fourcc         = V4L2_PIX_FMT_BGR666,
  50                 .depth          = { 32 },
  51                 .color          = FIMC_FMT_RGB666,
  52                 .memplanes      = 1,
  53                 .colplanes      = 1,
  54                 .flags          = FMT_FLAGS_M2M,
  55         }, {
  56                 .name           = "ARGB8888, 32 bpp",
  57                 .fourcc         = V4L2_PIX_FMT_RGB32,
  58                 .depth          = { 32 },
  59                 .color          = FIMC_FMT_RGB888,
  60                 .memplanes      = 1,
  61                 .colplanes      = 1,
  62                 .flags          = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
  63         }, {
  64                 .name           = "ARGB1555",
  65                 .fourcc         = V4L2_PIX_FMT_RGB555,
  66                 .depth          = { 16 },
  67                 .color          = FIMC_FMT_RGB555,
  68                 .memplanes      = 1,
  69                 .colplanes      = 1,
  70                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  71         }, {
  72                 .name           = "ARGB4444",
  73                 .fourcc         = V4L2_PIX_FMT_RGB444,
  74                 .depth          = { 16 },
  75                 .color          = FIMC_FMT_RGB444,
  76                 .memplanes      = 1,
  77                 .colplanes      = 1,
  78                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  79         }, {
  80                 .name           = "YUV 4:2:2 packed, YCbYCr",
  81                 .fourcc         = V4L2_PIX_FMT_YUYV,
  82                 .depth          = { 16 },
  83                 .color          = FIMC_FMT_YCBYCR422,
  84                 .memplanes      = 1,
  85                 .colplanes      = 1,
  86                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  87                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  88         }, {
  89                 .name           = "YUV 4:2:2 packed, CbYCrY",
  90                 .fourcc         = V4L2_PIX_FMT_UYVY,
  91                 .depth          = { 16 },
  92                 .color          = FIMC_FMT_CBYCRY422,
  93                 .memplanes      = 1,
  94                 .colplanes      = 1,
  95                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
  96                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  97         }, {
  98                 .name           = "YUV 4:2:2 packed, CrYCbY",
  99                 .fourcc         = V4L2_PIX_FMT_VYUY,
 100                 .depth          = { 16 },
 101                 .color          = FIMC_FMT_CRYCBY422,
 102                 .memplanes      = 1,
 103                 .colplanes      = 1,
 104                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
 105                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 106         }, {
 107                 .name           = "YUV 4:2:2 packed, YCrYCb",
 108                 .fourcc         = V4L2_PIX_FMT_YVYU,
 109                 .depth          = { 16 },
 110                 .color          = FIMC_FMT_YCRYCB422,
 111                 .memplanes      = 1,
 112                 .colplanes      = 1,
 113                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
 114                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 115         }, {
 116                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 117                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 118                 .depth          = { 12 },
 119                 .color          = FIMC_FMT_YCBYCR422,
 120                 .memplanes      = 1,
 121                 .colplanes      = 3,
 122                 .flags          = FMT_FLAGS_M2M,
 123         }, {
 124                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 125                 .fourcc         = V4L2_PIX_FMT_NV16,
 126                 .depth          = { 16 },
 127                 .color          = FIMC_FMT_YCBYCR422,
 128                 .memplanes      = 1,
 129                 .colplanes      = 2,
 130                 .flags          = FMT_FLAGS_M2M,
 131         }, {
 132                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 133                 .fourcc         = V4L2_PIX_FMT_NV61,
 134                 .depth          = { 16 },
 135                 .color          = FIMC_FMT_YCRYCB422,
 136                 .memplanes      = 1,
 137                 .colplanes      = 2,
 138                 .flags          = FMT_FLAGS_M2M,
 139         }, {
 140                 .name           = "YUV 4:2:0 planar, YCbCr",
 141                 .fourcc         = V4L2_PIX_FMT_YUV420,
 142                 .depth          = { 12 },
 143                 .color          = FIMC_FMT_YCBCR420,
 144                 .memplanes      = 1,
 145                 .colplanes      = 3,
 146                 .flags          = FMT_FLAGS_M2M,
 147         }, {
 148                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 149                 .fourcc         = V4L2_PIX_FMT_NV12,
 150                 .depth          = { 12 },
 151                 .color          = FIMC_FMT_YCBCR420,
 152                 .memplanes      = 1,
 153                 .colplanes      = 2,
 154                 .flags          = FMT_FLAGS_M2M,
 155         }, {
 156                 .name           = "YUV 4:2:0 non-contig. 2p, Y/CbCr",
 157                 .fourcc         = V4L2_PIX_FMT_NV12M,
 158                 .color          = FIMC_FMT_YCBCR420,
 159                 .depth          = { 8, 4 },
 160                 .memplanes      = 2,
 161                 .colplanes      = 2,
 162                 .flags          = FMT_FLAGS_M2M,
 163         }, {
 164                 .name           = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr",
 165                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 166                 .color          = FIMC_FMT_YCBCR420,
 167                 .depth          = { 8, 2, 2 },
 168                 .memplanes      = 3,
 169                 .colplanes      = 3,
 170                 .flags          = FMT_FLAGS_M2M,
 171         }, {
 172                 .name           = "YUV 4:2:0 non-contig. 2p, tiled",
 173                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 174                 .color          = FIMC_FMT_YCBCR420,
 175                 .depth          = { 8, 4 },
 176                 .memplanes      = 2,
 177                 .colplanes      = 2,
 178                 .flags          = FMT_FLAGS_M2M,
 179         }, {
 180                 .name           = "JPEG encoded data",
 181                 .fourcc         = V4L2_PIX_FMT_JPEG,
 182                 .color          = FIMC_FMT_JPEG,
 183                 .depth          = { 8 },
 184                 .memplanes      = 1,
 185                 .colplanes      = 1,
 186                 .mbus_code      = V4L2_MBUS_FMT_JPEG_1X8,
 187                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 188         }, {
 189                 .name           = "S5C73MX interleaved UYVY/JPEG",
 190                 .fourcc         = V4L2_PIX_FMT_S5C_UYVY_JPG,
 191                 .color          = FIMC_FMT_YUYV_JPEG,
 192                 .depth          = { 8 },
 193                 .memplanes      = 2,
 194                 .colplanes      = 1,
 195                 .mdataplanes    = 0x2, /* plane 1 holds frame meta data */
 196                 .mbus_code      = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8,
 197                 .flags          = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED,
 198         },
 199 };
 200
 201 struct fimc_fmt *fimc_get_format(unsigned int index)
 202 {
 203         if (index >= ARRAY_SIZE(fimc_formats))
 204                 return NULL;
 205
 206         return &fimc_formats[index];
 207 }
 208
 209 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 210                             int dw, int dh, int rotation)
 211 {
 212         if (rotation == 90 || rotation == 270)
 213                 swap(dw, dh);
 214
 215         if (!ctx->scaler.enabled)
 216                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
 217
 218         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 219                 return -EINVAL;
 220
 221         return 0;
 222 }
 223
 224 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 225 {
 226         u32 sh = 6;
 227
 228         if (src >= 64 * tar)
 229                 return -EINVAL;
 230
 231         while (sh--) {
 232                 u32 tmp = 1 << sh;
 233                 if (src >= tar * tmp) {
 234                         *shift = sh, *ratio = tmp;
 235                         return 0;
 236                 }
 237         }
 238         *shift = 0, *ratio = 1;
 239         return 0;
 240 }
 241
 242 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 243 {
 244         const struct fimc_variant *variant = ctx->fimc_dev->variant;
 245         struct device *dev = &ctx->fimc_dev->pdev->dev;
 246         struct fimc_scaler *sc = &ctx->scaler;
 247         struct fimc_frame *s_frame = &ctx->s_frame;
 248         struct fimc_frame *d_frame = &ctx->d_frame;
 249         int tx, ty, sx, sy;
 250         int ret;
 251
 252         if (ctx->rotation == 90 || ctx->rotation == 270) {
 253                 ty = d_frame->width;
 254                 tx = d_frame->height;
 255         } else {
 256                 tx = d_frame->width;
 257                 ty = d_frame->height;
 258         }
 259         if (tx <= 0 || ty <= 0) {
 260                 dev_err(dev, "Invalid target size: %dx%d\n", tx, ty);
 261                 return -EINVAL;
 262         }
 263
 264         sx = s_frame->width;
 265         sy = s_frame->height;
 266         if (sx <= 0 || sy <= 0) {
 267                 dev_err(dev, "Invalid source size: %dx%d\n", sx, sy);
 268                 return -EINVAL;
 269         }
 270         sc->real_width = sx;
 271         sc->real_height = sy;
 272
 273         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 274         if (ret)
 275                 return ret;
 276
 277         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 278         if (ret)
 279                 return ret;
 280
 281         sc->pre_dst_width = sx / sc->pre_hratio;
 282         sc->pre_dst_height = sy / sc->pre_vratio;
 283
 284         if (variant->has_mainscaler_ext) {
 285                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 286                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 287         } else {
 288                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 289                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 290
 291         }
 292
 293         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 294         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 295
 296         /* check to see if input and output size/format differ */
 297         if (s_frame->fmt->color == d_frame->fmt->color
 298                 && s_frame->width == d_frame->width
 299                 && s_frame->height == d_frame->height)
 300                 sc->copy_mode = 1;
 301         else
 302                 sc->copy_mode = 0;
 303
 304         return 0;
 305 }
 306
 307 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 308 {
 309         struct fimc_dev *fimc = priv;
 310         struct fimc_ctx *ctx;
 311
 312         fimc_hw_clear_irq(fimc);
 313
 314         spin_lock(&fimc->slock);
 315
 316         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 317                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 318                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 319                         wake_up(&fimc->irq_queue);
 320                         goto out;
 321                 }
 322                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 323                 if (ctx != NULL) {
 324                         spin_unlock(&fimc->slock);
 325                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 326
 327                         if (ctx->state & FIMC_CTX_SHUT) {
 328                                 ctx->state &= ~FIMC_CTX_SHUT;
 329                                 wake_up(&fimc->irq_queue);
 330                         }
 331                         return IRQ_HANDLED;
 332                 }
 333         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 334                 int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) &&
 335                                 fimc->vid_cap.reqbufs_count == 1;
 336                 fimc_capture_irq_handler(fimc, !last_buf);
 337         }
 338 out:
 339         spin_unlock(&fimc->slock);
 340         return IRQ_HANDLED;
 341 }
 342
 343 /* The color format (colplanes, memplanes) must be already configured. */
 344 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 345                       struct fimc_frame *frame, struct fimc_addr *paddr)
 346 {
 347         int ret = 0;
 348         u32 pix_size;
 349
 350         if (vb == NULL || frame == NULL)
 351                 return -EINVAL;
 352
 353         pix_size = frame->width * frame->height;
 354
 355         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 356                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 357
 358         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 359
 360         if (frame->fmt->memplanes == 1) {
 361                 switch (frame->fmt->colplanes) {
 362                 case 1:
 363                         paddr->cb = 0;
 364                         paddr->cr = 0;
 365                         break;
 366                 case 2:
 367                         /* decompose Y into Y/Cb */
 368                         paddr->cb = (u32)(paddr->y + pix_size);
 369                         paddr->cr = 0;
 370                         break;
 371                 case 3:
 372                         paddr->cb = (u32)(paddr->y + pix_size);
 373                         /* decompose Y into Y/Cb/Cr */
 374                         if (FIMC_FMT_YCBCR420 == frame->fmt->color)
 375                                 paddr->cr = (u32)(paddr->cb
 376                                                 + (pix_size >> 2));
 377                         else /* 422 */
 378                                 paddr->cr = (u32)(paddr->cb
 379                                                 + (pix_size >> 1));
 380                         break;
 381                 default:
 382                         return -EINVAL;
 383                 }
 384         } else if (!frame->fmt->mdataplanes) {
 385                 if (frame->fmt->memplanes >= 2)
 386                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 387
 388                 if (frame->fmt->memplanes == 3)
 389                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 390         }
 391
 392         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 393             paddr->y, paddr->cb, paddr->cr, ret);
 394
 395         return ret;
 396 }
 397
 398 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 399 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 400 {
 401         /* The one only mode supported in SoC. */
 402         ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 403         ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB;
 404
 405         /* Set order for 1 plane input formats. */
 406         switch (ctx->s_frame.fmt->color) {
 407         case FIMC_FMT_YCRYCB422:
 408                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
 409                 break;
 410         case FIMC_FMT_CBYCRY422:
 411                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
 412                 break;
 413         case FIMC_FMT_CRYCBY422:
 414                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
 415                 break;
 416         case FIMC_FMT_YCBYCR422:
 417         default:
 418                 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
 419                 break;
 420         }
 421         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 422
 423         switch (ctx->d_frame.fmt->color) {
 424         case FIMC_FMT_YCRYCB422:
 425                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
 426                 break;
 427         case FIMC_FMT_CBYCRY422:
 428                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
 429                 break;
 430         case FIMC_FMT_CRYCBY422:
 431                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
 432                 break;
 433         case FIMC_FMT_YCBYCR422:
 434         default:
 435                 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
 436                 break;
 437         }
 438         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 439 }
 440
 441 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 442 {
 443         const struct fimc_variant *variant = ctx->fimc_dev->variant;
 444         u32 i, depth = 0;
 445
 446         for (i = 0; i < f->fmt->colplanes; i++)
 447                 depth += f->fmt->depth[i];
 448
 449         f->dma_offset.y_h = f->offs_h;
 450         if (!variant->pix_hoff)
 451                 f->dma_offset.y_h *= (depth >> 3);
 452
 453         f->dma_offset.y_v = f->offs_v;
 454
 455         f->dma_offset.cb_h = f->offs_h;
 456         f->dma_offset.cb_v = f->offs_v;
 457
 458         f->dma_offset.cr_h = f->offs_h;
 459         f->dma_offset.cr_v = f->offs_v;
 460
 461         if (!variant->pix_hoff) {
 462                 if (f->fmt->colplanes == 3) {
 463                         f->dma_offset.cb_h >>= 1;
 464                         f->dma_offset.cr_h >>= 1;
 465                 }
 466                 if (f->fmt->color == FIMC_FMT_YCBCR420) {
 467                         f->dma_offset.cb_v >>= 1;
 468                         f->dma_offset.cr_v >>= 1;
 469                 }
 470         }
 471
 472         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 473             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 474 }
 475
 476 static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx)
 477 {
 478         struct fimc_effect *effect = &ctx->effect;
 479
 480         switch (colorfx) {
 481         case V4L2_COLORFX_NONE:
 482                 effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 483                 break;
 484         case V4L2_COLORFX_BW:
 485                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 486                 effect->pat_cb = 128;
 487                 effect->pat_cr = 128;
 488                 break;
 489         case V4L2_COLORFX_SEPIA:
 490                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 491                 effect->pat_cb = 115;
 492                 effect->pat_cr = 145;
 493                 break;
 494         case V4L2_COLORFX_NEGATIVE:
 495                 effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE;
 496                 break;
 497         case V4L2_COLORFX_EMBOSS:
 498                 effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING;
 499                 break;
 500         case V4L2_COLORFX_ART_FREEZE:
 501                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE;
 502                 break;
 503         case V4L2_COLORFX_SILHOUETTE:
 504                 effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE;
 505                 break;
 506         case V4L2_COLORFX_SET_CBCR:
 507                 effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY;
 508                 effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8;
 509                 effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff;
 510                 break;
 511         default:
 512                 return -EINVAL;
 513         }
 514
 515         return 0;
 516 }
 517
 518 /*
 519  * V4L2 controls handling
 520  */
 521 #define ctrl_to_ctx(__ctrl) \
 522         container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler)
 523
 524 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
 525 {
 526         struct fimc_dev *fimc = ctx->fimc_dev;
 527         const struct fimc_variant *variant = fimc->variant;
 528         int ret = 0;
 529
 530         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 531                 return 0;
 532
 533         switch (ctrl->id) {
 534         case V4L2_CID_HFLIP:
 535                 ctx->hflip = ctrl->val;
 536                 break;
 537
 538         case V4L2_CID_VFLIP:
 539                 ctx->vflip = ctrl->val;
 540                 break;
 541
 542         case V4L2_CID_ROTATE:
 543                 if (fimc_capture_pending(fimc)) {
 544                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 545                                         ctx->s_frame.height, ctx->d_frame.width,
 546                                         ctx->d_frame.height, ctrl->val);
 547                         if (ret)
 548                                 return -EINVAL;
 549                 }
 550                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 551                     !variant->has_out_rot)
 552                         return -EINVAL;
 553
 554                 ctx->rotation = ctrl->val;
 555                 break;
 556
 557         case V4L2_CID_ALPHA_COMPONENT:
 558                 ctx->d_frame.alpha = ctrl->val;
 559                 break;
 560
 561         case V4L2_CID_COLORFX:
 562                 ret = fimc_set_color_effect(ctx, ctrl->val);
 563                 if (ret)
 564                         return ret;
 565                 break;
 566         }
 567
 568         ctx->state |= FIMC_PARAMS;
 569         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 570         return 0;
 571 }
 572
 573 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 574 {
 575         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 576         unsigned long flags;
 577         int ret;
 578
 579         spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 580         ret = __fimc_s_ctrl(ctx, ctrl);
 581         spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 582
 583         return ret;
 584 }
 585
 586 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 587         .s_ctrl = fimc_s_ctrl,
 588 };
 589
 590 int fimc_ctrls_create(struct fimc_ctx *ctx)
 591 {
 592         const struct fimc_variant *variant = ctx->fimc_dev->variant;
 593         unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
 594         struct fimc_ctrls *ctrls = &ctx->ctrls;
 595         struct v4l2_ctrl_handler *handler = &ctrls->handler;
 596
 597         if (ctx->ctrls.ready)
 598                 return 0;
 599
 600         v4l2_ctrl_handler_init(handler, 6);
 601
 602         ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 603                                         V4L2_CID_ROTATE, 0, 270, 90, 0);
 604         ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 605                                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 606         ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 607                                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 608
 609         if (variant->has_alpha)
 610                 ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 611                                         V4L2_CID_ALPHA_COMPONENT,
 612                                         0, max_alpha, 1, 0);
 613         else
 614                 ctrls->alpha = NULL;
 615
 616         ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops,
 617                                 V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR,
 618                                 ~0x983f, V4L2_COLORFX_NONE);
 619
 620         ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops,
 621                                 V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0);
 622
 623         ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 624
 625         if (!handler->error) {
 626                 v4l2_ctrl_cluster(2, &ctrls->colorfx);
 627                 ctrls->ready = true;
 628         }
 629
 630         return handler->error;
 631 }
 632
 633 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 634 {
 635         struct fimc_ctrls *ctrls = &ctx->ctrls;
 636
 637         if (ctrls->ready) {
 638                 v4l2_ctrl_handler_free(&ctrls->handler);
 639                 ctrls->ready = false;
 640                 ctrls->alpha = NULL;
 641         }
 642 }
 643
 644 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 645 {
 646         unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
 647         struct fimc_ctrls *ctrls = &ctx->ctrls;
 648
 649         if (!ctrls->ready)
 650                 return;
 651
 652         mutex_lock(ctrls->handler.lock);
 653         v4l2_ctrl_activate(ctrls->rotate, active);
 654         v4l2_ctrl_activate(ctrls->hflip, active);
 655         v4l2_ctrl_activate(ctrls->vflip, active);
 656         v4l2_ctrl_activate(ctrls->colorfx, active);
 657         if (ctrls->alpha)
 658                 v4l2_ctrl_activate(ctrls->alpha, active && has_alpha);
 659
 660         if (active) {
 661                 fimc_set_color_effect(ctx, ctrls->colorfx->cur.val);
 662                 ctx->rotation = ctrls->rotate->val;
 663                 ctx->hflip    = ctrls->hflip->val;
 664                 ctx->vflip    = ctrls->vflip->val;
 665         } else {
 666                 ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS;
 667                 ctx->rotation = 0;
 668                 ctx->hflip    = 0;
 669                 ctx->vflip    = 0;
 670         }
 671         mutex_unlock(ctrls->handler.lock);
 672 }
 673
 674 /* Update maximum value of the alpha color control */
 675 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
 676 {
 677         struct fimc_dev *fimc = ctx->fimc_dev;
 678         struct v4l2_ctrl *ctrl = ctx->ctrls.alpha;
 679
 680         if (ctrl == NULL || !fimc->variant->has_alpha)
 681                 return;
 682
 683         v4l2_ctrl_lock(ctrl);
 684         ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
 685
 686         if (ctrl->cur.val > ctrl->maximum)
 687                 ctrl->cur.val = ctrl->maximum;
 688
 689         v4l2_ctrl_unlock(ctrl);
 690 }
 691
 692 void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f)
 693 {
 694         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 695         int i;
 696
 697         pixm->width = frame->o_width;
 698         pixm->height = frame->o_height;
 699         pixm->field = V4L2_FIELD_NONE;
 700         pixm->pixelformat = frame->fmt->fourcc;
 701         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 702         pixm->num_planes = frame->fmt->memplanes;
 703
 704         for (i = 0; i < pixm->num_planes; ++i) {
 705                 pixm->plane_fmt[i].bytesperline = frame->bytesperline[i];
 706                 pixm->plane_fmt[i].sizeimage = frame->payload[i];
 707         }
 708 }
 709
 710 /**
 711  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 712  * @fmt: fimc pixel format description (input)
 713  * @width: requested pixel width
 714  * @height: requested pixel height
 715  * @pix: multi-plane format to adjust
 716  */
 717 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 718                                struct v4l2_pix_format_mplane *pix)
 719 {
 720         u32 bytesperline = 0;
 721         int i;
 722
 723         pix->colorspace = V4L2_COLORSPACE_JPEG;
 724         pix->field = V4L2_FIELD_NONE;
 725         pix->num_planes = fmt->memplanes;
 726         pix->pixelformat = fmt->fourcc;
 727         pix->height = height;
 728         pix->width = width;
 729
 730         for (i = 0; i < pix->num_planes; ++i) {
 731                 struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i];
 732                 u32 bpl = plane_fmt->bytesperline;
 733
 734                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 735                         bpl = pix->width; /* Planar */
 736
 737                 if (fmt->colplanes == 1 && /* Packed */
 738                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 739                         bpl = (pix->width * fmt->depth[0]) / 8;
 740                 /*
 741                  * Currently bytesperline for each plane is same, except
 742                  * V4L2_PIX_FMT_YUV420M format. This calculation may need
 743                  * to be changed when other multi-planar formats are added
 744                  * to the fimc_formats[] array.
 745                  */
 746                 if (i == 0)
 747                         bytesperline = bpl;
 748                 else if (i == 1 && fmt->memplanes == 3)
 749                         bytesperline /= 2;
 750
 751                 plane_fmt->bytesperline = bytesperline;
 752                 plane_fmt->sizeimage = max((pix->width * pix->height *
 753                                    fmt->depth[i]) / 8, plane_fmt->sizeimage);
 754         }
 755 }
 756
 757 /**
 758  * fimc_find_format - lookup fimc color format by fourcc or media bus format
 759  * @pixelformat: fourcc to match, ignored if null
 760  * @mbus_code: media bus code to match, ignored if null
 761  * @mask: the color flags to match
 762  * @index: offset in the fimc_formats array, ignored if negative
 763  */
 764 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
 765                                   unsigned int mask, int index)
 766 {
 767         struct fimc_fmt *fmt, *def_fmt = NULL;
 768         unsigned int i;
 769         int id = 0;
 770
 771         if (index >= (int)ARRAY_SIZE(fimc_formats))
 772                 return NULL;
 773
 774         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 775                 fmt = &fimc_formats[i];
 776                 if (!(fmt->flags & mask))
 777                         continue;
 778                 if (pixelformat && fmt->fourcc == *pixelformat)
 779                         return fmt;
 780                 if (mbus_code && fmt->mbus_code == *mbus_code)
 781                         return fmt;
 782                 if (index == id)
 783                         def_fmt = fmt;
 784                 id++;
 785         }
 786         return def_fmt;
 787 }
 788
 789 static void fimc_clk_put(struct fimc_dev *fimc)
 790 {
 791         int i;
 792         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 793                 if (IS_ERR(fimc->clock[i]))
 794                         continue;
 795                 clk_unprepare(fimc->clock[i]);
 796                 clk_put(fimc->clock[i]);
 797                 fimc->clock[i] = ERR_PTR(-EINVAL);
 798         }
 799 }
 800
 801 static int fimc_clk_get(struct fimc_dev *fimc)
 802 {
 803         int i, ret;
 804
 805         for (i = 0; i < MAX_FIMC_CLOCKS; i++)
 806                 fimc->clock[i] = ERR_PTR(-EINVAL);
 807
 808         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
 809                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
 810                 if (IS_ERR(fimc->clock[i])) {
 811                         ret = PTR_ERR(fimc->clock[i]);
 812                         goto err;
 813                 }
 814                 ret = clk_prepare(fimc->clock[i]);
 815                 if (ret < 0) {
 816                         clk_put(fimc->clock[i]);
 817                         fimc->clock[i] = ERR_PTR(-EINVAL);
 818                         goto err;
 819                 }
 820         }
 821         return 0;
 822 err:
 823         fimc_clk_put(fimc);
 824         dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
 825                 fimc_clocks[i]);
 826         return -ENXIO;
 827 }
 828
 829 static int fimc_m2m_suspend(struct fimc_dev *fimc)
 830 {
 831         unsigned long flags;
 832         int timeout;
 833
 834         spin_lock_irqsave(&fimc->slock, flags);
 835         if (!fimc_m2m_pending(fimc)) {
 836                 spin_unlock_irqrestore(&fimc->slock, flags);
 837                 return 0;
 838         }
 839         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
 840         set_bit(ST_M2M_SUSPENDING, &fimc->state);
 841         spin_unlock_irqrestore(&fimc->slock, flags);
 842
 843         timeout = wait_event_timeout(fimc->irq_queue,
 844                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
 845                              FIMC_SHUTDOWN_TIMEOUT);
 846
 847         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
 848         return timeout == 0 ? -EAGAIN : 0;
 849 }
 850
 851 static int fimc_m2m_resume(struct fimc_dev *fimc)
 852 {
 853         struct fimc_ctx *ctx;
 854         unsigned long flags;
 855
 856         spin_lock_irqsave(&fimc->slock, flags);
 857         /* Clear for full H/W setup in first run after resume */
 858         ctx = fimc->m2m.ctx;
 859         fimc->m2m.ctx = NULL;
 860         spin_unlock_irqrestore(&fimc->slock, flags);
 861
 862         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
 863                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 864
 865         return 0;
 866 }
 867
 868 static int fimc_probe(struct platform_device *pdev)
 869 {
 870         const struct fimc_drvdata *drv_data = fimc_get_drvdata(pdev);
 871         struct s5p_platform_fimc *pdata;
 872         struct fimc_dev *fimc;
 873         struct resource *res;
 874         int ret = 0;
 875
 876         if (pdev->id >= drv_data->num_entities) {
 877                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
 878                         pdev->id);
 879                 return -EINVAL;
 880         }
 881
 882         fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
 883         if (!fimc)
 884                 return -ENOMEM;
 885
 886         fimc->id = pdev->id;
 887
 888         fimc->variant = drv_data->variant[fimc->id];
 889         fimc->pdev = pdev;
 890         pdata = pdev->dev.platform_data;
 891         fimc->pdata = pdata;
 892
 893         init_waitqueue_head(&fimc->irq_queue);
 894         spin_lock_init(&fimc->slock);
 895         mutex_init(&fimc->lock);
 896
 897         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 898         fimc->regs = devm_ioremap_resource(&pdev->dev, res);
 899         if (IS_ERR(fimc->regs))
 900                 return PTR_ERR(fimc->regs);
 901
 902         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 903         if (res == NULL) {
 904                 dev_err(&pdev->dev, "Failed to get IRQ resource\n");
 905                 return -ENXIO;
 906         }
 907
 908         ret = fimc_clk_get(fimc);
 909         if (ret)
 910                 return ret;
 911
 912         ret = clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
 913         if (ret < 0)
 914                 return ret;
 915
 916         ret = clk_enable(fimc->clock[CLK_BUS]);
 917         if (ret < 0)
 918                 return ret;
 919
 920         ret = devm_request_irq(&pdev->dev, res->start, fimc_irq_handler,
 921                                0, dev_name(&pdev->dev), fimc);
 922         if (ret) {
 923                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
 924                 goto err_clk;
 925         }
 926
 927         ret = fimc_initialize_capture_subdev(fimc);
 928         if (ret)
 929                 goto err_clk;
 930
 931         platform_set_drvdata(pdev, fimc);
 932         pm_runtime_enable(&pdev->dev);
 933         ret = pm_runtime_get_sync(&pdev->dev);
 934         if (ret < 0)
 935                 goto err_sd;
 936         /* Initialize contiguous memory allocator */
 937         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
 938         if (IS_ERR(fimc->alloc_ctx)) {
 939                 ret = PTR_ERR(fimc->alloc_ctx);
 940                 goto err_pm;
 941         }
 942
 943         dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
 944
 945         pm_runtime_put(&pdev->dev);
 946         return 0;
 947 err_pm:
 948         pm_runtime_put(&pdev->dev);
 949 err_sd:
 950         fimc_unregister_capture_subdev(fimc);
 951 err_clk:
 952         clk_disable(fimc->clock[CLK_BUS]);
 953         fimc_clk_put(fimc);
 954         return ret;
 955 }
 956
 957 static int fimc_runtime_resume(struct device *dev)
 958 {
 959         struct fimc_dev *fimc = dev_get_drvdata(dev);
 960
 961         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
 962
 963         /* Enable clocks and perform basic initalization */
 964         clk_enable(fimc->clock[CLK_GATE]);
 965         fimc_hw_reset(fimc);
 966
 967         /* Resume the capture or mem-to-mem device */
 968         if (fimc_capture_busy(fimc))
 969                 return fimc_capture_resume(fimc);
 970
 971         return fimc_m2m_resume(fimc);
 972 }
 973
 974 static int fimc_runtime_suspend(struct device *dev)
 975 {
 976         struct fimc_dev *fimc = dev_get_drvdata(dev);
 977         int ret = 0;
 978
 979         if (fimc_capture_busy(fimc))
 980                 ret = fimc_capture_suspend(fimc);
 981         else
 982                 ret = fimc_m2m_suspend(fimc);
 983         if (!ret)
 984                 clk_disable(fimc->clock[CLK_GATE]);
 985
 986         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
 987         return ret;
 988 }
 989
 990 #ifdef CONFIG_PM_SLEEP
 991 static int fimc_resume(struct device *dev)
 992 {
 993         struct fimc_dev *fimc = dev_get_drvdata(dev);
 994         unsigned long flags;
 995
 996         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
 997
 998         /* Do not resume if the device was idle before system suspend */
 999         spin_lock_irqsave(&fimc->slock, flags);
1000         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1001             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1002                 spin_unlock_irqrestore(&fimc->slock, flags);
1003                 return 0;
1004         }
1005         fimc_hw_reset(fimc);
1006         spin_unlock_irqrestore(&fimc->slock, flags);
1007
1008         if (fimc_capture_busy(fimc))
1009                 return fimc_capture_resume(fimc);
1010
1011         return fimc_m2m_resume(fimc);
1012 }
1013
1014 static int fimc_suspend(struct device *dev)
1015 {
1016         struct fimc_dev *fimc = dev_get_drvdata(dev);
1017
1018         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1019
1020         if (test_and_set_bit(ST_LPM, &fimc->state))
1021                 return 0;
1022         if (fimc_capture_busy(fimc))
1023                 return fimc_capture_suspend(fimc);
1024
1025         return fimc_m2m_suspend(fimc);
1026 }
1027 #endif /* CONFIG_PM_SLEEP */
1028
1029 static int fimc_remove(struct platform_device *pdev)
1030 {
1031         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1032
1033         pm_runtime_disable(&pdev->dev);
1034         pm_runtime_set_suspended(&pdev->dev);
1035
1036         fimc_unregister_capture_subdev(fimc);
1037         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1038
1039         clk_disable(fimc->clock[CLK_BUS]);
1040         fimc_clk_put(fimc);
1041
1042         dev_info(&pdev->dev, "driver unloaded\n");
1043         return 0;
1044 }
1045
1046 /* Image pixel limits, similar across several FIMC HW revisions. */
1047 static const struct fimc_pix_limit s5p_pix_limit[4] = {
1048         [0] = {
1049                 .scaler_en_w    = 3264,
1050                 .scaler_dis_w   = 8192,
1051                 .in_rot_en_h    = 1920,
1052                 .in_rot_dis_w   = 8192,
1053                 .out_rot_en_w   = 1920,
1054                 .out_rot_dis_w  = 4224,
1055         },
1056         [1] = {
1057                 .scaler_en_w    = 4224,
1058                 .scaler_dis_w   = 8192,
1059                 .in_rot_en_h    = 1920,
1060                 .in_rot_dis_w   = 8192,
1061                 .out_rot_en_w   = 1920,
1062                 .out_rot_dis_w  = 4224,
1063         },
1064         [2] = {
1065                 .scaler_en_w    = 1920,
1066                 .scaler_dis_w   = 8192,
1067                 .in_rot_en_h    = 1280,
1068                 .in_rot_dis_w   = 8192,
1069                 .out_rot_en_w   = 1280,
1070                 .out_rot_dis_w  = 1920,
1071         },
1072         [3] = {
1073                 .scaler_en_w    = 1920,
1074                 .scaler_dis_w   = 8192,
1075                 .in_rot_en_h    = 1366,
1076                 .in_rot_dis_w   = 8192,
1077                 .out_rot_en_w   = 1366,
1078                 .out_rot_dis_w  = 1920,
1079         },
1080 };
1081
1082 static const struct fimc_variant fimc0_variant_s5p = {
1083         .has_inp_rot     = 1,
1084         .has_out_rot     = 1,
1085         .has_cam_if      = 1,
1086         .min_inp_pixsize = 16,
1087         .min_out_pixsize = 16,
1088         .hor_offs_align  = 8,
1089         .min_vsize_align = 16,
1090         .out_buf_count   = 4,
1091         .pix_limit       = &s5p_pix_limit[0],
1092 };
1093
1094 static const struct fimc_variant fimc2_variant_s5p = {
1095         .has_cam_if      = 1,
1096         .min_inp_pixsize = 16,
1097         .min_out_pixsize = 16,
1098         .hor_offs_align  = 8,
1099         .min_vsize_align = 16,
1100         .out_buf_count   = 4,
1101         .pix_limit       = &s5p_pix_limit[1],
1102 };
1103
1104 static const struct fimc_variant fimc0_variant_s5pv210 = {
1105         .pix_hoff        = 1,
1106         .has_inp_rot     = 1,
1107         .has_out_rot     = 1,
1108         .has_cam_if      = 1,
1109         .min_inp_pixsize = 16,
1110         .min_out_pixsize = 16,
1111         .hor_offs_align  = 8,
1112         .min_vsize_align = 16,
1113         .out_buf_count   = 4,
1114         .pix_limit       = &s5p_pix_limit[1],
1115 };
1116
1117 static const struct fimc_variant fimc1_variant_s5pv210 = {
1118         .pix_hoff        = 1,
1119         .has_inp_rot     = 1,
1120         .has_out_rot     = 1,
1121         .has_cam_if      = 1,
1122         .has_mainscaler_ext = 1,
1123         .min_inp_pixsize = 16,
1124         .min_out_pixsize = 16,
1125         .hor_offs_align  = 1,
1126         .min_vsize_align = 1,
1127         .out_buf_count   = 4,
1128         .pix_limit       = &s5p_pix_limit[2],
1129 };
1130
1131 static const struct fimc_variant fimc2_variant_s5pv210 = {
1132         .has_cam_if      = 1,
1133         .pix_hoff        = 1,
1134         .min_inp_pixsize = 16,
1135         .min_out_pixsize = 16,
1136         .hor_offs_align  = 8,
1137         .min_vsize_align = 16,
1138         .out_buf_count   = 4,
1139         .pix_limit       = &s5p_pix_limit[2],
1140 };
1141
1142 static const struct fimc_variant fimc0_variant_exynos4210 = {
1143         .pix_hoff        = 1,
1144         .has_inp_rot     = 1,
1145         .has_out_rot     = 1,
1146         .has_cam_if      = 1,
1147         .has_cistatus2   = 1,
1148         .has_mainscaler_ext = 1,
1149         .has_alpha       = 1,
1150         .min_inp_pixsize = 16,
1151         .min_out_pixsize = 16,
1152         .hor_offs_align  = 2,
1153         .min_vsize_align = 1,
1154         .out_buf_count   = 32,
1155         .pix_limit       = &s5p_pix_limit[1],
1156 };
1157
1158 static const struct fimc_variant fimc3_variant_exynos4210 = {
1159         .pix_hoff        = 1,
1160         .has_cistatus2   = 1,
1161         .has_mainscaler_ext = 1,
1162         .has_alpha       = 1,
1163         .min_inp_pixsize = 16,
1164         .min_out_pixsize = 16,
1165         .hor_offs_align  = 2,
1166         .min_vsize_align = 1,
1167         .out_buf_count   = 32,
1168         .pix_limit       = &s5p_pix_limit[3],
1169 };
1170
1171 static const struct fimc_variant fimc0_variant_exynos4x12 = {
1172         .pix_hoff               = 1,
1173         .has_inp_rot            = 1,
1174         .has_out_rot            = 1,
1175         .has_cam_if             = 1,
1176         .has_isp_wb             = 1,
1177         .has_cistatus2          = 1,
1178         .has_mainscaler_ext     = 1,
1179         .has_alpha              = 1,
1180         .min_inp_pixsize        = 16,
1181         .min_out_pixsize        = 16,
1182         .hor_offs_align         = 2,
1183         .min_vsize_align        = 1,
1184         .out_buf_count          = 32,
1185         .pix_limit              = &s5p_pix_limit[1],
1186 };
1187
1188 static const struct fimc_variant fimc3_variant_exynos4x12 = {
1189         .pix_hoff               = 1,
1190         .has_cistatus2          = 1,
1191         .has_mainscaler_ext     = 1,
1192         .has_alpha              = 1,
1193         .min_inp_pixsize        = 16,
1194         .min_out_pixsize        = 16,
1195         .hor_offs_align         = 2,
1196         .min_vsize_align        = 1,
1197         .out_buf_count          = 32,
1198         .pix_limit              = &s5p_pix_limit[3],
1199 };
1200
1201 /* S5PC100 */
1202 static const struct fimc_drvdata fimc_drvdata_s5p = {
1203         .variant = {
1204                 [0] = &fimc0_variant_s5p,
1205                 [1] = &fimc0_variant_s5p,
1206                 [2] = &fimc2_variant_s5p,
1207         },
1208         .num_entities = 3,
1209         .lclk_frequency = 133000000UL,
1210 };
1211
1212 /* S5PV210, S5PC110 */
1213 static const struct fimc_drvdata fimc_drvdata_s5pv210 = {
1214         .variant = {
1215                 [0] = &fimc0_variant_s5pv210,
1216                 [1] = &fimc1_variant_s5pv210,
1217                 [2] = &fimc2_variant_s5pv210,
1218         },
1219         .num_entities = 3,
1220         .lclk_frequency = 166000000UL,
1221 };
1222
1223 /* EXYNOS4210, S5PV310, S5PC210 */
1224 static const struct fimc_drvdata fimc_drvdata_exynos4210 = {
1225         .variant = {
1226                 [0] = &fimc0_variant_exynos4210,
1227                 [1] = &fimc0_variant_exynos4210,
1228                 [2] = &fimc0_variant_exynos4210,
1229                 [3] = &fimc3_variant_exynos4210,
1230         },
1231         .num_entities = 4,
1232         .lclk_frequency = 166000000UL,
1233 };
1234
1235 /* EXYNOS4212, EXYNOS4412 */
1236 static const struct fimc_drvdata fimc_drvdata_exynos4x12 = {
1237         .variant = {
1238                 [0] = &fimc0_variant_exynos4x12,
1239                 [1] = &fimc0_variant_exynos4x12,
1240                 [2] = &fimc0_variant_exynos4x12,
1241                 [3] = &fimc3_variant_exynos4x12,
1242         },
1243         .num_entities = 4,
1244         .lclk_frequency = 166000000UL,
1245 };
1246
1247 static const struct platform_device_id fimc_driver_ids[] = {
1248         {
1249                 .name           = "s5p-fimc",
1250                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1251         }, {
1252                 .name           = "s5pv210-fimc",
1253                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1254         }, {
1255                 .name           = "exynos4-fimc",
1256                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4210,
1257         }, {
1258                 .name           = "exynos4x12-fimc",
1259                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4x12,
1260         },
1261         {},
1262 };
1263 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1264
1265 static const struct dev_pm_ops fimc_pm_ops = {
1266         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1267         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1268 };
1269
1270 static struct platform_driver fimc_driver = {
1271         .probe          = fimc_probe,
1272         .remove         = fimc_remove,
1273         .id_table       = fimc_driver_ids,
1274         .driver = {
1275                 .name   = FIMC_MODULE_NAME,
1276                 .owner  = THIS_MODULE,
1277                 .pm     = &fimc_pm_ops,
1278         }
1279 };
1280
1281 int __init fimc_register_driver(void)
1282 {
1283         return platform_driver_register(&fimc_driver);
1284 }
1285
1286 void __exit fimc_unregister_driver(void)
1287 {
1288         platform_driver_unregister(&fimc_driver);
1289 }