drivers/mfd/rtsx_pcr.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/module.h>
  25 #include <linux/slab.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/highmem.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/delay.h>
  30 #include <linux/idr.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/mfd/core.h>
  33 #include <linux/mfd/rtsx_pci.h>
  34 #include <asm/unaligned.h>
  35
  36 #include "rtsx_pcr.h"
  37
  38 static bool msi_en = true;
  39 module_param(msi_en, bool, S_IRUGO | S_IWUSR);
  40 MODULE_PARM_DESC(msi_en, "Enable MSI");
  41
  42 static DEFINE_IDR(rtsx_pci_idr);
  43 static DEFINE_SPINLOCK(rtsx_pci_lock);
  44
  45 static struct mfd_cell rtsx_pcr_cells[] = {
  46         [RTSX_SD_CARD] = {
  47                 .name = DRV_NAME_RTSX_PCI_SDMMC,
  48         },
  49         [RTSX_MS_CARD] = {
  50                 .name = DRV_NAME_RTSX_PCI_MS,
  51         },
  52 };
  53
  54 static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
  55         { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  56         { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  57         { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  58         { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  59         { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  60         { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
  61         { 0, }
  62 };
  63
  64 MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
  65
  66 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
  67 {
  68         /* If pci device removed, don't queue idle work any more */
  69         if (pcr->remove_pci)
  70                 return;
  71
  72         if (pcr->state != PDEV_STAT_RUN) {
  73                 pcr->state = PDEV_STAT_RUN;
  74                 if (pcr->ops->enable_auto_blink)
  75                         pcr->ops->enable_auto_blink(pcr);
  76         }
  77
  78         mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
  79 }
  80 EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
  81
  82 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
  83 {
  84         int i;
  85         u32 val = HAIMR_WRITE_START;
  86
  87         val |= (u32)(addr & 0x3FFF) << 16;
  88         val |= (u32)mask << 8;
  89         val |= (u32)data;
  90
  91         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
  92
  93         for (i = 0; i < MAX_RW_REG_CNT; i++) {
  94                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
  95                 if ((val & HAIMR_TRANS_END) == 0) {
  96                         if (data != (u8)val)
  97                                 return -EIO;
  98                         return 0;
  99                 }
 100         }
 101
 102         return -ETIMEDOUT;
 103 }
 104 EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
 105
 106 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
 107 {
 108         u32 val = HAIMR_READ_START;
 109         int i;
 110
 111         val |= (u32)(addr & 0x3FFF) << 16;
 112         rtsx_pci_writel(pcr, RTSX_HAIMR, val);
 113
 114         for (i = 0; i < MAX_RW_REG_CNT; i++) {
 115                 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
 116                 if ((val & HAIMR_TRANS_END) == 0)
 117                         break;
 118         }
 119
 120         if (i >= MAX_RW_REG_CNT)
 121                 return -ETIMEDOUT;
 122
 123         if (data)
 124                 *data = (u8)(val & 0xFF);
 125
 126         return 0;
 127 }
 128 EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
 129
 130 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
 131 {
 132         int err, i, finished = 0;
 133         u8 tmp;
 134
 135         rtsx_pci_init_cmd(pcr);
 136
 137         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
 138         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
 139         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 140         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
 141
 142         err = rtsx_pci_send_cmd(pcr, 100);
 143         if (err < 0)
 144                 return err;
 145
 146         for (i = 0; i < 100000; i++) {
 147                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 148                 if (err < 0)
 149                         return err;
 150
 151                 if (!(tmp & 0x80)) {
 152                         finished = 1;
 153                         break;
 154                 }
 155         }
 156
 157         if (!finished)
 158                 return -ETIMEDOUT;
 159
 160         return 0;
 161 }
 162 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
 163
 164 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
 165 {
 166         int err, i, finished = 0;
 167         u16 data;
 168         u8 *ptr, tmp;
 169
 170         rtsx_pci_init_cmd(pcr);
 171
 172         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
 173         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
 174
 175         err = rtsx_pci_send_cmd(pcr, 100);
 176         if (err < 0)
 177                 return err;
 178
 179         for (i = 0; i < 100000; i++) {
 180                 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
 181                 if (err < 0)
 182                         return err;
 183
 184                 if (!(tmp & 0x80)) {
 185                         finished = 1;
 186                         break;
 187                 }
 188         }
 189
 190         if (!finished)
 191                 return -ETIMEDOUT;
 192
 193         rtsx_pci_init_cmd(pcr);
 194
 195         rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
 196         rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
 197
 198         err = rtsx_pci_send_cmd(pcr, 100);
 199         if (err < 0)
 200                 return err;
 201
 202         ptr = rtsx_pci_get_cmd_data(pcr);
 203         data = ((u16)ptr[1] << 8) | ptr[0];
 204
 205         if (val)
 206                 *val = data;
 207
 208         return 0;
 209 }
 210 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
 211
 212 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
 213 {
 214         rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
 215         rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
 216
 217         rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
 218         rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
 219 }
 220 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
 221
 222 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 223                 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
 224 {
 225         unsigned long flags;
 226         u32 val = 0;
 227         u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
 228
 229         val |= (u32)(cmd_type & 0x03) << 30;
 230         val |= (u32)(reg_addr & 0x3FFF) << 16;
 231         val |= (u32)mask << 8;
 232         val |= (u32)data;
 233
 234         spin_lock_irqsave(&pcr->lock, flags);
 235         ptr += pcr->ci;
 236         if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
 237                 put_unaligned_le32(val, ptr);
 238                 ptr++;
 239                 pcr->ci++;
 240         }
 241         spin_unlock_irqrestore(&pcr->lock, flags);
 242 }
 243 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
 244
 245 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
 246 {
 247         u32 val = 1 << 31;
 248
 249         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 250
 251         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 252         /* Hardware Auto Response */
 253         val |= 0x40000000;
 254         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 255 }
 256 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
 257
 258 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
 259 {
 260         struct completion trans_done;
 261         u32 val = 1 << 31;
 262         long timeleft;
 263         unsigned long flags;
 264         int err = 0;
 265
 266         spin_lock_irqsave(&pcr->lock, flags);
 267
 268         /* set up data structures for the wakeup system */
 269         pcr->done = &trans_done;
 270         pcr->trans_result = TRANS_NOT_READY;
 271         init_completion(&trans_done);
 272
 273         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 274
 275         val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
 276         /* Hardware Auto Response */
 277         val |= 0x40000000;
 278         rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
 279
 280         spin_unlock_irqrestore(&pcr->lock, flags);
 281
 282         /* Wait for TRANS_OK_INT */
 283         timeleft = wait_for_completion_interruptible_timeout(
 284                         &trans_done, msecs_to_jiffies(timeout));
 285         if (timeleft <= 0) {
 286                 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 287                                 __func__, __LINE__);
 288                 err = -ETIMEDOUT;
 289                 goto finish_send_cmd;
 290         }
 291
 292         spin_lock_irqsave(&pcr->lock, flags);
 293         if (pcr->trans_result == TRANS_RESULT_FAIL)
 294                 err = -EINVAL;
 295         else if (pcr->trans_result == TRANS_RESULT_OK)
 296                 err = 0;
 297         else if (pcr->trans_result == TRANS_NO_DEVICE)
 298                 err = -ENODEV;
 299         spin_unlock_irqrestore(&pcr->lock, flags);
 300
 301 finish_send_cmd:
 302         spin_lock_irqsave(&pcr->lock, flags);
 303         pcr->done = NULL;
 304         spin_unlock_irqrestore(&pcr->lock, flags);
 305
 306         if ((err < 0) && (err != -ENODEV))
 307                 rtsx_pci_stop_cmd(pcr);
 308
 309         if (pcr->finish_me)
 310                 complete(pcr->finish_me);
 311
 312         return err;
 313 }
 314 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
 315
 316 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
 317                 dma_addr_t addr, unsigned int len, int end)
 318 {
 319         u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
 320         u64 val;
 321         u8 option = SG_VALID | SG_TRANS_DATA;
 322
 323         dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
 324                         (unsigned int)addr, len);
 325
 326         if (end)
 327                 option |= SG_END;
 328         val = ((u64)addr << 32) | ((u64)len << 12) | option;
 329
 330         put_unaligned_le64(val, ptr);
 331         pcr->sgi++;
 332 }
 333
 334 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 335                 int num_sg, bool read, int timeout)
 336 {
 337         struct completion trans_done;
 338         u8 dir;
 339         int err = 0, i, count;
 340         long timeleft;
 341         unsigned long flags;
 342         struct scatterlist *sg;
 343         enum dma_data_direction dma_dir;
 344         u32 val;
 345         dma_addr_t addr;
 346         unsigned int len;
 347
 348         dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
 349
 350         /* don't transfer data during abort processing */
 351         if (pcr->remove_pci)
 352                 return -EINVAL;
 353
 354         if ((sglist == NULL) || (num_sg <= 0))
 355                 return -EINVAL;
 356
 357         if (read) {
 358                 dir = DEVICE_TO_HOST;
 359                 dma_dir = DMA_FROM_DEVICE;
 360         } else {
 361                 dir = HOST_TO_DEVICE;
 362                 dma_dir = DMA_TO_DEVICE;
 363         }
 364
 365         count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 366         if (count < 1) {
 367                 dev_err(&(pcr->pci->dev), "scatterlist map failed\n");
 368                 return -EINVAL;
 369         }
 370         dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
 371
 372         val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
 373         pcr->sgi = 0;
 374         for_each_sg(sglist, sg, count, i) {
 375                 addr = sg_dma_address(sg);
 376                 len = sg_dma_len(sg);
 377                 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
 378         }
 379
 380         spin_lock_irqsave(&pcr->lock, flags);
 381
 382         pcr->done = &trans_done;
 383         pcr->trans_result = TRANS_NOT_READY;
 384         init_completion(&trans_done);
 385         rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
 386         rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
 387
 388         spin_unlock_irqrestore(&pcr->lock, flags);
 389
 390         timeleft = wait_for_completion_interruptible_timeout(
 391                         &trans_done, msecs_to_jiffies(timeout));
 392         if (timeleft <= 0) {
 393                 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
 394                                 __func__, __LINE__);
 395                 err = -ETIMEDOUT;
 396                 goto out;
 397         }
 398
 399         spin_lock_irqsave(&pcr->lock, flags);
 400
 401         if (pcr->trans_result == TRANS_RESULT_FAIL)
 402                 err = -EINVAL;
 403         else if (pcr->trans_result == TRANS_NO_DEVICE)
 404                 err = -ENODEV;
 405
 406         spin_unlock_irqrestore(&pcr->lock, flags);
 407
 408 out:
 409         spin_lock_irqsave(&pcr->lock, flags);
 410         pcr->done = NULL;
 411         spin_unlock_irqrestore(&pcr->lock, flags);
 412
 413         dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir);
 414
 415         if ((err < 0) && (err != -ENODEV))
 416                 rtsx_pci_stop_cmd(pcr);
 417
 418         if (pcr->finish_me)
 419                 complete(pcr->finish_me);
 420
 421         return err;
 422 }
 423 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
 424
 425 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 426 {
 427         int err;
 428         int i, j;
 429         u16 reg;
 430         u8 *ptr;
 431
 432         if (buf_len > 512)
 433                 buf_len = 512;
 434
 435         ptr = buf;
 436         reg = PPBUF_BASE2;
 437         for (i = 0; i < buf_len / 256; i++) {
 438                 rtsx_pci_init_cmd(pcr);
 439
 440                 for (j = 0; j < 256; j++)
 441                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 442
 443                 err = rtsx_pci_send_cmd(pcr, 250);
 444                 if (err < 0)
 445                         return err;
 446
 447                 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
 448                 ptr += 256;
 449         }
 450
 451         if (buf_len % 256) {
 452                 rtsx_pci_init_cmd(pcr);
 453
 454                 for (j = 0; j < buf_len % 256; j++)
 455                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
 456
 457                 err = rtsx_pci_send_cmd(pcr, 250);
 458                 if (err < 0)
 459                         return err;
 460         }
 461
 462         memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
 463
 464         return 0;
 465 }
 466 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
 467
 468 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
 469 {
 470         int err;
 471         int i, j;
 472         u16 reg;
 473         u8 *ptr;
 474
 475         if (buf_len > 512)
 476                 buf_len = 512;
 477
 478         ptr = buf;
 479         reg = PPBUF_BASE2;
 480         for (i = 0; i < buf_len / 256; i++) {
 481                 rtsx_pci_init_cmd(pcr);
 482
 483                 for (j = 0; j < 256; j++) {
 484                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 485                                         reg++, 0xFF, *ptr);
 486                         ptr++;
 487                 }
 488
 489                 err = rtsx_pci_send_cmd(pcr, 250);
 490                 if (err < 0)
 491                         return err;
 492         }
 493
 494         if (buf_len % 256) {
 495                 rtsx_pci_init_cmd(pcr);
 496
 497                 for (j = 0; j < buf_len % 256; j++) {
 498                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 499                                         reg++, 0xFF, *ptr);
 500                         ptr++;
 501                 }
 502
 503                 err = rtsx_pci_send_cmd(pcr, 250);
 504                 if (err < 0)
 505                         return err;
 506         }
 507
 508         return 0;
 509 }
 510 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
 511
 512 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
 513 {
 514         int err;
 515
 516         rtsx_pci_init_cmd(pcr);
 517
 518         while (*tbl & 0xFFFF0000) {
 519                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 520                                 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
 521                 tbl++;
 522         }
 523
 524         err = rtsx_pci_send_cmd(pcr, 100);
 525         if (err < 0)
 526                 return err;
 527
 528         return 0;
 529 }
 530
 531 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
 532 {
 533         const u32 *tbl;
 534
 535         if (card == RTSX_SD_CARD)
 536                 tbl = pcr->sd_pull_ctl_enable_tbl;
 537         else if (card == RTSX_MS_CARD)
 538                 tbl = pcr->ms_pull_ctl_enable_tbl;
 539         else
 540                 return -EINVAL;
 541
 542         return rtsx_pci_set_pull_ctl(pcr, tbl);
 543 }
 544 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
 545
 546 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
 547 {
 548         const u32 *tbl;
 549
 550         if (card == RTSX_SD_CARD)
 551                 tbl = pcr->sd_pull_ctl_disable_tbl;
 552         else if (card == RTSX_MS_CARD)
 553                 tbl = pcr->ms_pull_ctl_disable_tbl;
 554         else
 555                 return -EINVAL;
 556
 557
 558         return rtsx_pci_set_pull_ctl(pcr, tbl);
 559 }
 560 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
 561
 562 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
 563 {
 564         pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
 565
 566         if (pcr->num_slots > 1)
 567                 pcr->bier |= MS_INT_EN;
 568
 569         /* Enable Bus Interrupt */
 570         rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
 571
 572         dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
 573 }
 574
 575 static inline u8 double_ssc_depth(u8 depth)
 576 {
 577         return ((depth > 1) ? (depth - 1) : depth);
 578 }
 579
 580 static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
 581 {
 582         if (div > CLK_DIV_1) {
 583                 if (ssc_depth > (div - 1))
 584                         ssc_depth -= (div - 1);
 585                 else
 586                         ssc_depth = SSC_DEPTH_4M;
 587         }
 588
 589         return ssc_depth;
 590 }
 591
 592 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 593                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
 594 {
 595         int err, clk;
 596         u8 n, clk_divider, mcu_cnt, div;
 597         u8 depth[] = {
 598                 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
 599                 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
 600                 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
 601                 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
 602                 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
 603         };
 604
 605         if (initial_mode) {
 606                 /* We use 250k(around) here, in initial stage */
 607                 clk_divider = SD_CLK_DIVIDE_128;
 608                 card_clock = 30000000;
 609         } else {
 610                 clk_divider = SD_CLK_DIVIDE_0;
 611         }
 612         err = rtsx_pci_write_register(pcr, SD_CFG1,
 613                         SD_CLK_DIVIDE_MASK, clk_divider);
 614         if (err < 0)
 615                 return err;
 616
 617         card_clock /= 1000000;
 618         dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
 619
 620         clk = card_clock;
 621         if (!initial_mode && double_clk)
 622                 clk = card_clock * 2;
 623         dev_dbg(&(pcr->pci->dev),
 624                         "Internal SSC clock: %dMHz (cur_clock = %d)\n",
 625                         clk, pcr->cur_clock);
 626
 627         if (clk == pcr->cur_clock)
 628                 return 0;
 629
 630         if (pcr->ops->conv_clk_and_div_n)
 631                 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
 632         else
 633                 n = (u8)(clk - 2);
 634         if ((clk <= 2) || (n > MAX_DIV_N_PCR))
 635                 return -EINVAL;
 636
 637         mcu_cnt = (u8)(125/clk + 3);
 638         if (mcu_cnt > 15)
 639                 mcu_cnt = 15;
 640
 641         /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
 642         div = CLK_DIV_1;
 643         while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
 644                 if (pcr->ops->conv_clk_and_div_n) {
 645                         int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
 646                                         DIV_N_TO_CLK) * 2;
 647                         n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
 648                                         CLK_TO_DIV_N);
 649                 } else {
 650                         n = (n + 2) * 2 - 2;
 651                 }
 652                 div++;
 653         }
 654         dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
 655
 656         ssc_depth = depth[ssc_depth];
 657         if (double_clk)
 658                 ssc_depth = double_ssc_depth(ssc_depth);
 659
 660         ssc_depth = revise_ssc_depth(ssc_depth, div);
 661         dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
 662
 663         rtsx_pci_init_cmd(pcr);
 664         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 665                         CLK_LOW_FREQ, CLK_LOW_FREQ);
 666         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
 667                         0xFF, (div << 4) | mcu_cnt);
 668         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
 669         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
 670                         SSC_DEPTH_MASK, ssc_depth);
 671         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
 672         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 673         if (vpclk) {
 674                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 675                                 PHASE_NOT_RESET, 0);
 676                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
 677                                 PHASE_NOT_RESET, PHASE_NOT_RESET);
 678         }
 679
 680         err = rtsx_pci_send_cmd(pcr, 2000);
 681         if (err < 0)
 682                 return err;
 683
 684         /* Wait SSC clock stable */
 685         udelay(10);
 686         err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
 687         if (err < 0)
 688                 return err;
 689
 690         pcr->cur_clock = clk;
 691         return 0;
 692 }
 693 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
 694
 695 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
 696 {
 697         if (pcr->ops->card_power_on)
 698                 return pcr->ops->card_power_on(pcr, card);
 699
 700         return 0;
 701 }
 702 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
 703
 704 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
 705 {
 706         if (pcr->ops->card_power_off)
 707                 return pcr->ops->card_power_off(pcr, card);
 708
 709         return 0;
 710 }
 711 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
 712
 713 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
 714 {
 715         unsigned int cd_mask[] = {
 716                 [RTSX_SD_CARD] = SD_EXIST,
 717                 [RTSX_MS_CARD] = MS_EXIST
 718         };
 719
 720         if (!pcr->ms_pmos) {
 721                 /* When using single PMOS, accessing card is not permitted
 722                  * if the existing card is not the designated one.
 723                  */
 724                 if (pcr->card_exist & (~cd_mask[card]))
 725                         return -EIO;
 726         }
 727
 728         return 0;
 729 }
 730 EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
 731
 732 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 733 {
 734         if (pcr->ops->switch_output_voltage)
 735                 return pcr->ops->switch_output_voltage(pcr, voltage);
 736
 737         return 0;
 738 }
 739 EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
 740
 741 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
 742 {
 743         unsigned int val;
 744
 745         val = rtsx_pci_readl(pcr, RTSX_BIPR);
 746         if (pcr->ops->cd_deglitch)
 747                 val = pcr->ops->cd_deglitch(pcr);
 748
 749         return val;
 750 }
 751 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
 752
 753 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
 754 {
 755         struct completion finish;
 756
 757         pcr->finish_me = &finish;
 758         init_completion(&finish);
 759
 760         if (pcr->done)
 761                 complete(pcr->done);
 762
 763         if (!pcr->remove_pci)
 764                 rtsx_pci_stop_cmd(pcr);
 765
 766         wait_for_completion_interruptible_timeout(&finish,
 767                         msecs_to_jiffies(2));
 768         pcr->finish_me = NULL;
 769 }
 770 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
 771
 772 static void rtsx_pci_card_detect(struct work_struct *work)
 773 {
 774         struct delayed_work *dwork;
 775         struct rtsx_pcr *pcr;
 776         unsigned long flags;
 777         unsigned int card_detect = 0, card_inserted, card_removed;
 778         u32 irq_status;
 779
 780         dwork = to_delayed_work(work);
 781         pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
 782
 783         dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 784
 785         mutex_lock(&pcr->pcr_mutex);
 786         spin_lock_irqsave(&pcr->lock, flags);
 787
 788         irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
 789         dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
 790
 791         irq_status &= CARD_EXIST;
 792         card_inserted = pcr->card_inserted & irq_status;
 793         card_removed = pcr->card_removed;
 794         pcr->card_inserted = 0;
 795         pcr->card_removed = 0;
 796
 797         spin_unlock_irqrestore(&pcr->lock, flags);
 798
 799         if (card_inserted || card_removed) {
 800                 dev_dbg(&(pcr->pci->dev),
 801                                 "card_inserted: 0x%x, card_removed: 0x%x\n",
 802                                 card_inserted, card_removed);
 803
 804                 if (pcr->ops->cd_deglitch)
 805                         card_inserted = pcr->ops->cd_deglitch(pcr);
 806
 807                 card_detect = card_inserted | card_removed;
 808
 809                 pcr->card_exist |= card_inserted;
 810                 pcr->card_exist &= ~card_removed;
 811         }
 812
 813         mutex_unlock(&pcr->pcr_mutex);
 814
 815         if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
 816                 pcr->slots[RTSX_SD_CARD].card_event(
 817                                 pcr->slots[RTSX_SD_CARD].p_dev);
 818         if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
 819                 pcr->slots[RTSX_MS_CARD].card_event(
 820                                 pcr->slots[RTSX_MS_CARD].p_dev);
 821 }
 822
 823 static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
 824 {
 825         struct rtsx_pcr *pcr = dev_id;
 826         u32 int_reg;
 827
 828         if (!pcr)
 829                 return IRQ_NONE;
 830
 831         spin_lock(&pcr->lock);
 832
 833         int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
 834         /* Clear interrupt flag */
 835         rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
 836         if ((int_reg & pcr->bier) == 0) {
 837                 spin_unlock(&pcr->lock);
 838                 return IRQ_NONE;
 839         }
 840         if (int_reg == 0xFFFFFFFF) {
 841                 spin_unlock(&pcr->lock);
 842                 return IRQ_HANDLED;
 843         }
 844
 845         int_reg &= (pcr->bier | 0x7FFFFF);
 846
 847         if (int_reg & SD_INT) {
 848                 if (int_reg & SD_EXIST) {
 849                         pcr->card_inserted |= SD_EXIST;
 850                 } else {
 851                         pcr->card_removed |= SD_EXIST;
 852                         pcr->card_inserted &= ~SD_EXIST;
 853                 }
 854         }
 855
 856         if (int_reg & MS_INT) {
 857                 if (int_reg & MS_EXIST) {
 858                         pcr->card_inserted |= MS_EXIST;
 859                 } else {
 860                         pcr->card_removed |= MS_EXIST;
 861                         pcr->card_inserted &= ~MS_EXIST;
 862                 }
 863         }
 864
 865         if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
 866                 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
 867                         pcr->trans_result = TRANS_RESULT_FAIL;
 868                         if (pcr->done)
 869                                 complete(pcr->done);
 870                 } else if (int_reg & TRANS_OK_INT) {
 871                         pcr->trans_result = TRANS_RESULT_OK;
 872                         if (pcr->done)
 873                                 complete(pcr->done);
 874                 }
 875         }
 876
 877         if (pcr->card_inserted || pcr->card_removed)
 878                 schedule_delayed_work(&pcr->carddet_work,
 879                                 msecs_to_jiffies(200));
 880
 881         spin_unlock(&pcr->lock);
 882         return IRQ_HANDLED;
 883 }
 884
 885 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
 886 {
 887         dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
 888                         __func__, pcr->msi_en, pcr->pci->irq);
 889
 890         if (request_irq(pcr->pci->irq, rtsx_pci_isr,
 891                         pcr->msi_en ? 0 : IRQF_SHARED,
 892                         DRV_NAME_RTSX_PCI, pcr)) {
 893                 dev_err(&(pcr->pci->dev),
 894                         "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
 895                         pcr->pci->irq);
 896                 return -1;
 897         }
 898
 899         pcr->irq = pcr->pci->irq;
 900         pci_intx(pcr->pci, !pcr->msi_en);
 901
 902         return 0;
 903 }
 904
 905 static void rtsx_pci_idle_work(struct work_struct *work)
 906 {
 907         struct delayed_work *dwork = to_delayed_work(work);
 908         struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
 909
 910         dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
 911
 912         mutex_lock(&pcr->pcr_mutex);
 913
 914         pcr->state = PDEV_STAT_IDLE;
 915
 916         if (pcr->ops->disable_auto_blink)
 917                 pcr->ops->disable_auto_blink(pcr);
 918         if (pcr->ops->turn_off_led)
 919                 pcr->ops->turn_off_led(pcr);
 920
 921         mutex_unlock(&pcr->pcr_mutex);
 922 }
 923
 924 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
 925 {
 926         int err;
 927
 928         rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
 929
 930         rtsx_pci_enable_bus_int(pcr);
 931
 932         /* Power on SSC */
 933         err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
 934         if (err < 0)
 935                 return err;
 936
 937         /* Wait SSC power stable */
 938         udelay(200);
 939
 940         if (pcr->ops->optimize_phy) {
 941                 err = pcr->ops->optimize_phy(pcr);
 942                 if (err < 0)
 943                         return err;
 944         }
 945
 946         rtsx_pci_init_cmd(pcr);
 947
 948         /* Set mcu_cnt to 7 to ensure data can be sampled properly */
 949         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
 950
 951         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
 952         /* Disable card clock */
 953         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
 954         /* Reset ASPM state to default value */
 955         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 956         /* Reset delink mode */
 957         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
 958         /* Card driving select */
 959         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
 960                         0x07, DRIVER_TYPE_D);
 961         /* Enable SSC Clock */
 962         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
 963                         0xFF, SSC_8X_EN | SSC_SEL_4M);
 964         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
 965         /* Disable cd_pwr_save */
 966         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
 967         /* Clear Link Ready Interrupt */
 968         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 969                         LINK_RDY_INT, LINK_RDY_INT);
 970         /* Enlarge the estimation window of PERST# glitch
 971          * to reduce the chance of invalid card interrupt
 972          */
 973         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 974         /* Update RC oscillator to 400k
 975          * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
 976          *                1: 2M  0: 400k
 977          */
 978         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
 979         /* Set interrupt write clear
 980          * bit 1: U_elbi_if_rd_clr_en
 981          *      1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
 982          *      0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
 983          */
 984         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
 985         /* Force CLKREQ# PIN to drive 0 to request clock */
 986         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
 987
 988         err = rtsx_pci_send_cmd(pcr, 100);
 989         if (err < 0)
 990                 return err;
 991
 992         /* Enable clk_request_n to enable clock power management */
 993         rtsx_pci_write_config_byte(pcr, 0x81, 1);
 994         /* Enter L1 when host tx idle */
 995         rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
 996
 997         if (pcr->ops->extra_init_hw) {
 998                 err = pcr->ops->extra_init_hw(pcr);
 999                 if (err < 0)
1000                         return err;
1001         }
1002
1003         /* No CD interrupt if probing driver with card inserted.
1004          * So we need to initialize pcr->card_exist here.
1005          */
1006         if (pcr->ops->cd_deglitch)
1007                 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1008         else
1009                 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1010
1011         return 0;
1012 }
1013
1014 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1015 {
1016         int err;
1017
1018         spin_lock_init(&pcr->lock);
1019         mutex_init(&pcr->pcr_mutex);
1020
1021         switch (PCI_PID(pcr)) {
1022         default:
1023         case 0x5209:
1024                 rts5209_init_params(pcr);
1025                 break;
1026
1027         case 0x5229:
1028                 rts5229_init_params(pcr);
1029                 break;
1030
1031         case 0x5289:
1032                 rtl8411_init_params(pcr);
1033                 break;
1034
1035         case 0x5227:
1036                 rts5227_init_params(pcr);
1037                 break;
1038
1039         case 0x5249:
1040                 rts5249_init_params(pcr);
1041                 break;
1042
1043         case 0x5287:
1044                 rtl8411b_init_params(pcr);
1045                 break;
1046         }
1047
1048         dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1049                         PCI_PID(pcr), pcr->ic_version);
1050
1051         pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1052                         GFP_KERNEL);
1053         if (!pcr->slots)
1054                 return -ENOMEM;
1055
1056         pcr->state = PDEV_STAT_IDLE;
1057         err = rtsx_pci_init_hw(pcr);
1058         if (err < 0) {
1059                 kfree(pcr->slots);
1060                 return err;
1061         }
1062
1063         return 0;
1064 }
1065
1066 static int rtsx_pci_probe(struct pci_dev *pcidev,
1067                           const struct pci_device_id *id)
1068 {
1069         struct rtsx_pcr *pcr;
1070         struct pcr_handle *handle;
1071         u32 base, len;
1072         int ret, i;
1073
1074         dev_dbg(&(pcidev->dev),
1075                 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1076                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1077                 (int)pcidev->revision);
1078
1079         ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1080         if (ret < 0)
1081                 return ret;
1082
1083         ret = pci_enable_device(pcidev);
1084         if (ret)
1085                 return ret;
1086
1087         ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1088         if (ret)
1089                 goto disable;
1090
1091         pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1092         if (!pcr) {
1093                 ret = -ENOMEM;
1094                 goto release_pci;
1095         }
1096
1097         handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1098         if (!handle) {
1099                 ret = -ENOMEM;
1100                 goto free_pcr;
1101         }
1102         handle->pcr = pcr;
1103
1104         idr_preload(GFP_KERNEL);
1105         spin_lock(&rtsx_pci_lock);
1106         ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1107         if (ret >= 0)
1108                 pcr->id = ret;
1109         spin_unlock(&rtsx_pci_lock);
1110         idr_preload_end();
1111         if (ret < 0)
1112                 goto free_handle;
1113
1114         pcr->pci = pcidev;
1115         dev_set_drvdata(&pcidev->dev, handle);
1116
1117         len = pci_resource_len(pcidev, 0);
1118         base = pci_resource_start(pcidev, 0);
1119         pcr->remap_addr = ioremap_nocache(base, len);
1120         if (!pcr->remap_addr) {
1121                 ret = -ENOMEM;
1122                 goto free_host;
1123         }
1124
1125         pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1126                         RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1127                         GFP_KERNEL);
1128         if (pcr->rtsx_resv_buf == NULL) {
1129                 ret = -ENXIO;
1130                 goto unmap;
1131         }
1132         pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1133         pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1134         pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1135         pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1136
1137         pcr->card_inserted = 0;
1138         pcr->card_removed = 0;
1139         INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1140         INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1141
1142         pcr->msi_en = msi_en;
1143         if (pcr->msi_en) {
1144                 ret = pci_enable_msi(pcidev);
1145                 if (ret < 0)
1146                         pcr->msi_en = false;
1147         }
1148
1149         ret = rtsx_pci_acquire_irq(pcr);
1150         if (ret < 0)
1151                 goto disable_msi;
1152
1153         pci_set_master(pcidev);
1154         synchronize_irq(pcr->irq);
1155
1156         ret = rtsx_pci_init_chip(pcr);
1157         if (ret < 0)
1158                 goto disable_irq;
1159
1160         for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1161                 rtsx_pcr_cells[i].platform_data = handle;
1162                 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1163         }
1164         ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1165                         ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1166         if (ret < 0)
1167                 goto disable_irq;
1168
1169         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1170
1171         return 0;
1172
1173 disable_irq:
1174         free_irq(pcr->irq, (void *)pcr);
1175 disable_msi:
1176         if (pcr->msi_en)
1177                 pci_disable_msi(pcr->pci);
1178         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1179                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1180 unmap:
1181         iounmap(pcr->remap_addr);
1182 free_host:
1183         dev_set_drvdata(&pcidev->dev, NULL);
1184 free_handle:
1185         kfree(handle);
1186 free_pcr:
1187         kfree(pcr);
1188 release_pci:
1189         pci_release_regions(pcidev);
1190 disable:
1191         pci_disable_device(pcidev);
1192
1193         return ret;
1194 }
1195
1196 static void rtsx_pci_remove(struct pci_dev *pcidev)
1197 {
1198         struct pcr_handle *handle = pci_get_drvdata(pcidev);
1199         struct rtsx_pcr *pcr = handle->pcr;
1200
1201         pcr->remove_pci = true;
1202
1203         cancel_delayed_work(&pcr->carddet_work);
1204         cancel_delayed_work(&pcr->idle_work);
1205
1206         mfd_remove_devices(&pcidev->dev);
1207
1208         dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1209                         pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1210         free_irq(pcr->irq, (void *)pcr);
1211         if (pcr->msi_en)
1212                 pci_disable_msi(pcr->pci);
1213         iounmap(pcr->remap_addr);
1214
1215         dev_set_drvdata(&pcidev->dev, NULL);
1216         pci_release_regions(pcidev);
1217         pci_disable_device(pcidev);
1218
1219         spin_lock(&rtsx_pci_lock);
1220         idr_remove(&rtsx_pci_idr, pcr->id);
1221         spin_unlock(&rtsx_pci_lock);
1222
1223         kfree(pcr->slots);
1224         kfree(pcr);
1225         kfree(handle);
1226
1227         dev_dbg(&(pcidev->dev),
1228                 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1229                 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1230 }
1231
1232 #ifdef CONFIG_PM
1233
1234 static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1235 {
1236         struct pcr_handle *handle;
1237         struct rtsx_pcr *pcr;
1238         int ret = 0;
1239
1240         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1241
1242         handle = pci_get_drvdata(pcidev);
1243         pcr = handle->pcr;
1244
1245         cancel_delayed_work(&pcr->carddet_work);
1246         cancel_delayed_work(&pcr->idle_work);
1247
1248         mutex_lock(&pcr->pcr_mutex);
1249
1250         if (pcr->ops->turn_off_led)
1251                 pcr->ops->turn_off_led(pcr);
1252
1253         rtsx_pci_writel(pcr, RTSX_BIER, 0);
1254         pcr->bier = 0;
1255
1256         rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1257         rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02);
1258
1259         pci_save_state(pcidev);
1260         pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1261         pci_disable_device(pcidev);
1262         pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1263
1264         mutex_unlock(&pcr->pcr_mutex);
1265         return ret;
1266 }
1267
1268 static int rtsx_pci_resume(struct pci_dev *pcidev)
1269 {
1270         struct pcr_handle *handle;
1271         struct rtsx_pcr *pcr;
1272         int ret = 0;
1273
1274         dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1275
1276         handle = pci_get_drvdata(pcidev);
1277         pcr = handle->pcr;
1278
1279         mutex_lock(&pcr->pcr_mutex);
1280
1281         pci_set_power_state(pcidev, PCI_D0);
1282         pci_restore_state(pcidev);
1283         ret = pci_enable_device(pcidev);
1284         if (ret)
1285                 goto out;
1286         pci_set_master(pcidev);
1287
1288         ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1289         if (ret)
1290                 goto out;
1291
1292         ret = rtsx_pci_init_hw(pcr);
1293         if (ret)
1294                 goto out;
1295
1296         schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1297
1298 out:
1299         mutex_unlock(&pcr->pcr_mutex);
1300         return ret;
1301 }
1302
1303 #else /* CONFIG_PM */
1304
1305 #define rtsx_pci_suspend NULL
1306 #define rtsx_pci_resume NULL
1307
1308 #endif /* CONFIG_PM */
1309
1310 static struct pci_driver rtsx_pci_driver = {
1311         .name = DRV_NAME_RTSX_PCI,
1312         .id_table = rtsx_pci_ids,
1313         .probe = rtsx_pci_probe,
1314         .remove = rtsx_pci_remove,
1315         .suspend = rtsx_pci_suspend,
1316         .resume = rtsx_pci_resume,
1317 };
1318 module_pci_driver(rtsx_pci_driver);
1319
1320 MODULE_LICENSE("GPL");
1321 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1322 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");