2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci_regs.h>
11 #include <linux/pci_ids.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/sort.h>
17 #include <linux/pci.h>
19 #include <linux/delay.h>
21 #include <asm/msi_bitmap.h>
22 #include <asm/pnv-pci.h>
30 #define CXL_PCI_VSEC_ID 0x1280
31 #define CXL_VSEC_MIN_SIZE 0x80
33 #define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
38 #define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
41 #define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43 #define CXL_STATUS_SECOND_PORT 0x80
44 #define CXL_STATUS_MSI_X_FULL 0x40
45 #define CXL_STATUS_MSI_X_SINGLE 0x20
46 #define CXL_STATUS_FLASH_RW 0x08
47 #define CXL_STATUS_FLASH_RO 0x04
48 #define CXL_STATUS_LOADABLE_AFU 0x02
49 #define CXL_STATUS_LOADABLE_PSL 0x01
50 /* If we see these features we won't try to use the card */
51 #define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
54 #define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56 #define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
58 #define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
59 pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
60 #define CXL_VSEC_PROTOCOL_MASK 0xe0
61 #define CXL_VSEC_PROTOCOL_1024TB 0x80
62 #define CXL_VSEC_PROTOCOL_512TB 0x40
63 #define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
64 #define CXL_VSEC_PROTOCOL_ENABLE 0x01
66 #define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0xc, dest)
68 #define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xe, dest)
70 #define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
71 pci_read_config_byte(dev, vsec + 0xf, dest)
72 #define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
73 pci_read_config_word(dev, vsec + 0x10, dest)
75 #define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
76 pci_read_config_byte(dev, vsec + 0x13, dest)
77 #define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
78 pci_write_config_byte(dev, vsec + 0x13, val)
79 #define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
80 #define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
81 #define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
83 #define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x20, dest)
85 #define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x24, dest)
87 #define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x28, dest)
89 #define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
90 pci_read_config_dword(dev, vsec + 0x2c, dest)
93 /* This works a little different than the p1/p2 register accesses to make it
94 * easier to pull out individual fields */
95 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
96 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
97 #define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
98 #define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
100 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
101 #define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
102 #define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
103 #define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
104 #define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
105 #define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
106 #define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
107 #define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
108 #define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
109 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
110 #define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
112 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
113 #define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
114 #define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
115 #define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
116 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
117 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
118 #define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
119 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
121 static const struct pci_device_id cxl_pci_tbl[] = {
122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
126 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
127 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
128 { PCI_DEVICE_CLASS(0x120000, ~0), },
132 MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
136 * Mostly using these wrappers to avoid confusion:
137 * priv 1 is BAR2, while priv 2 is BAR0
139 static inline resource_size_t p1_base(struct pci_dev *dev)
141 return pci_resource_start(dev, 2);
144 static inline resource_size_t p1_size(struct pci_dev *dev)
146 return pci_resource_len(dev, 2);
149 static inline resource_size_t p2_base(struct pci_dev *dev)
151 return pci_resource_start(dev, 0);
154 static inline resource_size_t p2_size(struct pci_dev *dev)
156 return pci_resource_len(dev, 0);
159 static int find_cxl_vsec(struct pci_dev *dev)
164 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
165 pci_read_config_word(dev, vsec + 0x4, &val);
166 if (val == CXL_PCI_VSEC_ID)
173 static void dump_cxl_config_space(struct pci_dev *dev)
178 dev_info(&dev->dev, "dump_cxl_config_space\n");
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
181 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
183 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
185 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
187 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
188 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
189 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
190 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
191 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
193 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
194 p1_base(dev), p1_size(dev));
195 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
196 p2_base(dev), p2_size(dev));
197 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
198 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
200 if (!(vsec = find_cxl_vsec(dev)))
203 #define show_reg(name, what) \
204 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
206 pci_read_config_dword(dev, vsec + 0x0, &val);
207 show_reg("Cap ID", (val >> 0) & 0xffff);
208 show_reg("Cap Ver", (val >> 16) & 0xf);
209 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
210 pci_read_config_dword(dev, vsec + 0x4, &val);
211 show_reg("VSEC ID", (val >> 0) & 0xffff);
212 show_reg("VSEC Rev", (val >> 16) & 0xf);
213 show_reg("VSEC Length", (val >> 20) & 0xfff);
214 pci_read_config_dword(dev, vsec + 0x8, &val);
215 show_reg("Num AFUs", (val >> 0) & 0xff);
216 show_reg("Status", (val >> 8) & 0xff);
217 show_reg("Mode Control", (val >> 16) & 0xff);
218 show_reg("Reserved", (val >> 24) & 0xff);
219 pci_read_config_dword(dev, vsec + 0xc, &val);
220 show_reg("PSL Rev", (val >> 0) & 0xffff);
221 show_reg("CAIA Ver", (val >> 16) & 0xffff);
222 pci_read_config_dword(dev, vsec + 0x10, &val);
223 show_reg("Base Image Rev", (val >> 0) & 0xffff);
224 show_reg("Reserved", (val >> 16) & 0x0fff);
225 show_reg("Image Control", (val >> 28) & 0x3);
226 show_reg("Reserved", (val >> 30) & 0x1);
227 show_reg("Image Loaded", (val >> 31) & 0x1);
229 pci_read_config_dword(dev, vsec + 0x14, &val);
230 show_reg("Reserved", val);
231 pci_read_config_dword(dev, vsec + 0x18, &val);
232 show_reg("Reserved", val);
233 pci_read_config_dword(dev, vsec + 0x1c, &val);
234 show_reg("Reserved", val);
236 pci_read_config_dword(dev, vsec + 0x20, &val);
237 show_reg("AFU Descriptor Offset", val);
238 pci_read_config_dword(dev, vsec + 0x24, &val);
239 show_reg("AFU Descriptor Size", val);
240 pci_read_config_dword(dev, vsec + 0x28, &val);
241 show_reg("Problem State Offset", val);
242 pci_read_config_dword(dev, vsec + 0x2c, &val);
243 show_reg("Problem State Size", val);
245 pci_read_config_dword(dev, vsec + 0x30, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x34, &val);
248 show_reg("Reserved", val);
249 pci_read_config_dword(dev, vsec + 0x38, &val);
250 show_reg("Reserved", val);
251 pci_read_config_dword(dev, vsec + 0x3c, &val);
252 show_reg("Reserved", val);
254 pci_read_config_dword(dev, vsec + 0x40, &val);
255 show_reg("PSL Programming Port", val);
256 pci_read_config_dword(dev, vsec + 0x44, &val);
257 show_reg("PSL Programming Control", val);
259 pci_read_config_dword(dev, vsec + 0x48, &val);
260 show_reg("Reserved", val);
261 pci_read_config_dword(dev, vsec + 0x4c, &val);
262 show_reg("Reserved", val);
264 pci_read_config_dword(dev, vsec + 0x50, &val);
265 show_reg("Flash Address Register", val);
266 pci_read_config_dword(dev, vsec + 0x54, &val);
267 show_reg("Flash Size Register", val);
268 pci_read_config_dword(dev, vsec + 0x58, &val);
269 show_reg("Flash Status/Control Register", val);
270 pci_read_config_dword(dev, vsec + 0x58, &val);
271 show_reg("Flash Data Port", val);
276 static void dump_afu_descriptor(struct cxl_afu *afu)
278 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
281 #define show_reg(name, what) \
282 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
284 val = AFUD_READ_INFO(afu);
285 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
286 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
287 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
288 show_reg("req_prog_mode", val & 0xffffULL);
289 afu_cr_num = AFUD_NUM_CRS(val);
291 val = AFUD_READ(afu, 0x8);
292 show_reg("Reserved", val);
293 val = AFUD_READ(afu, 0x10);
294 show_reg("Reserved", val);
295 val = AFUD_READ(afu, 0x18);
296 show_reg("Reserved", val);
298 val = AFUD_READ_CR(afu);
299 show_reg("Reserved", (val >> (63-7)) & 0xff);
300 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
301 afu_cr_len = AFUD_CR_LEN(val) * 256;
303 val = AFUD_READ_CR_OFF(afu);
305 show_reg("AFU_CR_offset", val);
307 val = AFUD_READ_PPPSA(afu);
308 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
309 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
311 val = AFUD_READ_PPPSA_OFF(afu);
312 show_reg("PerProcessPSA_offset", val);
314 val = AFUD_READ_EB(afu);
315 show_reg("Reserved", (val >> (63-7)) & 0xff);
316 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
318 val = AFUD_READ_EB_OFF(afu);
319 show_reg("AFU_EB_offset", val);
321 for (i = 0; i < afu_cr_num; i++) {
322 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
323 show_reg("CR Vendor", val & 0xffff);
324 show_reg("CR Device", (val >> 16) & 0xffff);
329 #define P8_CAPP_UNIT0_ID 0xBA
330 #define P8_CAPP_UNIT1_ID 0XBE
331 #define P9_CAPP_UNIT0_ID 0xC0
332 #define P9_CAPP_UNIT1_ID 0xE0
334 static int get_phb_index(struct device_node *np, u32 *phb_index)
336 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
341 static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
345 * - For chips other than POWER8NVL, we only have CAPP 0,
346 * irrespective of which PHB is used.
347 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
348 * CAPP 1 is attached to PHB1.
350 if (cxl_is_power8()) {
351 if (!pvr_version_is(PVR_POWER8NVL))
352 return P8_CAPP_UNIT0_ID;
355 return P8_CAPP_UNIT0_ID;
358 return P8_CAPP_UNIT1_ID;
363 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
364 * PEC1 (PHB1 - PHB2). No capi mode
365 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
367 if (cxl_is_power9()) {
369 return P9_CAPP_UNIT0_ID;
372 return P9_CAPP_UNIT1_ID;
378 static int calc_capp_routing(struct pci_dev *dev, u64 *chipid,
379 u32 *phb_index, u64 *capp_unit_id)
382 struct device_node *np;
385 if (!(np = pnv_pci_get_phb_node(dev)))
388 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
389 np = of_get_next_parent(np);
393 *chipid = be32_to_cpup(prop);
395 rc = get_phb_index(np, phb_index);
397 pr_err("cxl: invalid phb index\n");
401 *capp_unit_id = get_capp_unit_id(np, *phb_index);
403 if (!*capp_unit_id) {
404 pr_err("cxl: invalid capp unit id\n");
411 static int init_implementation_adapter_regs_psl9(struct cxl *adapter, struct pci_dev *dev)
413 u64 xsl_dsnctl, psl_fircntl;
419 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
424 * CAPI Identifier bits [0:7]
425 * bit 61:60 MSI bits --> 0
426 * bit 59 TVT selector --> 0
430 * Tell XSL where to route data to.
431 * The field chipid should match the PHB CAPI_CMPM register
433 xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */
434 xsl_dsnctl |= (capp_unit_id << (63-15));
436 /* nMMU_ID Defaults to: b’000001001’*/
437 xsl_dsnctl |= ((u64)0x09 << (63-28));
439 if (!(cxl_is_power9_dd1())) {
441 * Used to identify CAPI packets which should be sorted into
442 * the Non-Blocking queues by the PHB. This field should match
443 * the PHB PBL_NBW_CMPM register
444 * nbwind=0x03, bits [57:58], must include capi indicator.
445 * Not supported on P9 DD1.
447 xsl_dsnctl |= ((u64)0x03 << (63-47));
450 * Upper 16b address bits of ASB_Notify messages sent to the
451 * system. Need to match the PHB’s ASN Compare/Mask Register.
452 * Not supported on P9 DD1.
454 xsl_dsnctl |= ((u64)0x04 << (63-55));
457 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
459 /* Set fir_cntl to recommended value for production env */
460 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
461 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
462 psl_fircntl |= 0x1ULL; /* ce_thresh */
463 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
465 /* vccredits=0x1 pcklat=0x4 */
466 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
469 * For debugging with trace arrays.
470 * Configure RX trace 0 segmented mode.
471 * Configure CT trace 0 segmented mode.
472 * Configure LA0 trace 0 segmented mode.
473 * Configure LA1 trace 0 segmented mode.
475 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
476 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
477 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
478 cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
481 * A response to an ASB_Notify request is returned by the
482 * system as an MMIO write to the address defined in
483 * the PSL_TNR_ADDR register
488 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
490 /* allocate the apc machines */
491 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
493 /* Disable vc dd1 fix */
494 if (cxl_is_power9_dd1())
495 cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
500 static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
502 u64 psl_dsnctl, psl_fircntl;
508 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
512 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
513 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
514 /* Tell PSL where to route data to */
515 psl_dsnctl |= (chipid << (63-5));
516 psl_dsnctl |= (capp_unit_id << (63-13));
518 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
519 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
520 /* snoop write mask */
521 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
522 /* set fir_cntl to recommended value for production env */
523 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
524 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
525 psl_fircntl |= 0x1ULL; /* ce_thresh */
526 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
527 /* for debugging with trace arrays */
528 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
533 static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)
541 rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
545 /* Tell XSL where to route data to */
546 xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
547 xsl_dsnctl |= (capp_unit_id << (63-13));
548 cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
554 #define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
555 #define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
556 /* For the PSL this is a multiple for 0 < n <= 7: */
557 #define PSL_2048_250MHZ_CYCLES 1
559 static void write_timebase_ctrl_psl9(struct cxl *adapter)
561 cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
562 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
565 static void write_timebase_ctrl_psl8(struct cxl *adapter)
567 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
568 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
572 #define TBSYNC_ENA (1ULL << 63)
573 /* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
574 #define XSL_2000_CLOCKS 1
575 #define XSL_4000_CLOCKS 2
576 #define XSL_8000_CLOCKS 3
578 static void write_timebase_ctrl_xsl(struct cxl *adapter)
580 cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
583 TBSYNC_CNT(XSL_4000_CLOCKS));
586 static u64 timebase_read_psl9(struct cxl *adapter)
588 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
591 static u64 timebase_read_psl8(struct cxl *adapter)
593 return cxl_p1_read(adapter, CXL_PSL_Timebase);
596 static u64 timebase_read_xsl(struct cxl *adapter)
598 return cxl_p1_read(adapter, CXL_XSL_Timebase);
601 static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
605 unsigned int retry = 0;
606 struct device_node *np;
608 adapter->psl_timebase_synced = false;
610 if (!(np = pnv_pci_get_phb_node(dev)))
613 /* Do not fail when CAPP timebase sync is not supported by OPAL */
615 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
617 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
623 * Setup PSL Timebase Control and Status register
624 * with the recommended Timebase Sync Count value
626 adapter->native->sl_ops->write_timebase_ctrl(adapter);
628 /* Enable PSL Timebase */
629 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
630 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
632 /* Wait until CORE TB and PSL TB difference <= 16usecs */
636 dev_info(&dev->dev, "PSL timebase can't synchronize\n");
639 psl_tb = adapter->native->sl_ops->timebase_read(adapter);
640 delta = mftb() - psl_tb;
643 } while (tb_to_ns(delta) > 16000);
645 adapter->psl_timebase_synced = true;
649 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
654 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
656 /* read/write masks for this slice */
657 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
658 /* APC read/write masks for this slice */
659 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
660 /* for debugging with trace arrays */
661 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
662 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
667 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
670 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
672 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
675 int cxl_update_image_control(struct cxl *adapter)
677 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
682 if (!(vsec = find_cxl_vsec(dev))) {
683 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
687 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
688 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
692 if (adapter->perst_loads_image)
693 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
695 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
697 if (adapter->perst_select_user)
698 image_state |= CXL_VSEC_PERST_SELECT_USER;
700 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
702 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
703 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
710 int cxl_pci_alloc_one_irq(struct cxl *adapter)
712 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
714 return pnv_cxl_alloc_hwirqs(dev, 1);
717 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
719 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
721 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
724 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
725 struct cxl *adapter, unsigned int num)
727 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
729 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
732 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
735 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
737 pnv_cxl_release_hwirq_ranges(irqs, dev);
740 static int setup_cxl_bars(struct pci_dev *dev)
742 /* Safety check in case we get backported to < 3.17 without M64 */
743 if ((p1_base(dev) < 0x100000000ULL) ||
744 (p2_base(dev) < 0x100000000ULL)) {
745 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
750 * BAR 4/5 has a special meaning for CXL and must be programmed with a
751 * special value corresponding to the CXL protocol address range.
752 * For POWER 8/9 that means bits 48:49 must be set to 10
754 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
755 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
760 #ifdef CONFIG_CXL_BIMODAL
762 struct cxl_switch_work {
764 struct work_struct work;
769 static void switch_card_to_cxl(struct work_struct *work)
771 struct cxl_switch_work *switch_work =
772 container_of(work, struct cxl_switch_work, work);
773 struct pci_dev *dev = switch_work->dev;
774 struct pci_bus *bus = dev->bus;
775 struct pci_controller *hose = pci_bus_to_host(bus);
776 struct pci_dev *bridge;
777 struct pnv_php_slot *php_slot;
782 dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
783 bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
786 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
790 php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
792 dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
793 "information. You may need to upgrade "
794 "skiboot. Aborting.\n");
798 rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
800 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
805 /* Release the reference obtained in cxl_check_and_switch_mode() */
808 dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
809 pci_lock_rescan_remove();
810 pci_hp_remove_devices(bridge->subordinate);
811 pci_unlock_rescan_remove();
813 /* Switch the CXL protocol on the card */
814 if (switch_work->mode == CXL_BIMODE_CXL) {
815 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
816 val &= ~CXL_VSEC_PROTOCOL_MASK;
817 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
818 rc = pnv_cxl_enable_phb_kernel_api(hose, true);
820 dev_err(&bus->dev, "cxl: Failed to enable kernel API"
821 " on real PHB, aborting\n");
825 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
829 rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
831 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
836 * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
837 * we must wait 100ms after this mode switch before touching PCIe config
843 * Hot reset to cause the card to come back in cxl mode. A
844 * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
845 * in skiboot, so we use a hot reset instead.
847 * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
848 * guaranteed to sit directly under the root port, and setting the reset
849 * state on a device directly under the root port is equivalent to doing
850 * it on the root port iself.
852 dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
853 pci_set_pcie_reset_state(bridge, pcie_hot_reset);
854 pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
856 dev_dbg(&bus->dev, "cxl: Offlining slot\n");
857 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
859 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
863 dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
864 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
866 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
870 pci_lock_rescan_remove();
871 pci_hp_add_devices(bridge->subordinate);
872 pci_unlock_rescan_remove();
874 dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
879 /* Release the reference obtained in cxl_check_and_switch_mode() */
885 int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
887 struct cxl_switch_work *work;
891 if (!cpu_has_feature(CPU_FTR_HVMODE))
895 vsec = find_cxl_vsec(dev);
897 dev_info(&dev->dev, "CXL VSEC not found\n");
902 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
904 dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
908 if (mode == CXL_BIMODE_PCI) {
909 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
910 dev_info(&dev->dev, "Card is already in PCI mode\n");
914 * TODO: Before it's safe to switch the card back to PCI mode
915 * we need to disable the CAPP and make sure any cachelines the
916 * card holds have been flushed out. Needs skiboot support.
918 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
922 if (val & CXL_VSEC_PROTOCOL_ENABLE) {
923 dev_info(&dev->dev, "Card is already in CXL mode\n");
927 dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
928 "to switch to CXL mode\n");
930 work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
938 INIT_WORK(&work->work, switch_card_to_cxl);
940 schedule_work(&work->work);
943 * We return a failure now to abort the driver init. Once the
944 * link has been cycled and the card is in cxl mode we will
945 * come back (possibly using the generic cxl driver), but
946 * return success as the card should then be in cxl mode.
948 * TODO: What if the card comes back in PCI mode even after
949 * the switch? Don't want to spin endlessly.
953 EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
955 #endif /* CONFIG_CXL_BIMODAL */
957 static int setup_cxl_protocol_area(struct pci_dev *dev)
961 int vsec = find_cxl_vsec(dev);
964 dev_info(&dev->dev, "CXL VSEC not found\n");
968 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
970 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
974 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
975 dev_err(&dev->dev, "Card not in CAPI mode!\n");
979 if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
980 val &= ~CXL_VSEC_PROTOCOL_MASK;
981 val |= CXL_VSEC_PROTOCOL_256TB;
982 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
984 dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
992 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
994 u64 p1n_base, p2n_base, afu_desc;
995 const u64 p1n_size = 0x100;
996 const u64 p2n_size = 0x1000;
998 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
999 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
1000 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
1001 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
1003 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
1005 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
1008 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
1014 iounmap(afu->p2n_mmio);
1016 iounmap(afu->native->p1n_mmio);
1018 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
1022 static void pci_unmap_slice_regs(struct cxl_afu *afu)
1024 if (afu->p2n_mmio) {
1025 iounmap(afu->p2n_mmio);
1026 afu->p2n_mmio = NULL;
1028 if (afu->native->p1n_mmio) {
1029 iounmap(afu->native->p1n_mmio);
1030 afu->native->p1n_mmio = NULL;
1032 if (afu->native->afu_desc_mmio) {
1033 iounmap(afu->native->afu_desc_mmio);
1034 afu->native->afu_desc_mmio = NULL;
1038 void cxl_pci_release_afu(struct device *dev)
1040 struct cxl_afu *afu = to_cxl_afu(dev);
1042 pr_devel("%s\n", __func__);
1044 idr_destroy(&afu->contexts_idr);
1045 cxl_release_spa(afu);
1051 /* Expects AFU struct to have recently been zeroed out */
1052 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
1056 val = AFUD_READ_INFO(afu);
1057 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
1058 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
1059 afu->crs_num = AFUD_NUM_CRS(val);
1061 if (AFUD_AFU_DIRECTED(val))
1062 afu->modes_supported |= CXL_MODE_DIRECTED;
1063 if (AFUD_DEDICATED_PROCESS(val))
1064 afu->modes_supported |= CXL_MODE_DEDICATED;
1065 if (AFUD_TIME_SLICED(val))
1066 afu->modes_supported |= CXL_MODE_TIME_SLICED;
1068 val = AFUD_READ_PPPSA(afu);
1069 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
1070 afu->psa = AFUD_PPPSA_PSA(val);
1071 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
1072 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
1074 val = AFUD_READ_CR(afu);
1075 afu->crs_len = AFUD_CR_LEN(val) * 256;
1076 afu->crs_offset = AFUD_READ_CR_OFF(afu);
1079 /* eb_len is in multiple of 4K */
1080 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
1081 afu->eb_offset = AFUD_READ_EB_OFF(afu);
1083 /* eb_off is 4K aligned so lower 12 bits are always zero */
1084 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
1086 "Invalid AFU error buffer offset %Lx\n",
1089 "Ignoring AFU error buffer in the descriptor\n");
1090 /* indicate that no afu buffer exists */
1097 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
1102 if (afu->psa && afu->adapter->ps_size <
1103 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
1104 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
1108 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
1109 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
1111 for (i = 0; i < afu->crs_num; i++) {
1112 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
1113 if (rc || val == 0) {
1114 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
1119 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
1121 * We could also check this for the dedicated process model
1122 * since the architecture indicates it should be set to 1, but
1123 * in that case we ignore the value and I'd rather not risk
1124 * breaking any existing dedicated process AFUs that left it as
1125 * 0 (not that I'm aware of any). It is clearly an error for an
1126 * AFU directed AFU to set this to 0, and would have previously
1127 * triggered a bug resulting in the maximum not being enforced
1128 * at all since idr_alloc treats 0 as no maximum.
1130 dev_err(&afu->dev, "AFU does not support any processes\n");
1137 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
1142 * Clear out any regs that contain either an IVTE or address or may be
1143 * waiting on an acknowledgment to try to be a bit safer as we bring
1146 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1147 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1148 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1149 if (cxl_ops->afu_reset(afu))
1151 if (cxl_afu_disable(afu))
1153 if (cxl_psl_purge(afu))
1156 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1157 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1158 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1160 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1161 if (reg & CXL_PSL9_DSISR_An_TF)
1162 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1164 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1166 if (afu->adapter->native->sl_ops->register_serr_irq) {
1167 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1169 if (reg & ~0x000000007fffffff)
1170 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1171 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1174 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1176 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1177 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1183 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
1188 * Clear out any regs that contain either an IVTE or address or may be
1189 * waiting on an acknowledgement to try to be a bit safer as we bring
1192 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1193 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1194 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1195 if (cxl_ops->afu_reset(afu))
1197 if (cxl_afu_disable(afu))
1199 if (cxl_psl_purge(afu))
1202 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1203 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1204 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1205 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1206 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1207 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1208 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1209 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1210 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1211 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1212 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1213 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1215 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1216 if (reg & CXL_PSL_DSISR_TRANS)
1217 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1219 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1221 if (afu->adapter->native->sl_ops->register_serr_irq) {
1222 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1225 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1226 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1229 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1231 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1232 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1238 #define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1241 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1242 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1243 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1245 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1246 loff_t off, size_t count)
1248 loff_t aligned_start, aligned_end;
1249 size_t aligned_length;
1251 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1253 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1256 /* calculate aligned read window */
1257 count = min((size_t)(afu->eb_len - off), count);
1258 aligned_start = round_down(off, 8);
1259 aligned_end = round_up(off + count, 8);
1260 aligned_length = aligned_end - aligned_start;
1262 /* max we can copy in one read is PAGE_SIZE */
1263 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1264 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1265 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1268 /* use bounce buffer for copy */
1269 tbuf = (void *)__get_free_page(GFP_TEMPORARY);
1273 /* perform aligned read from the mmio region */
1274 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1275 memcpy(buf, tbuf + (off & 0x7), count);
1277 free_page((unsigned long)tbuf);
1282 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1286 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1289 if (adapter->native->sl_ops->sanitise_afu_regs) {
1290 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1295 /* We need to reset the AFU before we can read the AFU descriptor */
1296 if ((rc = cxl_ops->afu_reset(afu)))
1300 dump_afu_descriptor(afu);
1302 if ((rc = cxl_read_afu_descriptor(afu)))
1305 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1308 if (adapter->native->sl_ops->afu_regs_init)
1309 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1312 if (adapter->native->sl_ops->register_serr_irq)
1313 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1316 if ((rc = cxl_native_register_psl_irq(afu)))
1319 atomic_set(&afu->configured_state, 0);
1323 if (adapter->native->sl_ops->release_serr_irq)
1324 adapter->native->sl_ops->release_serr_irq(afu);
1326 pci_unmap_slice_regs(afu);
1330 static void pci_deconfigure_afu(struct cxl_afu *afu)
1333 * It's okay to deconfigure when AFU is already locked, otherwise wait
1334 * until there are no readers
1336 if (atomic_read(&afu->configured_state) != -1) {
1337 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1340 cxl_native_release_psl_irq(afu);
1341 if (afu->adapter->native->sl_ops->release_serr_irq)
1342 afu->adapter->native->sl_ops->release_serr_irq(afu);
1343 pci_unmap_slice_regs(afu);
1346 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
1348 struct cxl_afu *afu;
1351 afu = cxl_alloc_afu(adapter, slice);
1355 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1359 mutex_init(&afu->native->spa_mutex);
1361 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1363 goto err_free_native;
1365 rc = pci_configure_afu(afu, adapter, dev);
1367 goto err_free_native;
1369 /* Don't care if this fails */
1370 cxl_debugfs_afu_add(afu);
1373 * After we call this function we must not free the afu directly, even
1374 * if it returns an error!
1376 if ((rc = cxl_register_afu(afu)))
1379 if ((rc = cxl_sysfs_afu_add(afu)))
1382 adapter->afu[afu->slice] = afu;
1384 if ((rc = cxl_pci_vphb_add(afu)))
1385 dev_info(&afu->dev, "Can't register vPHB\n");
1390 pci_deconfigure_afu(afu);
1391 cxl_debugfs_afu_remove(afu);
1392 device_unregister(&afu->dev);
1403 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1405 pr_devel("%s\n", __func__);
1410 cxl_pci_vphb_remove(afu);
1411 cxl_sysfs_afu_remove(afu);
1412 cxl_debugfs_afu_remove(afu);
1414 spin_lock(&afu->adapter->afu_list_lock);
1415 afu->adapter->afu[afu->slice] = NULL;
1416 spin_unlock(&afu->adapter->afu_list_lock);
1418 cxl_context_detach_all(afu);
1419 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1421 pci_deconfigure_afu(afu);
1422 device_unregister(&afu->dev);
1425 int cxl_pci_reset(struct cxl *adapter)
1427 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1430 if (adapter->perst_same_image) {
1432 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1436 dev_info(&dev->dev, "CXL reset\n");
1439 * The adapter is about to be reset, so ignore errors.
1440 * Not supported on P9 DD1
1442 if ((cxl_is_power8()) || (!(cxl_is_power9_dd1())))
1443 cxl_data_cache_flush(adapter);
1445 /* pcie_warm_reset requests a fundamental pci reset which includes a
1446 * PERST assert/deassert. PERST triggers a loading of the image
1447 * if "user" or "factory" is selected in sysfs */
1448 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1449 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1456 static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1458 if (pci_request_region(dev, 2, "priv 2 regs"))
1460 if (pci_request_region(dev, 0, "priv 1 regs"))
1463 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
1464 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1466 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
1469 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
1475 iounmap(adapter->native->p1_mmio);
1476 adapter->native->p1_mmio = NULL;
1478 pci_release_region(dev, 0);
1480 pci_release_region(dev, 2);
1485 static void cxl_unmap_adapter_regs(struct cxl *adapter)
1487 if (adapter->native->p1_mmio) {
1488 iounmap(adapter->native->p1_mmio);
1489 adapter->native->p1_mmio = NULL;
1490 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1492 if (adapter->native->p2_mmio) {
1493 iounmap(adapter->native->p2_mmio);
1494 adapter->native->p2_mmio = NULL;
1495 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1499 static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1502 u32 afu_desc_off, afu_desc_size;
1503 u32 ps_off, ps_size;
1507 if (!(vsec = find_cxl_vsec(dev))) {
1508 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
1512 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1513 if (vseclen < CXL_VSEC_MIN_SIZE) {
1514 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
1518 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1519 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1520 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1521 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1522 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1523 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1524 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1525 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
1526 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
1528 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1529 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1530 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1531 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1532 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1534 /* Convert everything to bytes, because there is NO WAY I'd look at the
1535 * code a month later and forget what units these are in ;-) */
1536 adapter->native->ps_off = ps_off * 64 * 1024;
1537 adapter->ps_size = ps_size * 64 * 1024;
1538 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1539 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
1541 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1542 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1548 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1549 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1550 * reported. Mask this error in the Uncorrectable Error Mask Register.
1552 * The upper nibble of the PSL revision is used to distinguish between
1553 * different cards. The affected ones have it set to 0.
1555 static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1560 if (adapter->psl_rev & 0xf000)
1562 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1564 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1565 if (data & PCI_ERR_UNC_MALF_TLP)
1566 if (data & PCI_ERR_UNC_INTN)
1568 data |= PCI_ERR_UNC_MALF_TLP;
1569 data |= PCI_ERR_UNC_INTN;
1570 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1573 static bool cxl_compatible_caia_version(struct cxl *adapter)
1575 if (cxl_is_power8() && (adapter->caia_major == 1))
1578 if (cxl_is_power9() && (adapter->caia_major == 2))
1584 static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1586 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1589 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
1590 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
1594 if (!cxl_compatible_caia_version(adapter)) {
1595 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1596 adapter->caia_major);
1600 if (!adapter->slices) {
1601 /* Once we support dynamic reprogramming we can use the card if
1602 * it supports loadable AFUs */
1603 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
1607 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
1608 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
1612 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
1613 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
1614 "available in BAR2: 0x%llx > 0x%llx\n",
1615 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
1622 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1624 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1627 static void cxl_release_adapter(struct device *dev)
1629 struct cxl *adapter = to_cxl_adapter(dev);
1631 pr_devel("cxl_release_adapter\n");
1633 cxl_remove_adapter_nr(adapter);
1635 kfree(adapter->native);
1639 #define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1641 static int sanitise_adapter_regs(struct cxl *adapter)
1645 /* Clear PSL tberror bit by writing 1 to it */
1646 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
1648 if (adapter->native->sl_ops->invalidate_all) {
1649 /* do not invalidate ERAT entries when not reloading on PERST */
1650 if (cxl_is_power9() && (adapter->perst_loads_image))
1652 rc = adapter->native->sl_ops->invalidate_all(adapter);
1658 /* This should contain *only* operations that can safely be done in
1659 * both creation and recovery.
1661 static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
1665 adapter->dev.parent = &dev->dev;
1666 adapter->dev.release = cxl_release_adapter;
1667 pci_set_drvdata(dev, adapter);
1669 rc = pci_enable_device(dev);
1671 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1675 if ((rc = cxl_read_vsec(adapter, dev)))
1678 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
1681 cxl_fixup_malformed_tlp(adapter, dev);
1683 if ((rc = setup_cxl_bars(dev)))
1686 if ((rc = setup_cxl_protocol_area(dev)))
1689 if ((rc = cxl_update_image_control(adapter)))
1692 if ((rc = cxl_map_adapter_regs(adapter, dev)))
1695 if ((rc = sanitise_adapter_regs(adapter)))
1698 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
1701 /* Required for devices using CAPP DMA mode, harmless for others */
1702 pci_set_master(dev);
1704 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
1707 /* If recovery happened, the last step is to turn on snooping.
1708 * In the non-recovery case this has no effect */
1709 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1712 /* Ignore error, adapter init is not dependant on timebase sync */
1713 cxl_setup_psl_timebase(adapter, dev);
1715 if ((rc = cxl_native_register_psl_err_irq(adapter)))
1721 cxl_unmap_adapter_regs(adapter);
1726 static void cxl_deconfigure_adapter(struct cxl *adapter)
1728 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1730 cxl_native_release_psl_err_irq(adapter);
1731 cxl_unmap_adapter_regs(adapter);
1733 pci_disable_device(pdev);
1736 static const struct cxl_service_layer_ops psl9_ops = {
1737 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1738 .invalidate_all = cxl_invalidate_all_psl9,
1739 .afu_regs_init = init_implementation_afu_regs_psl9,
1740 .sanitise_afu_regs = sanitise_afu_regs_psl9,
1741 .register_serr_irq = cxl_native_register_serr_irq,
1742 .release_serr_irq = cxl_native_release_serr_irq,
1743 .handle_interrupt = cxl_irq_psl9,
1744 .fail_irq = cxl_fail_irq_psl,
1745 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1746 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1747 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1748 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1749 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1750 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1751 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
1752 .debugfs_stop_trace = cxl_stop_trace_psl9,
1753 .write_timebase_ctrl = write_timebase_ctrl_psl9,
1754 .timebase_read = timebase_read_psl9,
1755 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1756 .needs_reset_before_disable = true,
1759 static const struct cxl_service_layer_ops psl8_ops = {
1760 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1761 .invalidate_all = cxl_invalidate_all_psl8,
1762 .afu_regs_init = init_implementation_afu_regs_psl8,
1763 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1764 .register_serr_irq = cxl_native_register_serr_irq,
1765 .release_serr_irq = cxl_native_release_serr_irq,
1766 .handle_interrupt = cxl_irq_psl8,
1767 .fail_irq = cxl_fail_irq_psl,
1768 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1769 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1770 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1771 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1772 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1773 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1774 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
1775 .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
1776 .debugfs_stop_trace = cxl_stop_trace_psl8,
1777 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1778 .timebase_read = timebase_read_psl8,
1779 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1780 .needs_reset_before_disable = true,
1783 static const struct cxl_service_layer_ops xsl_ops = {
1784 .adapter_regs_init = init_implementation_adapter_regs_xsl,
1785 .invalidate_all = cxl_invalidate_all_psl8,
1786 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1787 .handle_interrupt = cxl_irq_psl8,
1788 .fail_irq = cxl_fail_irq_psl,
1789 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1790 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1791 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1792 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1793 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
1794 .write_timebase_ctrl = write_timebase_ctrl_xsl,
1795 .timebase_read = timebase_read_xsl,
1796 .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
1799 static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1801 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
1803 dev_info(&dev->dev, "Device uses an XSL\n");
1804 adapter->native->sl_ops = &xsl_ops;
1805 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
1807 if (cxl_is_power8()) {
1808 dev_info(&dev->dev, "Device uses a PSL8\n");
1809 adapter->native->sl_ops = &psl8_ops;
1811 dev_info(&dev->dev, "Device uses a PSL9\n");
1812 adapter->native->sl_ops = &psl9_ops;
1818 static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
1820 struct cxl *adapter;
1823 adapter = cxl_alloc_adapter();
1825 return ERR_PTR(-ENOMEM);
1827 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1828 if (!adapter->native) {
1833 set_sl_ops(adapter, dev);
1835 /* Set defaults for parameters which need to persist over
1836 * configure/reconfigure
1838 adapter->perst_loads_image = true;
1839 adapter->perst_same_image = false;
1841 rc = cxl_configure_adapter(adapter, dev);
1843 pci_disable_device(dev);
1847 /* Don't care if this one fails: */
1848 cxl_debugfs_adapter_add(adapter);
1851 * After we call this function we must not free the adapter directly,
1852 * even if it returns an error!
1854 if ((rc = cxl_register_adapter(adapter)))
1857 if ((rc = cxl_sysfs_adapter_add(adapter)))
1860 /* Release the context lock as adapter is configured */
1861 cxl_adapter_context_unlock(adapter);
1866 /* This should mirror cxl_remove_adapter, except without the
1869 cxl_debugfs_adapter_remove(adapter);
1870 cxl_deconfigure_adapter(adapter);
1871 device_unregister(&adapter->dev);
1875 cxl_release_adapter(&adapter->dev);
1879 static void cxl_pci_remove_adapter(struct cxl *adapter)
1881 pr_devel("cxl_remove_adapter\n");
1883 cxl_sysfs_adapter_remove(adapter);
1884 cxl_debugfs_adapter_remove(adapter);
1887 * Flush adapter datacache as its about to be removed.
1888 * Not supported on P9 DD1.
1890 if ((cxl_is_power8()) || (!(cxl_is_power9_dd1())))
1891 cxl_data_cache_flush(adapter);
1893 cxl_deconfigure_adapter(adapter);
1895 device_unregister(&adapter->dev);
1898 #define CXL_MAX_PCIEX_PARENT 2
1900 static int cxl_slot_is_switched(struct pci_dev *dev)
1902 struct device_node *np;
1906 if (!(np = pci_device_to_OF_node(dev))) {
1907 pr_err("cxl: np = NULL\n");
1912 np = of_get_next_parent(np);
1913 prop = of_get_property(np, "device_type", NULL);
1914 if (!prop || strcmp((char *)prop, "pciex"))
1919 return (depth > CXL_MAX_PCIEX_PARENT);
1922 bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
1924 if (!cpu_has_feature(CPU_FTR_HVMODE))
1927 if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
1929 * CAPP DMA mode is technically supported on regular P8, but
1930 * will EEH if the card attempts to access memory < 4GB, which
1931 * we cannot realistically avoid. We might be able to work
1932 * around the issue, but until then return unsupported:
1937 if (cxl_slot_is_switched(dev))
1941 * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
1942 * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
1943 * served basis, which is racy to check from here. If we need to
1944 * support this in future we might need to consider having this
1945 * function effectively reserve it ahead of time.
1947 * Currently, the only user of this API is the Mellanox CX4, which is
1948 * only supported on P8NVL due to the above mentioned limitation of
1949 * CAPP DMA mode and therefore does not need to worry about this. If the
1950 * issue with CAPP DMA mode is later worked around on P8 we might need
1956 EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
1959 static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1961 struct cxl *adapter;
1965 if (cxl_pci_is_vphb_device(dev)) {
1966 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1970 if (cxl_slot_is_switched(dev)) {
1971 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1975 if (cxl_is_power9() && !radix_enabled()) {
1976 dev_info(&dev->dev, "Only Radix mode supported\n");
1981 dump_cxl_config_space(dev);
1983 adapter = cxl_pci_init_adapter(dev);
1984 if (IS_ERR(adapter)) {
1985 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1986 return PTR_ERR(adapter);
1989 for (slice = 0; slice < adapter->slices; slice++) {
1990 if ((rc = pci_init_afu(adapter, slice, dev))) {
1991 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
1995 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1997 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
2000 if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
2001 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
2006 static void cxl_remove(struct pci_dev *dev)
2008 struct cxl *adapter = pci_get_drvdata(dev);
2009 struct cxl_afu *afu;
2013 * Lock to prevent someone grabbing a ref through the adapter list as
2014 * we are removing it
2016 for (i = 0; i < adapter->slices; i++) {
2017 afu = adapter->afu[i];
2018 cxl_pci_remove_afu(afu);
2020 cxl_pci_remove_adapter(adapter);
2023 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
2024 pci_channel_state_t state)
2026 struct pci_dev *afu_dev;
2027 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2028 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2030 /* There should only be one entry, but go through the list
2033 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2034 if (!afu_dev->driver)
2037 afu_dev->error_state = state;
2039 if (afu_dev->driver->err_handler)
2040 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
2042 /* Disconnect trumps all, NONE trumps NEED_RESET */
2043 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2044 result = PCI_ERS_RESULT_DISCONNECT;
2045 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2046 (result == PCI_ERS_RESULT_NEED_RESET))
2047 result = PCI_ERS_RESULT_NONE;
2052 static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
2053 pci_channel_state_t state)
2055 struct cxl *adapter = pci_get_drvdata(pdev);
2056 struct cxl_afu *afu;
2057 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET, afu_result;
2060 /* At this point, we could still have an interrupt pending.
2061 * Let's try to get them out of the way before they do
2062 * anything we don't like.
2066 /* If we're permanently dead, give up. */
2067 if (state == pci_channel_io_perm_failure) {
2068 for (i = 0; i < adapter->slices; i++) {
2069 afu = adapter->afu[i];
2071 * Tell the AFU drivers; but we don't care what they
2072 * say, we're going away.
2074 if (afu->phb != NULL)
2075 cxl_vphb_error_detected(afu, state);
2077 return PCI_ERS_RESULT_DISCONNECT;
2080 /* Are we reflashing?
2082 * If we reflash, we could come back as something entirely
2083 * different, including a non-CAPI card. As such, by default
2084 * we don't participate in the process. We'll be unbound and
2085 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
2088 * However, this isn't the entire story: for reliablity
2089 * reasons, we usually want to reflash the FPGA on PERST in
2090 * order to get back to a more reliable known-good state.
2092 * This causes us a bit of a problem: if we reflash we can't
2093 * trust that we'll come back the same - we could have a new
2094 * image and been PERSTed in order to load that
2095 * image. However, most of the time we actually *will* come
2096 * back the same - for example a regular EEH event.
2098 * Therefore, we allow the user to assert that the image is
2099 * indeed the same and that we should continue on into EEH
2102 if (adapter->perst_loads_image && !adapter->perst_same_image) {
2103 /* TODO take the PHB out of CXL mode */
2104 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
2105 return PCI_ERS_RESULT_NONE;
2109 * At this point, we want to try to recover. We'll always
2110 * need a complete slot reset: we don't trust any other reset.
2112 * Now, we go through each AFU:
2113 * - We send the driver, if bound, an error_detected callback.
2114 * We expect it to clean up, but it can also tell us to give
2115 * up and permanently detach the card. To simplify things, if
2116 * any bound AFU driver doesn't support EEH, we give up on EEH.
2118 * - We detach all contexts associated with the AFU. This
2119 * does not free them, but puts them into a CLOSED state
2120 * which causes any the associated files to return useful
2121 * errors to userland. It also unmaps, but does not free,
2124 * - We clean up our side: releasing and unmapping resources we hold
2125 * so we can wire them up again when the hardware comes back up.
2127 * Driver authors should note:
2129 * - Any contexts you create in your kernel driver (except
2130 * those associated with anonymous file descriptors) are
2131 * your responsibility to free and recreate. Likewise with
2132 * any attached resources.
2134 * - We will take responsibility for re-initialising the
2135 * device context (the one set up for you in
2136 * cxl_pci_enable_device_hook and accessed through
2137 * cxl_get_context). If you've attached IRQs or other
2138 * resources to it, they remains yours to free.
2140 * You can call the same functions to release resources as you
2141 * normally would: we make sure that these functions continue
2142 * to work when the hardware is down.
2146 * 1) If you normally free all your resources at the end of
2147 * each request, or if you use anonymous FDs, your
2148 * error_detected callback can simply set a flag to tell
2149 * your driver not to start any new calls. You can then
2150 * clear the flag in the resume callback.
2152 * 2) If you normally allocate your resources on startup:
2153 * * Set a flag in error_detected as above.
2154 * * Let CXL detach your contexts.
2155 * * In slot_reset, free the old resources and allocate new ones.
2156 * * In resume, clear the flag to allow things to start.
2158 for (i = 0; i < adapter->slices; i++) {
2159 afu = adapter->afu[i];
2161 afu_result = cxl_vphb_error_detected(afu, state);
2163 cxl_context_detach_all(afu);
2164 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2165 pci_deconfigure_afu(afu);
2167 /* Disconnect trumps all, NONE trumps NEED_RESET */
2168 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2169 result = PCI_ERS_RESULT_DISCONNECT;
2170 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2171 (result == PCI_ERS_RESULT_NEED_RESET))
2172 result = PCI_ERS_RESULT_NONE;
2175 /* should take the context lock here */
2176 if (cxl_adapter_context_lock(adapter) != 0)
2177 dev_warn(&adapter->dev,
2178 "Couldn't take context lock with %d active-contexts\n",
2179 atomic_read(&adapter->contexts_num));
2181 cxl_deconfigure_adapter(adapter);
2186 static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
2188 struct cxl *adapter = pci_get_drvdata(pdev);
2189 struct cxl_afu *afu;
2190 struct cxl_context *ctx;
2191 struct pci_dev *afu_dev;
2192 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
2193 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
2196 if (cxl_configure_adapter(adapter, pdev))
2200 * Unlock context activation for the adapter. Ideally this should be
2201 * done in cxl_pci_resume but cxlflash module tries to activate the
2202 * master context as part of slot_reset callback.
2204 cxl_adapter_context_unlock(adapter);
2206 for (i = 0; i < adapter->slices; i++) {
2207 afu = adapter->afu[i];
2209 if (pci_configure_afu(afu, adapter, pdev))
2212 if (cxl_afu_select_best_mode(afu))
2215 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2216 /* Reset the device context.
2217 * TODO: make this less disruptive
2219 ctx = cxl_get_context(afu_dev);
2221 if (ctx && cxl_release_context(ctx))
2224 ctx = cxl_dev_context_init(afu_dev);
2228 afu_dev->dev.archdata.cxl_ctx = ctx;
2230 if (cxl_ops->afu_check_and_enable(afu))
2233 afu_dev->error_state = pci_channel_io_normal;
2235 /* If there's a driver attached, allow it to
2236 * chime in on recovery. Drivers should check
2237 * if everything has come back OK, but
2238 * shouldn't start new work until we call
2239 * their resume function.
2241 if (!afu_dev->driver)
2244 if (afu_dev->driver->err_handler &&
2245 afu_dev->driver->err_handler->slot_reset)
2246 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2248 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2249 result = PCI_ERS_RESULT_DISCONNECT;
2255 /* All the bits that happen in both error_detected and cxl_remove
2256 * should be idempotent, so we don't need to worry about leaving a mix
2257 * of unconfigured and reconfigured resources.
2259 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2260 return PCI_ERS_RESULT_DISCONNECT;
2263 static void cxl_pci_resume(struct pci_dev *pdev)
2265 struct cxl *adapter = pci_get_drvdata(pdev);
2266 struct cxl_afu *afu;
2267 struct pci_dev *afu_dev;
2270 /* Everything is back now. Drivers should restart work now.
2271 * This is not the place to be checking if everything came back up
2272 * properly, because there's no return value: do that in slot_reset.
2274 for (i = 0; i < adapter->slices; i++) {
2275 afu = adapter->afu[i];
2277 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2278 if (afu_dev->driver && afu_dev->driver->err_handler &&
2279 afu_dev->driver->err_handler->resume)
2280 afu_dev->driver->err_handler->resume(afu_dev);
2285 static const struct pci_error_handlers cxl_err_handler = {
2286 .error_detected = cxl_pci_error_detected,
2287 .slot_reset = cxl_pci_slot_reset,
2288 .resume = cxl_pci_resume,
2291 struct pci_driver cxl_pci_driver = {
2293 .id_table = cxl_pci_tbl,
2295 .remove = cxl_remove,
2296 .shutdown = cxl_remove,
2297 .err_handler = &cxl_err_handler,