2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
14 static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
16 if (dma_mask < DMA_BIT_MASK(64)) {
17 pr_info("%s only 64bit DMA supported on CXL", __func__);
21 *(pdev->dev.dma_mask) = dma_mask;
25 static int cxl_pci_probe_mode(struct pci_bus *bus)
27 return PCI_PROBE_NORMAL;
30 static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
35 static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
38 * MSI should never be set but need still need to provide this call
43 static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
45 struct pci_controller *phb;
47 struct cxl_context *ctx;
49 phb = pci_bus_to_host(dev->bus);
50 afu = (struct cxl_afu *)phb->private_data;
51 set_dma_ops(&dev->dev, &dma_direct_ops);
52 set_dma_offset(&dev->dev, PAGE_OFFSET);
55 * Allocate a context to do cxl things too. If we eventually do real
56 * DMA ops, we'll need a default context to attach them to
58 ctx = cxl_dev_context_init(dev);
61 dev->dev.archdata.cxl_ctx = ctx;
63 return (cxl_afu_check_and_enable(afu) == 0);
66 static void cxl_pci_disable_device(struct pci_dev *dev)
68 struct cxl_context *ctx = cxl_get_context(dev);
71 if (ctx->status == STARTED) {
72 dev_err(&dev->dev, "Default context started\n");
75 dev->dev.archdata.cxl_ctx = NULL;
76 cxl_release_context(ctx);
80 static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
86 static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
88 /* Should we do an AFU reset here ? */
91 static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
93 return (bus << 8) + devfn;
96 static unsigned long cxl_pcie_cfg_addr(struct pci_controller* phb,
97 u8 bus, u8 devfn, int offset)
99 int record = cxl_pcie_cfg_record(bus, devfn);
101 return (unsigned long)phb->cfg_addr + ((unsigned long)phb->cfg_data * record) + offset;
105 static int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
107 volatile void __iomem **ioaddr,
108 u32 *mask, int *shift)
110 struct pci_controller *phb;
114 phb = pci_bus_to_host(bus);
115 afu = (struct cxl_afu *)phb->private_data;
117 return PCIBIOS_DEVICE_NOT_FOUND;
118 if (cxl_pcie_cfg_record(bus->number, devfn) > afu->crs_num)
119 return PCIBIOS_DEVICE_NOT_FOUND;
120 if (offset >= (unsigned long)phb->cfg_data)
121 return PCIBIOS_BAD_REGISTER_NUMBER;
122 addr = cxl_pcie_cfg_addr(phb, bus->number, devfn, offset);
124 *ioaddr = (void *)(addr & ~0x3ULL);
125 *shift = ((addr & 0x3) * 8);
140 static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
141 int offset, int len, u32 *val)
143 volatile void __iomem *ioaddr;
147 rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
152 /* Can only read 32 bits */
153 *val = (in_le32(ioaddr) >> shift) & mask;
154 return PCIBIOS_SUCCESSFUL;
157 static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
158 int offset, int len, u32 val)
160 volatile void __iomem *ioaddr;
164 rc = cxl_pcie_config_info(bus, devfn, offset, len, &ioaddr,
169 /* Can only write 32 bits so do read-modify-write */
173 v = (in_le32(ioaddr) & ~mask) || (val & mask);
176 return PCIBIOS_SUCCESSFUL;
179 static struct pci_ops cxl_pcie_pci_ops =
181 .read = cxl_pcie_read_config,
182 .write = cxl_pcie_write_config,
186 static struct pci_controller_ops cxl_pci_controller_ops =
188 .probe_mode = cxl_pci_probe_mode,
189 .enable_device_hook = cxl_pci_enable_device_hook,
190 .disable_device = cxl_pci_disable_device,
191 .release_device = cxl_pci_disable_device,
192 .window_alignment = cxl_pci_window_alignment,
193 .reset_secondary_bus = cxl_pci_reset_secondary_bus,
194 .setup_msi_irqs = cxl_setup_msi_irqs,
195 .teardown_msi_irqs = cxl_teardown_msi_irqs,
196 .dma_set_mask = cxl_dma_set_mask,
199 int cxl_pci_vphb_add(struct cxl_afu *afu)
201 struct pci_dev *phys_dev;
202 struct pci_controller *phb, *phys_phb;
204 phys_dev = to_pci_dev(afu->adapter->dev.parent);
205 phys_phb = pci_bus_to_host(phys_dev->bus);
207 /* Alloc and setup PHB data structure */
208 phb = pcibios_alloc_controller(phys_phb->dn);
213 /* Setup parent in sysfs */
214 phb->parent = &phys_dev->dev;
216 /* Setup the PHB using arch provided callback */
217 phb->ops = &cxl_pcie_pci_ops;
218 phb->cfg_addr = afu->afu_desc_mmio + afu->crs_offset;
219 phb->cfg_data = (void *)(u64)afu->crs_len;
220 phb->private_data = afu;
221 phb->controller_ops = cxl_pci_controller_ops;
224 pcibios_scan_phb(phb);
225 if (phb->bus == NULL)
228 /* Claim resources. This might need some rework as well depending
229 * whether we are doing probe-only or not, like assigning unassigned
232 pcibios_claim_one_bus(phb->bus);
234 /* Add probed PCI devices to the device model */
235 pci_bus_add_devices(phb->bus);
243 void cxl_pci_vphb_remove(struct cxl_afu *afu)
245 struct pci_controller *phb;
247 /* If there is no configuration record we won't have one of these */
248 if (!afu || !afu->phb)
253 pci_remove_root_bus(phb->bus);
256 struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
258 struct pci_controller *phb;
260 phb = pci_bus_to_host(dev->bus);
262 return (struct cxl_afu *)phb->private_data;
264 EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
266 unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
268 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
270 EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);