2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
28 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
29 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
30 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
34 uint dsaddr; /* SDMA system address register */
35 uint blkattr; /* Block attributes register */
36 uint cmdarg; /* Command argument register */
37 uint xfertyp; /* Transfer type register */
38 uint cmdrsp0; /* Command response 0 register */
39 uint cmdrsp1; /* Command response 1 register */
40 uint cmdrsp2; /* Command response 2 register */
41 uint cmdrsp3; /* Command response 3 register */
42 uint datport; /* Buffer data port register */
43 uint prsstat; /* Present state register */
44 uint proctl; /* Protocol control register */
45 uint sysctl; /* System Control Register */
46 uint irqstat; /* Interrupt status register */
47 uint irqstaten; /* Interrupt status enable register */
48 uint irqsigen; /* Interrupt signal enable register */
49 uint autoc12err; /* Auto CMD error status register */
50 uint hostcapblt; /* Host controller capabilities register */
51 uint wml; /* Watermark level register */
52 uint mixctrl; /* For USDHC */
53 char reserved1[4]; /* reserved */
54 uint fevt; /* Force event register */
55 uint admaes; /* ADMA error status register */
56 uint adsaddr; /* ADMA system address register */
57 char reserved2[160]; /* reserved */
58 uint hostver; /* Host controller version register */
59 char reserved3[4]; /* reserved */
60 uint dmaerraddr; /* DMA error address register */
61 char reserved4[4]; /* reserved */
62 uint dmaerrattr; /* DMA error attribute register */
63 char reserved5[4]; /* reserved */
64 uint hostcapblt2; /* Host controller capabilities register 2 */
65 char reserved6[8]; /* reserved */
66 uint tcr; /* Tuning control register */
67 char reserved7[28]; /* reserved */
68 uint sddirctl; /* SD direction control register */
69 char reserved8[712]; /* reserved */
70 uint scr; /* eSDHC control register */
73 /* Return the XFERTYP flags for a given command and data packet */
74 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
79 xfertyp |= XFERTYP_DPSEL;
80 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
81 xfertyp |= XFERTYP_DMAEN;
83 if (data->blocks > 1) {
84 xfertyp |= XFERTYP_MSBSEL;
85 xfertyp |= XFERTYP_BCEN;
86 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
87 xfertyp |= XFERTYP_AC12EN;
91 if (data->flags & MMC_DATA_READ)
92 xfertyp |= XFERTYP_DTDSEL;
95 if (cmd->resp_type & MMC_RSP_CRC)
96 xfertyp |= XFERTYP_CCCEN;
97 if (cmd->resp_type & MMC_RSP_OPCODE)
98 xfertyp |= XFERTYP_CICEN;
99 if (cmd->resp_type & MMC_RSP_136)
100 xfertyp |= XFERTYP_RSPTYP_136;
101 else if (cmd->resp_type & MMC_RSP_BUSY)
102 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
103 else if (cmd->resp_type & MMC_RSP_PRESENT)
104 xfertyp |= XFERTYP_RSPTYP_48;
106 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
107 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
108 xfertyp |= XFERTYP_CMDTYP_ABORT;
110 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
113 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
115 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
118 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
120 struct fsl_esdhc_cfg *cfg = mmc->priv;
121 struct fsl_esdhc *regs = cfg->esdhc_base;
127 int wml = esdhc_read32(®s->wml);
129 if (data->flags & MMC_DATA_READ) {
130 wml &= WML_RD_WML_MASK;
131 blocks = data->blocks;
134 timeout = PIO_TIMEOUT;
135 size = data->blocksize;
137 !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
141 while (!((prsstat = esdhc_read32(®s->prsstat)) &
142 PRSSTAT_BREN) && --timeout)
144 if (!(prsstat & PRSSTAT_BREN)) {
145 printf("%s: Data Read Failed in PIO Mode\n",
149 for (i = 0; i < wml && size; i++) {
150 databuf = in_le32(®s->datport);
151 memcpy(buffer, &databuf, sizeof(databuf));
159 wml = (wml & WML_WR_WML_MASK) >> 16;
160 blocks = data->blocks;
161 buffer = (char *)data->src; /* cast away 'const' */
163 timeout = PIO_TIMEOUT;
164 size = data->blocksize;
166 !(esdhc_read32(®s->irqstat) & IRQSTAT_TC)) {
170 while (!((prsstat = esdhc_read32(®s->prsstat)) &
171 PRSSTAT_BWEN) && --timeout)
173 if (!(prsstat & PRSSTAT_BWEN)) {
174 printf("%s: Data Write Failed in PIO Mode\n",
178 for (i = 0; i < wml && size; i++) {
179 memcpy(&databuf, buffer, sizeof(databuf));
180 out_le32(®s->datport, databuf);
191 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
194 struct fsl_esdhc_cfg *cfg = mmc->priv;
195 struct fsl_esdhc *regs = cfg->esdhc_base;
198 wml_value = data->blocksize / 4;
200 if (data->flags & MMC_DATA_READ) {
201 if (wml_value > WML_RD_WML_MAX)
202 wml_value = WML_RD_WML_MAX_VAL;
204 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
205 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
206 esdhc_write32(®s->dsaddr, (u32)data->dest);
209 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
210 flush_dcache_range((ulong)data->src,
211 (ulong)data->src+data->blocks
214 if (wml_value > WML_WR_WML_MAX)
215 wml_value = WML_WR_WML_MAX_VAL;
216 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
217 printf("The SD card is locked. Can not write to a locked card.\n");
221 flush_dcache_range((unsigned long)data->src,
222 (unsigned long)data->src + data->blocks * data->blocksize);
223 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
225 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
226 esdhc_write32(®s->dsaddr, (u32)data->src);
230 esdhc_write32(®s->blkattr, (data->blocks << 16) | data->blocksize);
232 /* Calculate the timeout period for data transactions */
234 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
235 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
236 * So, Number of SD Clock cycles for 0.25sec should be minimum
237 * (SD Clock/sec * 0.25 sec) SD Clock cycles
238 * = (mmc->clock * 1/4) SD Clock cycles
240 * => (2^(timeout+13)) >= mmc->clock * 1/4
241 * Taking log2 both the sides
242 * => timeout + 13 >= log2(mmc->clock/4)
243 * Rounding up to next power of 2
244 * => timeout + 13 = log2(mmc->clock/4) + 1
245 * => timeout + 13 = fls(mmc->clock/4)
247 timeout = fls(mmc->clock/4);
252 else if (timeout < 0)
255 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
256 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
260 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
263 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
268 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
269 static void check_and_invalidate_dcache_range
270 (struct mmc_cmd *cmd,
271 struct mmc_data *data) {
272 unsigned start = (unsigned)data->dest ;
273 unsigned size = roundup(ARCH_DMA_MINALIGN,
274 data->blocks*data->blocksize);
275 unsigned end = start+size ;
276 invalidate_dcache_range(start, end);
281 * Sends a command out on the bus. Takes the mmc pointer,
282 * a command pointer, and an optional data pointer.
285 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
290 struct fsl_esdhc_cfg *cfg = mmc->priv;
291 volatile struct fsl_esdhc *regs = cfg->esdhc_base;
294 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
295 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
298 esdhc_write32(®s->irqstat, -1);
302 start = get_timer_masked();
303 /* Wait for the bus to be idle */
304 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
305 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) {
306 if (get_timer(start) > CONFIG_SYS_HZ) {
307 printf("%s: Timeout waiting for bus idle\n", __func__);
312 start = get_timer_masked();
313 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) {
314 if (get_timer(start) > CONFIG_SYS_HZ)
318 /* Wait at least 8 SD clock cycles before the next command */
320 * Note: This is way more than 8 cycles, but 1ms seems to
321 * resolve timing issues with some cards
325 /* Set up for a data transfer if we have one */
327 err = esdhc_setup_data(mmc, data);
332 /* Figure out the transfer arguments */
333 xfertyp = esdhc_xfertyp(cmd, data);
336 esdhc_write32(®s->irqsigen, 0);
338 /* Send the command */
339 esdhc_write32(®s->cmdarg, cmd->cmdarg);
340 #if defined(CONFIG_FSL_USDHC)
341 esdhc_write32(®s->mixctrl,
342 (esdhc_read32(®s->mixctrl) & ~0x7f) | (xfertyp & 0x7F));
343 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
345 esdhc_write32(®s->xfertyp, xfertyp);
349 esdhc_write32(®s->irqsigen, 0);
351 start = get_timer_masked();
352 /* Wait for the command to complete */
353 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) {
354 if (get_timer(start) > CONFIG_SYS_HZ) {
355 printf("%s: Timeout waiting for cmd completion\n", __func__);
360 if (data && (data->flags & MMC_DATA_READ))
361 check_and_invalidate_dcache_range(cmd, data);
363 irqstat = esdhc_read32(®s->irqstat);
365 if (irqstat & CMD_ERR) {
370 if (irqstat & IRQSTAT_CTOE) {
375 /* Workaround for ESDHC errata ENGcm03648 */
376 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
379 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
380 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
387 printf("Timeout waiting for DAT0 to go high!\n");
393 /* Copy the response to the response buffer */
394 if (cmd->resp_type & MMC_RSP_136) {
395 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
397 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
398 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
399 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
400 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
401 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
402 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
403 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
404 cmd->response[3] = (cmdrsp0 << 8);
406 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
408 /* Wait until all of the blocks are transferred */
410 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
411 esdhc_pio_read_write(mmc, data);
414 irqstat = esdhc_read32(®s->irqstat);
416 if (irqstat & IRQSTAT_DTOE) {
421 if (irqstat & DATA_ERR) {
425 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
427 if (data->flags & MMC_DATA_READ)
428 check_and_invalidate_dcache_range(cmd, data);
433 /* Reset CMD and DATA portions on error */
435 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
437 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
441 esdhc_write32(®s->sysctl,
442 esdhc_read32(®s->sysctl) |
444 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
449 esdhc_write32(®s->irqstat, irqstat);
454 static void set_sysctl(struct mmc *mmc, uint clock)
457 struct fsl_esdhc_cfg *cfg = mmc->priv;
458 volatile struct fsl_esdhc *regs = cfg->esdhc_base;
459 int sdhc_clk = cfg->sdhc_clk;
462 if (clock < mmc->cfg->f_min)
463 clock = mmc->cfg->f_min;
465 if (sdhc_clk / 16 > clock) {
466 for (pre_div = 2; pre_div < 256; pre_div *= 2)
467 if ((sdhc_clk / pre_div) <= (clock * 16))
472 for (div = 1; div <= 16; div++)
473 if ((sdhc_clk / (div * pre_div)) <= clock)
479 clk = (pre_div << 8) | (div << 4);
481 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
483 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
487 clk = SYSCTL_PEREN | SYSCTL_CKEN;
489 esdhc_setbits32(®s->sysctl, clk);
492 static void esdhc_set_ios(struct mmc *mmc)
494 struct fsl_esdhc_cfg *cfg = mmc->priv;
495 struct fsl_esdhc *regs = cfg->esdhc_base;
497 /* Set the clock speed */
498 set_sysctl(mmc, mmc->clock);
500 /* Set the bus width */
501 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
503 if (mmc->bus_width == 4)
504 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
505 else if (mmc->bus_width == 8)
506 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
510 static int esdhc_init(struct mmc *mmc)
512 struct fsl_esdhc_cfg *cfg = mmc->priv;
513 struct fsl_esdhc *regs = cfg->esdhc_base;
516 /* Reset the entire host controller */
517 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
519 /* Wait until the controller is available */
520 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
524 /* Enable cache snooping */
525 esdhc_write32(®s->scr, 0x00000040);
528 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
530 /* Set the initial clock speed */
531 mmc_set_clock(mmc, 400000);
533 /* Disable the BRR and BWR bits in IRQSTAT */
534 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
536 /* Put the PROCTL reg back to the default */
537 esdhc_write32(®s->proctl, PROCTL_INIT);
539 /* Set timout to the maximum value */
540 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
545 static int esdhc_getcd(struct mmc *mmc)
547 struct fsl_esdhc_cfg *cfg = mmc->priv;
548 struct fsl_esdhc *regs = cfg->esdhc_base;
551 #ifdef CONFIG_ESDHC_DETECT_QUIRK
552 if (CONFIG_ESDHC_DETECT_QUIRK)
555 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
561 static void esdhc_reset(struct fsl_esdhc *regs)
563 unsigned long timeout = 100; /* wait max 100 ms */
565 /* reset the controller */
566 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
568 /* hardware clears the bit when it is done */
569 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
572 printf("MMC/SD: Reset never completed.\n");
575 static const struct mmc_ops esdhc_ops = {
576 .send_cmd = esdhc_send_cmd,
577 .set_ios = esdhc_set_ios,
579 .getcd = esdhc_getcd,
582 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
584 struct fsl_esdhc *regs;
586 u32 caps, voltage_caps;
591 regs = (struct fsl_esdhc *)cfg->esdhc_base;
593 /* First reset the eSDHC controller */
596 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
597 | SYSCTL_IPGEN | SYSCTL_CKEN);
599 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
600 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
603 caps = esdhc_read32(®s->hostcapblt);
605 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
606 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
607 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
610 /* T4240 host controller capabilities register should have VS33 bit */
611 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
612 caps = caps | ESDHC_HOSTCAPBLT_VS33;
615 if (caps & ESDHC_HOSTCAPBLT_VS18)
616 voltage_caps |= MMC_VDD_165_195;
617 if (caps & ESDHC_HOSTCAPBLT_VS30)
618 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
619 if (caps & ESDHC_HOSTCAPBLT_VS33)
620 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
622 cfg->cfg.name = "FSL_SDHC";
623 cfg->cfg.ops = &esdhc_ops;
624 #ifdef CONFIG_SYS_SD_VOLTAGE
625 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
627 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
629 if ((cfg->cfg.voltages & voltage_caps) == 0) {
630 printf("voltage not supported by controller\n");
634 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
636 if (cfg->max_bus_width > 0) {
637 if (cfg->max_bus_width < 8)
638 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
639 if (cfg->max_bus_width < 4)
640 cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
643 if (caps & ESDHC_HOSTCAPBLT_HSS)
644 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
646 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
647 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
648 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
651 cfg->cfg.f_min = 400000;
652 cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
654 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
656 mmc = mmc_create(&cfg->cfg, cfg);
663 int fsl_esdhc_mmc_init(bd_t *bis)
665 struct fsl_esdhc_cfg *cfg;
667 cfg = kzalloc(sizeof(struct fsl_esdhc_cfg), GFP_KERNEL);
670 cfg->esdhc_base = (void __iomem *)CONFIG_SYS_FSL_ESDHC_ADDR;
671 cfg->sdhc_clk = gd->arch.sdhc_clk;
672 return fsl_esdhc_initialize(bis, cfg);
675 #ifdef CONFIG_OF_LIBFDT
676 void fdt_fixup_esdhc(void *blob, bd_t *bd)
678 const char *compat = "fsl,esdhc";
680 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
681 if (!hwconfig("esdhc")) {
682 do_fixup_by_compat(blob, compat, "status", "disabled",
688 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
689 gd->arch.sdhc_clk, 1);
691 do_fixup_by_compat(blob, compat, "status", "okay",