2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/clk.h>
13 #include <linux/mmc/host.h>
14 #include <linux/mmc/dw_mmc.h>
15 #include <linux/of_address.h>
18 #include "dw_mmc-pltfm.h"
20 #define RK3288_CLKGEN_DIV 2
22 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
24 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
27 static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
29 host->bus_hz /= RK3288_CLKGEN_DIV;
34 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
44 * cclkin: source clock of mmc controller
45 * bus_hz: card interface clock generated by CLKGEN
46 * bus_hz = cclkin / RK3288_CLKGEN_DIV
47 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
49 * Note: div can only be 0 or 1
50 * if DDR50 8bit mode(only emmc work in 8bit mode),
53 if (ios->bus_width == MMC_BUS_WIDTH_8 &&
54 ios->timing == MMC_TIMING_MMC_DDR52)
55 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
57 cclkin = ios->clock * RK3288_CLKGEN_DIV;
59 ret = clk_set_rate(host->ciu_clk, cclkin);
61 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
63 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
64 if (bus_hz != host->bus_hz) {
65 host->bus_hz = bus_hz;
66 /* force dw_mci_setup_bus() */
67 host->current_speed = 0;
71 static int dw_mci_rockchip_init(struct dw_mci *host)
73 /* It is slot 8 on Rockchip SoCs */
76 /* It needs this quirk on all Rockchip SoCs */
77 host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO;
82 /* Common capabilities of RK3288 SoC */
83 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
84 MMC_CAP_RUNTIME_RESUME, /* emmc */
85 MMC_CAP_RUNTIME_RESUME, /* sdmmc */
86 MMC_CAP_RUNTIME_RESUME, /* sdio0 */
87 MMC_CAP_RUNTIME_RESUME, /* sdio1 */
89 static const struct dw_mci_drv_data rk2928_drv_data = {
90 .prepare_command = dw_mci_rockchip_prepare_command,
91 .init = dw_mci_rockchip_init,
94 static const struct dw_mci_drv_data rk3288_drv_data = {
95 .caps = dw_mci_rk3288_dwmmc_caps,
96 .prepare_command = dw_mci_rockchip_prepare_command,
97 .set_ios = dw_mci_rk3288_set_ios,
98 .setup_clock = dw_mci_rk3288_setup_clock,
99 .init = dw_mci_rockchip_init,
102 static const struct of_device_id dw_mci_rockchip_match[] = {
103 { .compatible = "rockchip,rk2928-dw-mshc",
104 .data = &rk2928_drv_data },
105 { .compatible = "rockchip,rk3288-dw-mshc",
106 .data = &rk3288_drv_data },
109 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
111 static int dw_mci_rockchip_probe(struct platform_device *pdev)
113 const struct dw_mci_drv_data *drv_data;
114 const struct of_device_id *match;
116 if (!pdev->dev.of_node)
119 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
120 drv_data = match->data;
122 return dw_mci_pltfm_register(pdev, drv_data);
125 #ifdef CONFIG_PM_SLEEP
126 static int dw_mci_rockchip_suspend(struct device *dev)
128 struct dw_mci *host = dev_get_drvdata(dev);
130 return dw_mci_suspend(host);
133 static int dw_mci_rockchip_resume(struct device *dev)
135 struct dw_mci *host = dev_get_drvdata(dev);
137 return dw_mci_resume(host);
139 #endif /* CONFIG_PM_SLEEP */
141 static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
142 dw_mci_rockchip_suspend,
143 dw_mci_rockchip_resume);
145 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
146 .probe = dw_mci_rockchip_probe,
147 .remove = dw_mci_pltfm_remove,
149 .name = "dwmmc_rockchip",
150 .of_match_table = dw_mci_rockchip_match,
151 .pm = &dw_mci_rockchip_pmops,
155 module_platform_driver(dw_mci_rockchip_pltfm_driver);
157 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
158 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
159 MODULE_ALIAS("platform:dwmmc_rockchip");
160 MODULE_LICENSE("GPL v2");