drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <kernel@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include <linux/pm_runtime.h>
  31 #include "sdhci-pltfm.h"
  32 #include "sdhci-esdhc.h"
  33
  34 #define ESDHC_CTRL_D3CD                 0x08
  35 /* VENDOR SPEC register */
  36 #define ESDHC_VENDOR_SPEC               0xc0
  37 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  39 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  40 #define ESDHC_WTMK_LVL                  0x44
  41 #define ESDHC_MIX_CTRL                  0x48
  42 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  43 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  44 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  45 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  46 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  47 /* Bits 3 and 6 are not SDHCI standard definitions */
  48 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  49 /* Tuning bits */
  50 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  51
  52 /* dll control register */
  53 #define ESDHC_DLL_CTRL                  0x60
  54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  56
  57 /* tune control register */
  58 #define ESDHC_TUNE_CTRL_STATUS          0x68
  59 #define  ESDHC_TUNE_CTRL_STEP           1
  60 #define  ESDHC_TUNE_CTRL_MIN            0
  61 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  62
  63 #define ESDHC_TUNING_CTRL               0xcc
  64 #define ESDHC_STD_TUNING_EN             (1 << 24)
  65 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  66 #define ESDHC_TUNING_START_TAP          0x1
  67
  68 /* pinctrl state */
  69 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  70 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  71
  72 /*
  73  * Our interpretation of the SDHCI_HOST_CONTROL register
  74  */
  75 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  76 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  77 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
  78
  79 /*
  80  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  81  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  82  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  83  * Define this macro DMA error INT for fsl eSDHC
  84  */
  85 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
  86
  87 /*
  88  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  89  * "11" when the STOP CMD12 is issued on imx53 to abort one
  90  * open ended multi-blk IO. Otherwise the TC INT wouldn't
  91  * be generated.
  92  * In exact block transfer, the controller doesn't complete the
  93  * operations automatically as required at the end of the
  94  * transfer and remains on hold if the abort command is not sent.
  95  * As a result, the TC flag is not asserted and SW  received timeout
  96  * exeception. Bit1 of Vendor Spec registor is used to fix it.
  97  */
  98 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
  99 /*
 100  * The flag enables the workaround for ESDHC errata ENGcm07207 which
 101  * affects i.MX25 and i.MX35.
 102  */
 103 #define ESDHC_FLAG_ENGCM07207           BIT(2)
 104 /*
 105  * The flag tells that the ESDHC controller is an USDHC block that is
 106  * integrated on the i.MX6 series.
 107  */
 108 #define ESDHC_FLAG_USDHC                BIT(3)
 109 /* The IP supports manual tuning process */
 110 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 111 /* The IP supports standard tuning process */
 112 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 113 /* The IP has SDHCI_CAPABILITIES_1 register */
 114 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 115 /*
 116  * The IP has errata ERR004536
 117  * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
 118  * when reading data from the card
 119  */
 120 #define ESDHC_FLAG_ERR004536            BIT(7)
 121
 122 struct esdhc_soc_data {
 123         u32 flags;
 124 };
 125
 126 static struct esdhc_soc_data esdhc_imx25_data = {
 127         .flags = ESDHC_FLAG_ENGCM07207,
 128 };
 129
 130 static struct esdhc_soc_data esdhc_imx35_data = {
 131         .flags = ESDHC_FLAG_ENGCM07207,
 132 };
 133
 134 static struct esdhc_soc_data esdhc_imx51_data = {
 135         .flags = 0,
 136 };
 137
 138 static struct esdhc_soc_data esdhc_imx53_data = {
 139         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 140 };
 141
 142 static struct esdhc_soc_data usdhc_imx6q_data = {
 143         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 144 };
 145
 146 static struct esdhc_soc_data usdhc_imx6sl_data = {
 147         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 148                         | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
 149 };
 150
 151 static struct esdhc_soc_data usdhc_imx6sx_data = {
 152         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 153                         | ESDHC_FLAG_HAVE_CAP1,
 154 };
 155
 156 struct pltfm_imx_data {
 157         u32 scratchpad;
 158         struct pinctrl *pinctrl;
 159         struct pinctrl_state *pins_default;
 160         struct pinctrl_state *pins_100mhz;
 161         struct pinctrl_state *pins_200mhz;
 162         const struct esdhc_soc_data *socdata;
 163         struct esdhc_platform_data boarddata;
 164         struct clk *clk_ipg;
 165         struct clk *clk_ahb;
 166         struct clk *clk_per;
 167         enum {
 168                 NO_CMD_PENDING,      /* no multiblock command pending*/
 169                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 170                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 171         } multiblock_status;
 172         u32 is_ddr;
 173 };
 174
 175 static const struct platform_device_id imx_esdhc_devtype[] = {
 176         {
 177                 .name = "sdhci-esdhc-imx25",
 178                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 179         }, {
 180                 .name = "sdhci-esdhc-imx35",
 181                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 182         }, {
 183                 .name = "sdhci-esdhc-imx51",
 184                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 185         }, {
 186                 /* sentinel */
 187         }
 188 };
 189 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 190
 191 static const struct of_device_id imx_esdhc_dt_ids[] = {
 192         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 193         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 194         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 195         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 196         { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
 197         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 198         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 199         { /* sentinel */ }
 200 };
 201 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 202
 203 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 204 {
 205         return data->socdata == &esdhc_imx25_data;
 206 }
 207
 208 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 209 {
 210         return data->socdata == &esdhc_imx53_data;
 211 }
 212
 213 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 214 {
 215         return data->socdata == &usdhc_imx6q_data;
 216 }
 217
 218 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 219 {
 220         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 221 }
 222
 223 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 224 {
 225         void __iomem *base = host->ioaddr + (reg & ~0x3);
 226         u32 shift = (reg & 0x3) * 8;
 227
 228         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 229 }
 230
 231 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 232 {
 233         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 234         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 235         u32 val = readl(host->ioaddr + reg);
 236
 237         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 238                 u32 fsl_prss = val;
 239                 /* save the least 20 bits */
 240                 val = fsl_prss & 0x000FFFFF;
 241                 /* move dat[0-3] bits */
 242                 val |= (fsl_prss & 0x0F000000) >> 4;
 243                 /* move cmd line bit */
 244                 val |= (fsl_prss & 0x00800000) << 1;
 245         }
 246
 247         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 248                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 249                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 250                         val &= 0xffff0000;
 251
 252                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 253                  * ADMA2 capability of esdhc, but this bit is messed up on
 254                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 255                  * don't actually support ADMA2). So set the BROKEN_ADMA
 256                  * uirk on MX25/35 platforms.
 257                  */
 258
 259                 if (val & SDHCI_CAN_DO_ADMA1) {
 260                         val &= ~SDHCI_CAN_DO_ADMA1;
 261                         val |= SDHCI_CAN_DO_ADMA2;
 262                 }
 263         }
 264
 265         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 266                 if (esdhc_is_usdhc(imx_data)) {
 267                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 268                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 269                         else
 270                                 /* imx6q/dl does not have cap_1 register, fake one */
 271                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 272                                         | SDHCI_SUPPORT_SDR50
 273                                         | SDHCI_USE_SDR50_TUNING;
 274                 }
 275         }
 276
 277         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 278                 val = 0;
 279                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 280                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 281                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 282         }
 283
 284         if (unlikely(reg == SDHCI_INT_STATUS)) {
 285                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 286                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 287                         val |= SDHCI_INT_ADMA_ERROR;
 288                 }
 289
 290                 /*
 291                  * mask off the interrupt we get in response to the manually
 292                  * sent CMD12
 293                  */
 294                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 295                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 296                         val &= ~SDHCI_INT_RESPONSE;
 297                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 298                                                    SDHCI_INT_STATUS);
 299                         imx_data->multiblock_status = NO_CMD_PENDING;
 300                 }
 301         }
 302
 303         return val;
 304 }
 305
 306 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 307 {
 308         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 309         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 310         u32 data;
 311
 312         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 313                 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
 314                         /*
 315                          * Clear and then set D3CD bit to avoid missing the
 316                          * card interrupt.  This is a eSDHC controller problem
 317                          * so we need to apply the following workaround: clear
 318                          * and set D3CD bit will make eSDHC re-sample the card
 319                          * interrupt. In case a card interrupt was lost,
 320                          * re-sample it by the following steps.
 321                          */
 322                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 323                         data &= ~ESDHC_CTRL_D3CD;
 324                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 325                         data |= ESDHC_CTRL_D3CD;
 326                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 327                 }
 328
 329                 if (val & SDHCI_INT_ADMA_ERROR) {
 330                         val &= ~SDHCI_INT_ADMA_ERROR;
 331                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 332                 }
 333         }
 334
 335         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 336                                 && (reg == SDHCI_INT_STATUS)
 337                                 && (val & SDHCI_INT_DATA_END))) {
 338                         u32 v;
 339                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 340                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 341                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 342
 343                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 344                         {
 345                                 /* send a manual CMD12 with RESPTYP=none */
 346                                 data = MMC_STOP_TRANSMISSION << 24 |
 347                                        SDHCI_CMD_ABORTCMD << 16;
 348                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 349                                 imx_data->multiblock_status = WAIT_FOR_INT;
 350                         }
 351         }
 352
 353         writel(val, host->ioaddr + reg);
 354 }
 355
 356 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 357 {
 358         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 359         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 360         u16 ret = 0;
 361         u32 val;
 362
 363         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 364                 reg ^= 2;
 365                 if (esdhc_is_usdhc(imx_data)) {
 366                         /*
 367                          * The usdhc register returns a wrong host version.
 368                          * Correct it here.
 369                          */
 370                         return SDHCI_SPEC_300;
 371                 }
 372         }
 373
 374         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 375                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 376                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 377                         ret |= SDHCI_CTRL_VDD_180;
 378
 379                 if (esdhc_is_usdhc(imx_data)) {
 380                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 381                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 382                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 383                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 384                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 385                 }
 386
 387                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 388                         ret |= SDHCI_CTRL_EXEC_TUNING;
 389                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 390                         ret |= SDHCI_CTRL_TUNED_CLK;
 391
 392                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 393
 394                 return ret;
 395         }
 396
 397         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 398                 if (esdhc_is_usdhc(imx_data)) {
 399                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 400                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 401                         /* Swap AC23 bit */
 402                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 403                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 404                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 405                         }
 406                 } else {
 407                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 408                 }
 409
 410                 return ret;
 411         }
 412
 413         return readw(host->ioaddr + reg);
 414 }
 415
 416 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 417 {
 418         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 419         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 420         u32 new_val = 0;
 421
 422         switch (reg) {
 423         case SDHCI_CLOCK_CONTROL:
 424                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 425                 if (val & SDHCI_CLOCK_CARD_EN)
 426                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 427                 else
 428                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 429                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 430                 return;
 431         case SDHCI_HOST_CONTROL2:
 432                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 433                 if (val & SDHCI_CTRL_VDD_180)
 434                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 435                 else
 436                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 437                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 438                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 439                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 440                         if (val & SDHCI_CTRL_TUNED_CLK)
 441                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 442                         else
 443                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 444                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 445                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 446                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 447                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 448                         if (val & SDHCI_CTRL_TUNED_CLK) {
 449                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 450                         } else {
 451                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 452                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 453                         }
 454
 455                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 456                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 457                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 458                         } else {
 459                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 460                         }
 461
 462                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
 463                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 464                 }
 465                 return;
 466         case SDHCI_TRANSFER_MODE:
 467                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 468                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 469                                 && (host->cmd->data->blocks > 1)
 470                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 471                         u32 v;
 472                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 473                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 474                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 475                 }
 476
 477                 if (esdhc_is_usdhc(imx_data)) {
 478                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 479                         /* Swap AC23 bit */
 480                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 481                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 482                                 val |= ESDHC_MIX_CTRL_AC23EN;
 483                         }
 484                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 485                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 486                 } else {
 487                         /*
 488                          * Postpone this write, we must do it together with a
 489                          * command write that is down below.
 490                          */
 491                         imx_data->scratchpad = val;
 492                 }
 493                 return;
 494         case SDHCI_COMMAND:
 495                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 496                         val |= SDHCI_CMD_ABORTCMD;
 497
 498                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 499                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 500                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 501
 502                 if (esdhc_is_usdhc(imx_data))
 503                         writel(val << 16,
 504                                host->ioaddr + SDHCI_TRANSFER_MODE);
 505                 else
 506                         writel(val << 16 | imx_data->scratchpad,
 507                                host->ioaddr + SDHCI_TRANSFER_MODE);
 508                 return;
 509         case SDHCI_BLOCK_SIZE:
 510                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 511                 break;
 512         }
 513         esdhc_clrset_le(host, 0xffff, val, reg);
 514 }
 515
 516 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 517 {
 518         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 519         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 520         u32 new_val;
 521         u32 mask;
 522
 523         switch (reg) {
 524         case SDHCI_POWER_CONTROL:
 525                 /*
 526                  * FSL put some DMA bits here
 527                  * If your board has a regulator, code should be here
 528                  */
 529                 return;
 530         case SDHCI_HOST_CONTROL:
 531                 /* FSL messed up here, so we need to manually compose it. */
 532                 new_val = val & SDHCI_CTRL_LED;
 533                 /* ensure the endianness */
 534                 new_val |= ESDHC_HOST_CONTROL_LE;
 535                 /* bits 8&9 are reserved on mx25 */
 536                 if (!is_imx25_esdhc(imx_data)) {
 537                         /* DMA mode bits are shifted */
 538                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 539                 }
 540
 541                 /*
 542                  * Do not touch buswidth bits here. This is done in
 543                  * esdhc_pltfm_bus_width.
 544                  * Do not touch the D3CD bit either which is used for the
 545                  * SDIO interrupt errata workaround.
 546                  */
 547                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 548
 549                 esdhc_clrset_le(host, mask, new_val, reg);
 550                 return;
 551         }
 552         esdhc_clrset_le(host, 0xff, val, reg);
 553
 554         /*
 555          * The esdhc has a design violation to SDHC spec which tells
 556          * that software reset should not affect card detection circuit.
 557          * But esdhc clears its SYSCTL register bits [0..2] during the
 558          * software reset.  This will stop those clocks that card detection
 559          * circuit relies on.  To work around it, we turn the clocks on back
 560          * to keep card detection circuit functional.
 561          */
 562         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
 563                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 564                 /*
 565                  * The reset on usdhc fails to clear MIX_CTRL register.
 566                  * Do it manually here.
 567                  */
 568                 if (esdhc_is_usdhc(imx_data)) {
 569                         /* the tuning bits should be kept during reset */
 570                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 571                         writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 572                                         host->ioaddr + ESDHC_MIX_CTRL);
 573                         imx_data->is_ddr = 0;
 574                 }
 575         }
 576 }
 577
 578 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 579 {
 580         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 581         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 582         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 583
 584         if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock))
 585                 return boarddata->f_max;
 586         else
 587                 return pltfm_host->clock;
 588 }
 589
 590 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 591 {
 592         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 593
 594         return pltfm_host->clock / 256 / 16;
 595 }
 596
 597 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 598                                          unsigned int clock)
 599 {
 600         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 601         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 602         unsigned int host_clock = pltfm_host->clock;
 603         int pre_div = 2;
 604         int div = 1;
 605         u32 temp, val;
 606
 607         if (clock == 0) {
 608                 host->mmc->actual_clock = 0;
 609
 610                 if (esdhc_is_usdhc(imx_data)) {
 611                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 612                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 613                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 614                 }
 615                 return;
 616         }
 617
 618         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
 619                 pre_div = 1;
 620
 621         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 622         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 623                 | ESDHC_CLOCK_MASK);
 624         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 625
 626         while (host_clock / pre_div / 16 > clock && pre_div < 256)
 627                 pre_div *= 2;
 628
 629         while (host_clock / pre_div / div > clock && div < 16)
 630                 div++;
 631
 632         host->mmc->actual_clock = host_clock / pre_div / div;
 633         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 634                 clock, host->mmc->actual_clock);
 635
 636         if (imx_data->is_ddr)
 637                 pre_div >>= 2;
 638         else
 639                 pre_div >>= 1;
 640         div--;
 641
 642         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 643         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 644                 | (div << ESDHC_DIVIDER_SHIFT)
 645                 | (pre_div << ESDHC_PREDIV_SHIFT));
 646         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 647
 648         if (esdhc_is_usdhc(imx_data)) {
 649                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 650                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 651                 host->ioaddr + ESDHC_VENDOR_SPEC);
 652         }
 653
 654         mdelay(1);
 655 }
 656
 657 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 658 {
 659         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 660         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 661         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 662
 663         switch (boarddata->wp_type) {
 664         case ESDHC_WP_GPIO:
 665                 return mmc_gpio_get_ro(host->mmc);
 666         case ESDHC_WP_CONTROLLER:
 667                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 668                                SDHCI_WRITE_PROTECT);
 669         case ESDHC_WP_NONE:
 670                 break;
 671         }
 672
 673         return -ENOSYS;
 674 }
 675
 676 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
 677 {
 678         u32 ctrl;
 679
 680         switch (width) {
 681         case MMC_BUS_WIDTH_8:
 682                 ctrl = ESDHC_CTRL_8BITBUS;
 683                 break;
 684         case MMC_BUS_WIDTH_4:
 685                 ctrl = ESDHC_CTRL_4BITBUS;
 686                 break;
 687         default:
 688                 ctrl = 0;
 689                 break;
 690         }
 691
 692         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 693                         SDHCI_HOST_CONTROL);
 694 }
 695
 696 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 697 {
 698         u32 reg;
 699
 700         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 701         mdelay(1);
 702
 703         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 704         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 705                         ESDHC_MIX_CTRL_FBCLK_SEL;
 706         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 707         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 708         dev_dbg(mmc_dev(host->mmc),
 709                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 710                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 711 }
 712
 713 static void esdhc_post_tuning(struct sdhci_host *host)
 714 {
 715         u32 reg;
 716
 717         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 718         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 719         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 720 }
 721
 722 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 723 {
 724         int min, max, avg, ret;
 725
 726         /* find the mininum delay first which can pass tuning */
 727         min = ESDHC_TUNE_CTRL_MIN;
 728         while (min < ESDHC_TUNE_CTRL_MAX) {
 729                 esdhc_prepare_tuning(host, min);
 730                 if (!mmc_send_tuning(host->mmc))
 731                         break;
 732                 min += ESDHC_TUNE_CTRL_STEP;
 733         }
 734
 735         /* find the maxinum delay which can not pass tuning */
 736         max = min + ESDHC_TUNE_CTRL_STEP;
 737         while (max < ESDHC_TUNE_CTRL_MAX) {
 738                 esdhc_prepare_tuning(host, max);
 739                 if (mmc_send_tuning(host->mmc)) {
 740                         max -= ESDHC_TUNE_CTRL_STEP;
 741                         break;
 742                 }
 743                 max += ESDHC_TUNE_CTRL_STEP;
 744         }
 745
 746         /* use average delay to get the best timing */
 747         avg = (min + max) / 2;
 748         esdhc_prepare_tuning(host, avg);
 749         ret = mmc_send_tuning(host->mmc);
 750         esdhc_post_tuning(host);
 751
 752         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
 753                 ret ? "failed" : "passed", avg, ret);
 754
 755         return ret;
 756 }
 757
 758 static int esdhc_change_pinstate(struct sdhci_host *host,
 759                                                 unsigned int uhs)
 760 {
 761         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 762         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 763         struct pinctrl_state *pinctrl;
 764
 765         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 766
 767         if (IS_ERR(imx_data->pinctrl) ||
 768                 IS_ERR(imx_data->pins_default) ||
 769                 IS_ERR(imx_data->pins_100mhz) ||
 770                 IS_ERR(imx_data->pins_200mhz))
 771                 return -EINVAL;
 772
 773         switch (uhs) {
 774         case MMC_TIMING_UHS_SDR50:
 775                 pinctrl = imx_data->pins_100mhz;
 776                 break;
 777         case MMC_TIMING_UHS_SDR104:
 778         case MMC_TIMING_MMC_HS200:
 779                 pinctrl = imx_data->pins_200mhz;
 780                 break;
 781         default:
 782                 /* back to default state for other legacy timing */
 783                 pinctrl = imx_data->pins_default;
 784         }
 785
 786         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 787 }
 788
 789 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 790 {
 791         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 792         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 793         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 794
 795         switch (timing) {
 796         case MMC_TIMING_UHS_SDR12:
 797         case MMC_TIMING_UHS_SDR25:
 798         case MMC_TIMING_UHS_SDR50:
 799         case MMC_TIMING_UHS_SDR104:
 800         case MMC_TIMING_MMC_HS200:
 801                 break;
 802         case MMC_TIMING_UHS_DDR50:
 803         case MMC_TIMING_MMC_DDR52:
 804                 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
 805                                 ESDHC_MIX_CTRL_DDREN,
 806                                 host->ioaddr + ESDHC_MIX_CTRL);
 807                 imx_data->is_ddr = 1;
 808                 if (boarddata->delay_line) {
 809                         u32 v;
 810                         v = boarddata->delay_line <<
 811                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
 812                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
 813                         if (is_imx53_esdhc(imx_data))
 814                                 v <<= 1;
 815                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
 816                 }
 817                 break;
 818         }
 819
 820         esdhc_change_pinstate(host, timing);
 821 }
 822
 823 static void esdhc_reset(struct sdhci_host *host, u8 mask)
 824 {
 825         sdhci_reset(host, mask);
 826
 827         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 828         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 829 }
 830
 831 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
 832 {
 833         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 834         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 835
 836         return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
 837 }
 838
 839 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 840 {
 841         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 842         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 843
 844         /* use maximum timeout counter */
 845         sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
 846                         SDHCI_TIMEOUT_CONTROL);
 847 }
 848
 849 static struct sdhci_ops sdhci_esdhc_ops = {
 850         .read_l = esdhc_readl_le,
 851         .read_w = esdhc_readw_le,
 852         .write_l = esdhc_writel_le,
 853         .write_w = esdhc_writew_le,
 854         .write_b = esdhc_writeb_le,
 855         .set_clock = esdhc_pltfm_set_clock,
 856         .get_max_clock = esdhc_pltfm_get_max_clock,
 857         .get_min_clock = esdhc_pltfm_get_min_clock,
 858         .get_max_timeout_count = esdhc_get_max_timeout_count,
 859         .get_ro = esdhc_pltfm_get_ro,
 860         .set_timeout = esdhc_set_timeout,
 861         .set_bus_width = esdhc_pltfm_set_bus_width,
 862         .set_uhs_signaling = esdhc_set_uhs_signaling,
 863         .reset = esdhc_reset,
 864 };
 865
 866 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 867         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
 868                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 869                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
 870                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 871         .ops = &sdhci_esdhc_ops,
 872 };
 873
 874 #ifdef CONFIG_OF
 875 static int
 876 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 877                          struct sdhci_host *host,
 878                          struct esdhc_platform_data *boarddata)
 879 {
 880         struct device_node *np = pdev->dev.of_node;
 881
 882         if (!np)
 883                 return -ENODEV;
 884
 885         if (of_get_property(np, "non-removable", NULL))
 886                 boarddata->cd_type = ESDHC_CD_PERMANENT;
 887
 888         if (of_get_property(np, "fsl,cd-controller", NULL))
 889                 boarddata->cd_type = ESDHC_CD_CONTROLLER;
 890
 891         if (of_get_property(np, "fsl,wp-controller", NULL))
 892                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
 893
 894         boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
 895         if (gpio_is_valid(boarddata->cd_gpio))
 896                 boarddata->cd_type = ESDHC_CD_GPIO;
 897
 898         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
 899         if (gpio_is_valid(boarddata->wp_gpio))
 900                 boarddata->wp_type = ESDHC_WP_GPIO;
 901
 902         of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
 903
 904         of_property_read_u32(np, "max-frequency", &boarddata->f_max);
 905
 906         if (of_find_property(np, "no-1-8-v", NULL))
 907                 boarddata->support_vsel = false;
 908         else
 909                 boarddata->support_vsel = true;
 910
 911         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
 912                 boarddata->delay_line = 0;
 913
 914         mmc_of_parse_voltage(np, &host->ocr_mask);
 915
 916         /* call to generic mmc_of_parse to support additional capabilities */
 917         return mmc_of_parse(host->mmc);
 918 }
 919 #else
 920 static inline int
 921 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 922                          struct sdhci_host *host,
 923                          struct esdhc_platform_data *boarddata)
 924 {
 925         return -ENODEV;
 926 }
 927 #endif
 928
 929 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 930 {
 931         const struct of_device_id *of_id =
 932                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
 933         struct sdhci_pltfm_host *pltfm_host;
 934         struct sdhci_host *host;
 935         struct esdhc_platform_data *boarddata;
 936         int err;
 937         struct pltfm_imx_data *imx_data;
 938         bool dt = true;
 939
 940         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 941         if (IS_ERR(host))
 942                 return PTR_ERR(host);
 943
 944         pltfm_host = sdhci_priv(host);
 945
 946         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
 947         if (!imx_data) {
 948                 err = -ENOMEM;
 949                 goto free_sdhci;
 950         }
 951
 952         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
 953                                                   pdev->id_entry->driver_data;
 954         pltfm_host->priv = imx_data;
 955
 956         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 957         if (IS_ERR(imx_data->clk_ipg)) {
 958                 err = PTR_ERR(imx_data->clk_ipg);
 959                 goto free_sdhci;
 960         }
 961
 962         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
 963         if (IS_ERR(imx_data->clk_ahb)) {
 964                 err = PTR_ERR(imx_data->clk_ahb);
 965                 goto free_sdhci;
 966         }
 967
 968         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
 969         if (IS_ERR(imx_data->clk_per)) {
 970                 err = PTR_ERR(imx_data->clk_per);
 971                 goto free_sdhci;
 972         }
 973
 974         pltfm_host->clk = imx_data->clk_per;
 975         pltfm_host->clock = clk_get_rate(pltfm_host->clk);
 976         clk_prepare_enable(imx_data->clk_per);
 977         clk_prepare_enable(imx_data->clk_ipg);
 978         clk_prepare_enable(imx_data->clk_ahb);
 979
 980         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
 981         if (IS_ERR(imx_data->pinctrl)) {
 982                 err = PTR_ERR(imx_data->pinctrl);
 983                 goto disable_clk;
 984         }
 985
 986         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
 987                                                 PINCTRL_STATE_DEFAULT);
 988         if (IS_ERR(imx_data->pins_default))
 989                 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
 990
 991         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 992
 993         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
 994                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
 995                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
 996                         | SDHCI_QUIRK_BROKEN_ADMA;
 997
 998         /*
 999          * The imx6q ROM code will change the default watermark level setting
1000          * to something insane.  Change it back here.
1001          */
1002         if (esdhc_is_usdhc(imx_data)) {
1003                 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1004                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1005                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1006
1007                 /*
1008                 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1009                 * TO1.1, it's harmless for MX6SL
1010                 */
1011                 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1012                         host->ioaddr + 0x6c);
1013         }
1014
1015         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1016                 sdhci_esdhc_ops.platform_execute_tuning =
1017                                         esdhc_executing_tuning;
1018
1019         if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1020                 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1021                         ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1022                         host->ioaddr + ESDHC_TUNING_CTRL);
1023
1024         if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1025                 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1026
1027         boarddata = &imx_data->boarddata;
1028         if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) {
1029                 if (!host->mmc->parent->platform_data) {
1030                         dev_err(mmc_dev(host->mmc), "no board data!\n");
1031                         err = -EINVAL;
1032                         goto disable_clk;
1033                 }
1034                 imx_data->boarddata = *((struct esdhc_platform_data *)
1035                                         host->mmc->parent->platform_data);
1036                 dt = false;
1037         }
1038         /* write_protect */
1039         if (boarddata->wp_type == ESDHC_WP_GPIO && !dt) {
1040                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1041                 if (err) {
1042                         dev_err(mmc_dev(host->mmc),
1043                                 "failed to request write-protect gpio!\n");
1044                         goto disable_clk;
1045                 }
1046                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1047         }
1048
1049         /* card_detect */
1050         switch (boarddata->cd_type) {
1051         case ESDHC_CD_GPIO:
1052                 if (dt)
1053                         break;
1054                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1055                 if (err) {
1056                         dev_err(mmc_dev(host->mmc),
1057                                 "failed to request card-detect gpio!\n");
1058                         goto disable_clk;
1059                 }
1060                 /* fall through */
1061
1062         case ESDHC_CD_CONTROLLER:
1063                 /* we have a working card_detect back */
1064                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1065                 break;
1066
1067         case ESDHC_CD_PERMANENT:
1068                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1069                 break;
1070
1071         case ESDHC_CD_NONE:
1072                 break;
1073         }
1074
1075         switch (boarddata->max_bus_width) {
1076         case 8:
1077                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1078                 break;
1079         case 4:
1080                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1081                 break;
1082         case 1:
1083         default:
1084                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1085                 break;
1086         }
1087
1088         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1089         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1090             !IS_ERR(imx_data->pins_default)) {
1091                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1092                                                 ESDHC_PINCTRL_STATE_100MHZ);
1093                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1094                                                 ESDHC_PINCTRL_STATE_200MHZ);
1095                 if (IS_ERR(imx_data->pins_100mhz) ||
1096                                 IS_ERR(imx_data->pins_200mhz)) {
1097                         dev_warn(mmc_dev(host->mmc),
1098                                 "could not get ultra high speed state, work on normal mode\n");
1099                         /* fall back to not support uhs by specify no 1.8v quirk */
1100                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1101                 }
1102         } else {
1103                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1104         }
1105
1106         err = sdhci_add_host(host);
1107         if (err)
1108                 goto disable_clk;
1109
1110         pm_runtime_set_active(&pdev->dev);
1111         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1112         pm_runtime_use_autosuspend(&pdev->dev);
1113         pm_suspend_ignore_children(&pdev->dev, 1);
1114         pm_runtime_enable(&pdev->dev);
1115
1116         return 0;
1117
1118 disable_clk:
1119         clk_disable_unprepare(imx_data->clk_per);
1120         clk_disable_unprepare(imx_data->clk_ipg);
1121         clk_disable_unprepare(imx_data->clk_ahb);
1122 free_sdhci:
1123         sdhci_pltfm_free(pdev);
1124         return err;
1125 }
1126
1127 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1128 {
1129         struct sdhci_host *host = platform_get_drvdata(pdev);
1130         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1131         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1132         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1133
1134         pm_runtime_get_sync(&pdev->dev);
1135         pm_runtime_disable(&pdev->dev);
1136         pm_runtime_put_noidle(&pdev->dev);
1137
1138         sdhci_remove_host(host, dead);
1139
1140         clk_disable_unprepare(imx_data->clk_per);
1141         clk_disable_unprepare(imx_data->clk_ipg);
1142         clk_disable_unprepare(imx_data->clk_ahb);
1143
1144         sdhci_pltfm_free(pdev);
1145
1146         return 0;
1147 }
1148
1149 #ifdef CONFIG_PM
1150 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1151 {
1152         struct sdhci_host *host = dev_get_drvdata(dev);
1153         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1154         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1155         int ret;
1156
1157         ret = sdhci_runtime_suspend_host(host);
1158
1159         if (!sdhci_sdio_irq_enabled(host)) {
1160                 clk_disable_unprepare(imx_data->clk_per);
1161                 clk_disable_unprepare(imx_data->clk_ipg);
1162         }
1163         clk_disable_unprepare(imx_data->clk_ahb);
1164
1165         return ret;
1166 }
1167
1168 static int sdhci_esdhc_runtime_resume(struct device *dev)
1169 {
1170         struct sdhci_host *host = dev_get_drvdata(dev);
1171         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1172         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1173
1174         if (!sdhci_sdio_irq_enabled(host)) {
1175                 clk_prepare_enable(imx_data->clk_per);
1176                 clk_prepare_enable(imx_data->clk_ipg);
1177         }
1178         clk_prepare_enable(imx_data->clk_ahb);
1179
1180         return sdhci_runtime_resume_host(host);
1181 }
1182 #endif
1183
1184 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1185         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1186         SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1187                                 sdhci_esdhc_runtime_resume, NULL)
1188 };
1189
1190 static struct platform_driver sdhci_esdhc_imx_driver = {
1191         .driver         = {
1192                 .name   = "sdhci-esdhc-imx",
1193                 .of_match_table = imx_esdhc_dt_ids,
1194                 .pm     = &sdhci_esdhc_pmops,
1195         },
1196         .id_table       = imx_esdhc_devtype,
1197         .probe          = sdhci_esdhc_imx_probe,
1198         .remove         = sdhci_esdhc_imx_remove,
1199 };
1200
1201 module_platform_driver(sdhci_esdhc_imx_driver);
1202
1203 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1204 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1205 MODULE_LICENSE("GPL v2");