drivers/mmc/host/sdhci-pxav2.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Jun Nie <njun@marvell.com>
   6  *              Qiming Wu <wuqm@marvell.com>
   7  *              Philip Rakity <prakity@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/module.h>
  25 #include <linux/io.h>
  26 #include <linux/gpio.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/mmc/host.h>
  29 #include <linux/platform_data/pxa_sdhci.h>
  30 #include <linux/slab.h>
  31 #include <linux/of.h>
  32 #include <linux/of_device.h>
  33
  34 #include "sdhci.h"
  35 #include "sdhci-pltfm.h"
  36
  37 #define SD_FIFO_PARAM           0xe0
  38 #define DIS_PAD_SD_CLK_GATE     0x0400 /* Turn on/off Dynamic SD Clock Gating */
  39 #define CLK_GATE_ON             0x0200 /* Disable/enable Clock Gate */
  40 #define CLK_GATE_CTL            0x0100 /* Clock Gate Control */
  41 #define CLK_GATE_SETTING_BITS   (DIS_PAD_SD_CLK_GATE | \
  42                 CLK_GATE_ON | CLK_GATE_CTL)
  43
  44 #define SD_CLOCK_BURST_SIZE_SETUP       0xe6
  45 #define SDCLK_SEL_SHIFT         8
  46 #define SDCLK_SEL_MASK          0x3
  47 #define SDCLK_DELAY_SHIFT       10
  48 #define SDCLK_DELAY_MASK        0x3c
  49
  50 #define SD_CE_ATA_2             0xea
  51 #define MMC_CARD                0x1000
  52 #define MMC_WIDTH               0x0100
  53
  54 static void pxav2_reset(struct sdhci_host *host, u8 mask)
  55 {
  56         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
  57         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  58
  59         sdhci_reset(host, mask);
  60
  61         if (mask == SDHCI_RESET_ALL) {
  62                 u16 tmp = 0;
  63
  64                 /*
  65                  * tune timing of read data/command when crc error happen
  66                  * no performance impact
  67                  */
  68                 if (pdata && pdata->clk_delay_sel == 1) {
  69                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  70
  71                         tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
  72                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
  73                                 << SDCLK_DELAY_SHIFT;
  74                         tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
  75                         tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
  76
  77                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  78                 }
  79
  80                 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
  81                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  82                         tmp &= ~CLK_GATE_SETTING_BITS;
  83                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  84                 } else {
  85                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  86                         tmp &= ~CLK_GATE_SETTING_BITS;
  87                         tmp |= CLK_GATE_SETTING_BITS;
  88                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  89                 }
  90         }
  91 }
  92
  93 static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
  94 {
  95         u8 ctrl;
  96         u16 tmp;
  97
  98         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  99         tmp = readw(host->ioaddr + SD_CE_ATA_2);
 100         if (width == MMC_BUS_WIDTH_8) {
 101                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 102                 tmp |= MMC_CARD | MMC_WIDTH;
 103         } else {
 104                 tmp &= ~(MMC_CARD | MMC_WIDTH);
 105                 if (width == MMC_BUS_WIDTH_4)
 106                         ctrl |= SDHCI_CTRL_4BITBUS;
 107                 else
 108                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 109         }
 110         writew(tmp, host->ioaddr + SD_CE_ATA_2);
 111         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 112 }
 113
 114 static const struct sdhci_ops pxav2_sdhci_ops = {
 115         .set_clock     = sdhci_set_clock,
 116         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 117         .set_bus_width = pxav2_mmc_set_bus_width,
 118         .reset         = pxav2_reset,
 119         .set_uhs_signaling = sdhci_set_uhs_signaling,
 120 };
 121
 122 #ifdef CONFIG_OF
 123 static const struct of_device_id sdhci_pxav2_of_match[] = {
 124         {
 125                 .compatible = "mrvl,pxav2-mmc",
 126         },
 127         {},
 128 };
 129 MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
 130
 131 static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
 132 {
 133         struct sdhci_pxa_platdata *pdata;
 134         struct device_node *np = dev->of_node;
 135         u32 bus_width;
 136         u32 clk_delay_cycles;
 137
 138         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 139         if (!pdata)
 140                 return NULL;
 141
 142         if (of_find_property(np, "non-removable", NULL))
 143                 pdata->flags |= PXA_FLAG_CARD_PERMANENT;
 144
 145         of_property_read_u32(np, "bus-width", &bus_width);
 146         if (bus_width == 8)
 147                 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
 148
 149         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
 150         if (clk_delay_cycles > 0) {
 151                 pdata->clk_delay_sel = 1;
 152                 pdata->clk_delay_cycles = clk_delay_cycles;
 153         }
 154
 155         return pdata;
 156 }
 157 #else
 158 static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
 159 {
 160         return NULL;
 161 }
 162 #endif
 163
 164 static int sdhci_pxav2_probe(struct platform_device *pdev)
 165 {
 166         struct sdhci_pltfm_host *pltfm_host;
 167         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 168         struct device *dev = &pdev->dev;
 169         struct sdhci_host *host = NULL;
 170         const struct of_device_id *match;
 171
 172         int ret;
 173         struct clk *clk;
 174
 175         host = sdhci_pltfm_init(pdev, NULL, 0);
 176         if (IS_ERR(host))
 177                 return PTR_ERR(host);
 178
 179         pltfm_host = sdhci_priv(host);
 180         pltfm_host->priv = NULL;
 181
 182         clk = clk_get(dev, "PXA-SDHCLK");
 183         if (IS_ERR(clk)) {
 184                 dev_err(dev, "failed to get io clock\n");
 185                 ret = PTR_ERR(clk);
 186                 goto err_clk_get;
 187         }
 188         pltfm_host->clk = clk;
 189         clk_prepare_enable(clk);
 190
 191         host->quirks = SDHCI_QUIRK_BROKEN_ADMA
 192                 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
 193                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 194
 195         match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
 196         if (match) {
 197                 pdata = pxav2_get_mmc_pdata(dev);
 198         }
 199         if (pdata) {
 200                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
 201                         /* on-chip device */
 202                         host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 203                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 204                 }
 205
 206                 /* If slot design supports 8 bit data, indicate this to MMC. */
 207                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 208                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 209
 210                 if (pdata->quirks)
 211                         host->quirks |= pdata->quirks;
 212                 if (pdata->host_caps)
 213                         host->mmc->caps |= pdata->host_caps;
 214                 if (pdata->pm_caps)
 215                         host->mmc->pm_caps |= pdata->pm_caps;
 216         }
 217
 218         host->ops = &pxav2_sdhci_ops;
 219
 220         ret = sdhci_add_host(host);
 221         if (ret) {
 222                 dev_err(&pdev->dev, "failed to add host\n");
 223                 goto err_add_host;
 224         }
 225
 226         platform_set_drvdata(pdev, host);
 227
 228         return 0;
 229
 230 err_add_host:
 231         clk_disable_unprepare(clk);
 232         clk_put(clk);
 233 err_clk_get:
 234         sdhci_pltfm_free(pdev);
 235         return ret;
 236 }
 237
 238 static int sdhci_pxav2_remove(struct platform_device *pdev)
 239 {
 240         struct sdhci_host *host = platform_get_drvdata(pdev);
 241         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 242
 243         sdhci_remove_host(host, 1);
 244
 245         clk_disable_unprepare(pltfm_host->clk);
 246         clk_put(pltfm_host->clk);
 247         sdhci_pltfm_free(pdev);
 248
 249         return 0;
 250 }
 251
 252 static struct platform_driver sdhci_pxav2_driver = {
 253         .driver         = {
 254                 .name   = "sdhci-pxav2",
 255                 .of_match_table = of_match_ptr(sdhci_pxav2_of_match),
 256                 .pm     = SDHCI_PLTFM_PMOPS,
 257         },
 258         .probe          = sdhci_pxav2_probe,
 259         .remove         = sdhci_pxav2_remove,
 260 };
 261
 262 module_platform_driver(sdhci_pxav2_driver);
 263
 264 MODULE_DESCRIPTION("SDHCI driver for pxav2");
 265 MODULE_AUTHOR("Marvell International Ltd.");
 266 MODULE_LICENSE("GPL v2");
 267