drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  42         defined(CONFIG_MMC_SDHCI_MODULE))
  43 #define SDHCI_USE_LEDS_CLASS
  44 #endif
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  57                                         struct mmc_data *data);
  58 static int sdhci_do_get_cd(struct sdhci_host *host);
  59
  60 #ifdef CONFIG_PM
  61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  65 #else
  66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  67 {
  68         return 0;
  69 }
  70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  71 {
  72         return 0;
  73 }
  74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  75 {
  76 }
  77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  78 {
  79 }
  80 #endif
  81
  82 static void sdhci_dumpregs(struct sdhci_host *host)
  83 {
  84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  85                 mmc_hostname(host->mmc));
  86
  87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  89                 sdhci_readw(host, SDHCI_HOST_VERSION));
  90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_ARGUMENT),
  95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 107                 sdhci_readl(host, SDHCI_INT_STATUS));
 108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 109                 sdhci_readl(host, SDHCI_INT_ENABLE),
 110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 115                 sdhci_readl(host, SDHCI_CAPABILITIES),
 116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_COMMAND),
 119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 122
 123         if (host->flags & SDHCI_USE_ADMA) {
 124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 129                 else
 130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 133         }
 134
 135         pr_debug(DRIVER_NAME ": ===========================================\n");
 136 }
 137
 138 /*****************************************************************************\
 139  *                                                                           *
 140  * Low level functions                                                       *
 141  *                                                                           *
 142 \*****************************************************************************/
 143
 144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 145 {
 146         u32 present;
 147
 148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 150                 return;
 151
 152         if (enable) {
 153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                                       SDHCI_CARD_PRESENT;
 155
 156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 157                                        SDHCI_INT_CARD_INSERT;
 158         } else {
 159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 160         }
 161
 162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 164 }
 165
 166 static void sdhci_enable_card_detection(struct sdhci_host *host)
 167 {
 168         sdhci_set_card_detection(host, true);
 169 }
 170
 171 static void sdhci_disable_card_detection(struct sdhci_host *host)
 172 {
 173         sdhci_set_card_detection(host, false);
 174 }
 175
 176 void sdhci_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         unsigned long timeout;
 179
 180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 181
 182         if (mask & SDHCI_RESET_ALL) {
 183                 host->clock = 0;
 184                 /* Reset-all turns off SD Bus Power */
 185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 186                         sdhci_runtime_pm_bus_off(host);
 187         }
 188
 189         /* Wait max 100 ms */
 190         timeout = 100;
 191
 192         /* hw clears the bit when it's done */
 193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 194                 if (timeout == 0) {
 195                         pr_err("%s: Reset 0x%x never completed.\n",
 196                                 mmc_hostname(host->mmc), (int)mask);
 197                         sdhci_dumpregs(host);
 198                         return;
 199                 }
 200                 timeout--;
 201                 mdelay(1);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 if (!sdhci_do_get_cd(host))
 210                         return;
 211         }
 212
 213         host->ops->reset(host, mask);
 214
 215         if (mask & SDHCI_RESET_ALL) {
 216                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 217                         if (host->ops->enable_dma)
 218                                 host->ops->enable_dma(host);
 219                 }
 220
 221                 /* Resetting the controller clears many */
 222                 host->preset_enabled = false;
 223         }
 224 }
 225
 226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 227
 228 static void sdhci_init(struct sdhci_host *host, int soft)
 229 {
 230         if (soft)
 231                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 232         else
 233                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 234
 235         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 236                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 237                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 238                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 239                     SDHCI_INT_RESPONSE;
 240
 241         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 242         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 243
 244         if (soft) {
 245                 /* force clock reconfiguration */
 246                 host->clock = 0;
 247                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 248         }
 249 }
 250
 251 static void sdhci_reinit(struct sdhci_host *host)
 252 {
 253         sdhci_init(host, 0);
 254         sdhci_enable_card_detection(host);
 255 }
 256
 257 static void sdhci_activate_led(struct sdhci_host *host)
 258 {
 259         u8 ctrl;
 260
 261         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 262         ctrl |= SDHCI_CTRL_LED;
 263         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 264 }
 265
 266 static void sdhci_deactivate_led(struct sdhci_host *host)
 267 {
 268         u8 ctrl;
 269
 270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 271         ctrl &= ~SDHCI_CTRL_LED;
 272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 273 }
 274
 275 #ifdef SDHCI_USE_LEDS_CLASS
 276 static void sdhci_led_control(struct led_classdev *led,
 277         enum led_brightness brightness)
 278 {
 279         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&host->lock, flags);
 283
 284         if (host->runtime_suspended)
 285                 goto out;
 286
 287         if (brightness == LED_OFF)
 288                 sdhci_deactivate_led(host);
 289         else
 290                 sdhci_activate_led(host);
 291 out:
 292         spin_unlock_irqrestore(&host->lock, flags);
 293 }
 294 #endif
 295
 296 /*****************************************************************************\
 297  *                                                                           *
 298  * Core functions                                                            *
 299  *                                                                           *
 300 \*****************************************************************************/
 301
 302 static void sdhci_read_block_pio(struct sdhci_host *host)
 303 {
 304         unsigned long flags;
 305         size_t blksize, len, chunk;
 306         u32 uninitialized_var(scratch);
 307         u8 *buf;
 308
 309         DBG("PIO reading\n");
 310
 311         blksize = host->data->blksz;
 312         chunk = 0;
 313
 314         local_irq_save(flags);
 315
 316         while (blksize) {
 317                 BUG_ON(!sg_miter_next(&host->sg_miter));
 318
 319                 len = min(host->sg_miter.length, blksize);
 320
 321                 blksize -= len;
 322                 host->sg_miter.consumed = len;
 323
 324                 buf = host->sg_miter.addr;
 325
 326                 while (len) {
 327                         if (chunk == 0) {
 328                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 329                                 chunk = 4;
 330                         }
 331
 332                         *buf = scratch & 0xFF;
 333
 334                         buf++;
 335                         scratch >>= 8;
 336                         chunk--;
 337                         len--;
 338                 }
 339         }
 340
 341         sg_miter_stop(&host->sg_miter);
 342
 343         local_irq_restore(flags);
 344 }
 345
 346 static void sdhci_write_block_pio(struct sdhci_host *host)
 347 {
 348         unsigned long flags;
 349         size_t blksize, len, chunk;
 350         u32 scratch;
 351         u8 *buf;
 352
 353         DBG("PIO writing\n");
 354
 355         blksize = host->data->blksz;
 356         chunk = 0;
 357         scratch = 0;
 358
 359         local_irq_save(flags);
 360
 361         while (blksize) {
 362                 BUG_ON(!sg_miter_next(&host->sg_miter));
 363
 364                 len = min(host->sg_miter.length, blksize);
 365
 366                 blksize -= len;
 367                 host->sg_miter.consumed = len;
 368
 369                 buf = host->sg_miter.addr;
 370
 371                 while (len) {
 372                         scratch |= (u32)*buf << (chunk * 8);
 373
 374                         buf++;
 375                         chunk++;
 376                         len--;
 377
 378                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 379                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 380                                 chunk = 0;
 381                                 scratch = 0;
 382                         }
 383                 }
 384         }
 385
 386         sg_miter_stop(&host->sg_miter);
 387
 388         local_irq_restore(flags);
 389 }
 390
 391 static void sdhci_transfer_pio(struct sdhci_host *host)
 392 {
 393         u32 mask;
 394
 395         BUG_ON(!host->data);
 396
 397         if (host->blocks == 0)
 398                 return;
 399
 400         if (host->data->flags & MMC_DATA_READ)
 401                 mask = SDHCI_DATA_AVAILABLE;
 402         else
 403                 mask = SDHCI_SPACE_AVAILABLE;
 404
 405         /*
 406          * Some controllers (JMicron JMB38x) mess up the buffer bits
 407          * for transfers < 4 bytes. As long as it is just one block,
 408          * we can ignore the bits.
 409          */
 410         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 411                 (host->data->blocks == 1))
 412                 mask = ~0;
 413
 414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 415                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 416                         udelay(100);
 417
 418                 if (host->data->flags & MMC_DATA_READ)
 419                         sdhci_read_block_pio(host);
 420                 else
 421                         sdhci_write_block_pio(host);
 422
 423                 host->blocks--;
 424                 if (host->blocks == 0)
 425                         break;
 426         }
 427
 428         DBG("PIO transfer complete.\n");
 429 }
 430
 431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 432 {
 433         local_irq_save(*flags);
 434         return kmap_atomic(sg_page(sg)) + sg->offset;
 435 }
 436
 437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 438 {
 439         kunmap_atomic(buffer);
 440         local_irq_restore(*flags);
 441 }
 442
 443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 444                                   dma_addr_t addr, int len, unsigned cmd)
 445 {
 446         struct sdhci_adma2_64_desc *dma_desc = desc;
 447
 448         /* 32-bit and 64-bit descriptors have these members in same position */
 449         dma_desc->cmd = cpu_to_le16(cmd);
 450         dma_desc->len = cpu_to_le16(len);
 451         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 452
 453         if (host->flags & SDHCI_USE_64_BIT_DMA)
 454                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 455 }
 456
 457 static void sdhci_adma_mark_end(void *desc)
 458 {
 459         struct sdhci_adma2_64_desc *dma_desc = desc;
 460
 461         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 462         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 463 }
 464
 465 static int sdhci_adma_table_pre(struct sdhci_host *host,
 466         struct mmc_data *data)
 467 {
 468         int direction;
 469
 470         void *desc;
 471         void *align;
 472         dma_addr_t addr;
 473         dma_addr_t align_addr;
 474         int len, offset;
 475
 476         struct scatterlist *sg;
 477         int i;
 478         char *buffer;
 479         unsigned long flags;
 480
 481         /*
 482          * The spec does not specify endianness of descriptor table.
 483          * We currently guess that it is LE.
 484          */
 485
 486         if (data->flags & MMC_DATA_READ)
 487                 direction = DMA_FROM_DEVICE;
 488         else
 489                 direction = DMA_TO_DEVICE;
 490
 491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 492                 host->align_buffer, host->align_buffer_sz, direction);
 493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 494                 goto fail;
 495         BUG_ON(host->align_addr & host->align_mask);
 496
 497         host->sg_count = sdhci_pre_dma_transfer(host, data);
 498         if (host->sg_count < 0)
 499                 goto unmap_align;
 500
 501         desc = host->adma_table;
 502         align = host->align_buffer;
 503
 504         align_addr = host->align_addr;
 505
 506         for_each_sg(data->sg, sg, host->sg_count, i) {
 507                 addr = sg_dma_address(sg);
 508                 len = sg_dma_len(sg);
 509
 510                 /*
 511                  * The SDHCI specification states that ADMA
 512                  * addresses must be 32-bit aligned. If they
 513                  * aren't, then we use a bounce buffer for
 514                  * the (up to three) bytes that screw up the
 515                  * alignment.
 516                  */
 517                 offset = (host->align_sz - (addr & host->align_mask)) &
 518                          host->align_mask;
 519                 if (offset) {
 520                         if (data->flags & MMC_DATA_WRITE) {
 521                                 buffer = sdhci_kmap_atomic(sg, &flags);
 522                                 memcpy(align, buffer, offset);
 523                                 sdhci_kunmap_atomic(buffer, &flags);
 524                         }
 525
 526                         /* tran, valid */
 527                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 528                                               ADMA2_TRAN_VALID);
 529
 530                         BUG_ON(offset > 65536);
 531
 532                         align += host->align_sz;
 533                         align_addr += host->align_sz;
 534
 535                         desc += host->desc_sz;
 536
 537                         addr += offset;
 538                         len -= offset;
 539                 }
 540
 541                 BUG_ON(len > 65536);
 542
 543                 if (len) {
 544                         /* tran, valid */
 545                         sdhci_adma_write_desc(host, desc, addr, len,
 546                                               ADMA2_TRAN_VALID);
 547                         desc += host->desc_sz;
 548                 }
 549
 550                 /*
 551                  * If this triggers then we have a calculation bug
 552                  * somewhere. :/
 553                  */
 554                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 555         }
 556
 557         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 558                 /*
 559                 * Mark the last descriptor as the terminating descriptor
 560                 */
 561                 if (desc != host->adma_table) {
 562                         desc -= host->desc_sz;
 563                         sdhci_adma_mark_end(desc);
 564                 }
 565         } else {
 566                 /*
 567                 * Add a terminating entry.
 568                 */
 569
 570                 /* nop, end, valid */
 571                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 572         }
 573
 574         /*
 575          * Resync align buffer as we might have changed it.
 576          */
 577         if (data->flags & MMC_DATA_WRITE) {
 578                 dma_sync_single_for_device(mmc_dev(host->mmc),
 579                         host->align_addr, host->align_buffer_sz, direction);
 580         }
 581
 582         return 0;
 583
 584 unmap_align:
 585         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 586                 host->align_buffer_sz, direction);
 587 fail:
 588         return -EINVAL;
 589 }
 590
 591 static void sdhci_adma_table_post(struct sdhci_host *host,
 592         struct mmc_data *data)
 593 {
 594         int direction;
 595
 596         struct scatterlist *sg;
 597         int i, size;
 598         void *align;
 599         char *buffer;
 600         unsigned long flags;
 601         bool has_unaligned;
 602
 603         if (data->flags & MMC_DATA_READ)
 604                 direction = DMA_FROM_DEVICE;
 605         else
 606                 direction = DMA_TO_DEVICE;
 607
 608         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 609                 host->align_buffer_sz, direction);
 610
 611         /* Do a quick scan of the SG list for any unaligned mappings */
 612         has_unaligned = false;
 613         for_each_sg(data->sg, sg, host->sg_count, i)
 614                 if (sg_dma_address(sg) & host->align_mask) {
 615                         has_unaligned = true;
 616                         break;
 617                 }
 618
 619         if (has_unaligned && data->flags & MMC_DATA_READ) {
 620                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 621                         data->sg_len, direction);
 622
 623                 align = host->align_buffer;
 624
 625                 for_each_sg(data->sg, sg, host->sg_count, i) {
 626                         if (sg_dma_address(sg) & host->align_mask) {
 627                                 size = host->align_sz -
 628                                        (sg_dma_address(sg) & host->align_mask);
 629
 630                                 buffer = sdhci_kmap_atomic(sg, &flags);
 631                                 memcpy(buffer, align, size);
 632                                 sdhci_kunmap_atomic(buffer, &flags);
 633
 634                                 align += host->align_sz;
 635                         }
 636                 }
 637         }
 638
 639         if (data->host_cookie == COOKIE_MAPPED) {
 640                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 641                         data->sg_len, direction);
 642                 data->host_cookie = COOKIE_UNMAPPED;
 643         }
 644 }
 645
 646 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 647 {
 648         u8 count;
 649         struct mmc_data *data = cmd->data;
 650         unsigned target_timeout, current_timeout;
 651
 652         /*
 653          * If the host controller provides us with an incorrect timeout
 654          * value, just skip the check and use 0xE.  The hardware may take
 655          * longer to time out, but that's much better than having a too-short
 656          * timeout value.
 657          */
 658         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 659                 return 0xE;
 660
 661         /* Unspecified timeout, assume max */
 662         if (!data && !cmd->busy_timeout)
 663                 return 0xE;
 664
 665         /* timeout in us */
 666         if (!data)
 667                 target_timeout = cmd->busy_timeout * 1000;
 668         else {
 669                 target_timeout = data->timeout_ns / 1000;
 670                 if (host->clock)
 671                         target_timeout += data->timeout_clks / host->clock;
 672         }
 673
 674         /*
 675          * Figure out needed cycles.
 676          * We do this in steps in order to fit inside a 32 bit int.
 677          * The first step is the minimum timeout, which will have a
 678          * minimum resolution of 6 bits:
 679          * (1) 2^13*1000 > 2^22,
 680          * (2) host->timeout_clk < 2^16
 681          *     =>
 682          *     (1) / (2) > 2^6
 683          */
 684         count = 0;
 685         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 686         while (current_timeout < target_timeout) {
 687                 count++;
 688                 current_timeout <<= 1;
 689                 if (count >= 0xF)
 690                         break;
 691         }
 692
 693         if (count >= 0xF) {
 694                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 695                     mmc_hostname(host->mmc), count, cmd->opcode);
 696                 count = 0xE;
 697         }
 698
 699         return count;
 700 }
 701
 702 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 703 {
 704         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 705         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 706
 707         if (host->flags & SDHCI_REQ_USE_DMA)
 708                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 709         else
 710                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 711
 712         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 713         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 714 }
 715
 716 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 717 {
 718         u8 count;
 719
 720         if (host->ops->set_timeout) {
 721                 host->ops->set_timeout(host, cmd);
 722         } else {
 723                 count = sdhci_calc_timeout(host, cmd);
 724                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 725         }
 726 }
 727
 728 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 729 {
 730         u8 ctrl;
 731         struct mmc_data *data = cmd->data;
 732         int ret;
 733
 734         WARN_ON(host->data);
 735
 736         if (data || (cmd->flags & MMC_RSP_BUSY))
 737                 sdhci_set_timeout(host, cmd);
 738
 739         if (!data)
 740                 return;
 741
 742         /* Sanity checks */
 743         BUG_ON(data->blksz * data->blocks > 524288);
 744         BUG_ON(data->blksz > host->mmc->max_blk_size);
 745         BUG_ON(data->blocks > 65535);
 746
 747         host->data = data;
 748         host->data_early = 0;
 749         host->data->bytes_xfered = 0;
 750
 751         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 752                 host->flags |= SDHCI_REQ_USE_DMA;
 753
 754         /*
 755          * FIXME: This doesn't account for merging when mapping the
 756          * scatterlist.
 757          */
 758         if (host->flags & SDHCI_REQ_USE_DMA) {
 759                 int broken, i;
 760                 struct scatterlist *sg;
 761
 762                 broken = 0;
 763                 if (host->flags & SDHCI_USE_ADMA) {
 764                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 765                                 broken = 1;
 766                 } else {
 767                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 768                                 broken = 1;
 769                 }
 770
 771                 if (unlikely(broken)) {
 772                         for_each_sg(data->sg, sg, data->sg_len, i) {
 773                                 if (sg->length & 0x3) {
 774                                         DBG("Reverting to PIO because of "
 775                                                 "transfer size (%d)\n",
 776                                                 sg->length);
 777                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 778                                         break;
 779                                 }
 780                         }
 781                 }
 782         }
 783
 784         /*
 785          * The assumption here being that alignment is the same after
 786          * translation to device address space.
 787          */
 788         if (host->flags & SDHCI_REQ_USE_DMA) {
 789                 int broken, i;
 790                 struct scatterlist *sg;
 791
 792                 broken = 0;
 793                 if (host->flags & SDHCI_USE_ADMA) {
 794                         /*
 795                          * As we use 3 byte chunks to work around
 796                          * alignment problems, we need to check this
 797                          * quirk.
 798                          */
 799                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 800                                 broken = 1;
 801                 } else {
 802                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 803                                 broken = 1;
 804                 }
 805
 806                 if (unlikely(broken)) {
 807                         for_each_sg(data->sg, sg, data->sg_len, i) {
 808                                 if (sg->offset & 0x3) {
 809                                         DBG("Reverting to PIO because of "
 810                                                 "bad alignment\n");
 811                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 812                                         break;
 813                                 }
 814                         }
 815                 }
 816         }
 817
 818         if (host->flags & SDHCI_REQ_USE_DMA) {
 819                 if (host->flags & SDHCI_USE_ADMA) {
 820                         ret = sdhci_adma_table_pre(host, data);
 821                         if (ret) {
 822                                 /*
 823                                  * This only happens when someone fed
 824                                  * us an invalid request.
 825                                  */
 826                                 WARN_ON(1);
 827                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 828                         } else {
 829                                 sdhci_writel(host, host->adma_addr,
 830                                         SDHCI_ADMA_ADDRESS);
 831                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 832                                         sdhci_writel(host,
 833                                                      (u64)host->adma_addr >> 32,
 834                                                      SDHCI_ADMA_ADDRESS_HI);
 835                         }
 836                 } else {
 837                         int sg_cnt;
 838
 839                         sg_cnt = sdhci_pre_dma_transfer(host, data);
 840                         if (sg_cnt <= 0) {
 841                                 /*
 842                                  * This only happens when someone fed
 843                                  * us an invalid request.
 844                                  */
 845                                 WARN_ON(1);
 846                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 847                         } else {
 848                                 WARN_ON(sg_cnt != 1);
 849                                 sdhci_writel(host, sg_dma_address(data->sg),
 850                                         SDHCI_DMA_ADDRESS);
 851                         }
 852                 }
 853         }
 854
 855         /*
 856          * Always adjust the DMA selection as some controllers
 857          * (e.g. JMicron) can't do PIO properly when the selection
 858          * is ADMA.
 859          */
 860         if (host->version >= SDHCI_SPEC_200) {
 861                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 862                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 863                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 864                         (host->flags & SDHCI_USE_ADMA)) {
 865                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 866                                 ctrl |= SDHCI_CTRL_ADMA64;
 867                         else
 868                                 ctrl |= SDHCI_CTRL_ADMA32;
 869                 } else {
 870                         ctrl |= SDHCI_CTRL_SDMA;
 871                 }
 872                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 873         }
 874
 875         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 876                 int flags;
 877
 878                 flags = SG_MITER_ATOMIC;
 879                 if (host->data->flags & MMC_DATA_READ)
 880                         flags |= SG_MITER_TO_SG;
 881                 else
 882                         flags |= SG_MITER_FROM_SG;
 883                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 884                 host->blocks = data->blocks;
 885         }
 886
 887         sdhci_set_transfer_irqs(host);
 888
 889         /* Set the DMA boundary value and block size */
 890         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 891                 data->blksz), SDHCI_BLOCK_SIZE);
 892         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 893 }
 894
 895 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 896         struct mmc_command *cmd)
 897 {
 898         u16 mode = 0;
 899         struct mmc_data *data = cmd->data;
 900
 901         if (data == NULL) {
 902                 if (host->quirks2 &
 903                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 904                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 905                 } else {
 906                 /* clear Auto CMD settings for no data CMDs */
 907                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 908                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 909                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 910                 }
 911                 return;
 912         }
 913
 914         WARN_ON(!host->data);
 915
 916         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 917                 mode = SDHCI_TRNS_BLK_CNT_EN;
 918
 919         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 920                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 921                 /*
 922                  * If we are sending CMD23, CMD12 never gets sent
 923                  * on successful completion (so no Auto-CMD12).
 924                  */
 925                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 926                     (cmd->opcode != SD_IO_RW_EXTENDED))
 927                         mode |= SDHCI_TRNS_AUTO_CMD12;
 928                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 929                         mode |= SDHCI_TRNS_AUTO_CMD23;
 930                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 931                 }
 932         }
 933
 934         if (data->flags & MMC_DATA_READ)
 935                 mode |= SDHCI_TRNS_READ;
 936         if (host->flags & SDHCI_REQ_USE_DMA)
 937                 mode |= SDHCI_TRNS_DMA;
 938
 939         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 940 }
 941
 942 static void sdhci_finish_data(struct sdhci_host *host)
 943 {
 944         struct mmc_data *data;
 945
 946         BUG_ON(!host->data);
 947
 948         data = host->data;
 949         host->data = NULL;
 950
 951         if (host->flags & SDHCI_REQ_USE_DMA) {
 952                 if (host->flags & SDHCI_USE_ADMA)
 953                         sdhci_adma_table_post(host, data);
 954                 else {
 955                         if (data->host_cookie == COOKIE_MAPPED) {
 956                                 dma_unmap_sg(mmc_dev(host->mmc),
 957                                         data->sg, data->sg_len,
 958                                         (data->flags & MMC_DATA_READ) ?
 959                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 960                                 data->host_cookie = COOKIE_UNMAPPED;
 961                         }
 962                 }
 963         }
 964
 965         /*
 966          * The specification states that the block count register must
 967          * be updated, but it does not specify at what point in the
 968          * data flow. That makes the register entirely useless to read
 969          * back so we have to assume that nothing made it to the card
 970          * in the event of an error.
 971          */
 972         if (data->error)
 973                 data->bytes_xfered = 0;
 974         else
 975                 data->bytes_xfered = data->blksz * data->blocks;
 976
 977         /*
 978          * Need to send CMD12 if -
 979          * a) open-ended multiblock transfer (no CMD23)
 980          * b) error in multiblock transfer
 981          */
 982         if (data->stop &&
 983             (data->error ||
 984              !host->mrq->sbc)) {
 985
 986                 /*
 987                  * The controller needs a reset of internal state machines
 988                  * upon error conditions.
 989                  */
 990                 if (data->error) {
 991                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 992                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 993                 }
 994
 995                 sdhci_send_command(host, data->stop);
 996         } else
 997                 tasklet_schedule(&host->finish_tasklet);
 998 }
 999
1000 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1001 {
1002         int flags;
1003         u32 mask;
1004         unsigned long timeout;
1005
1006         WARN_ON(host->cmd);
1007
1008         /* Wait max 10 ms */
1009         timeout = 10;
1010
1011         mask = SDHCI_CMD_INHIBIT;
1012         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1013                 mask |= SDHCI_DATA_INHIBIT;
1014
1015         /* We shouldn't wait for data inihibit for stop commands, even
1016            though they might use busy signaling */
1017         if (host->mrq->data && (cmd == host->mrq->data->stop))
1018                 mask &= ~SDHCI_DATA_INHIBIT;
1019
1020         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1021                 if (timeout == 0) {
1022                         pr_err("%s: Controller never released "
1023                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1024                         sdhci_dumpregs(host);
1025                         cmd->error = -EIO;
1026                         tasklet_schedule(&host->finish_tasklet);
1027                         return;
1028                 }
1029                 timeout--;
1030                 mdelay(1);
1031         }
1032
1033         timeout = jiffies;
1034         if (!cmd->data && cmd->busy_timeout > 9000)
1035                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1036         else
1037                 timeout += 10 * HZ;
1038         mod_timer(&host->timer, timeout);
1039
1040         host->cmd = cmd;
1041         host->busy_handle = 0;
1042
1043         sdhci_prepare_data(host, cmd);
1044
1045         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1046
1047         sdhci_set_transfer_mode(host, cmd);
1048
1049         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1050                 pr_err("%s: Unsupported response type!\n",
1051                         mmc_hostname(host->mmc));
1052                 cmd->error = -EINVAL;
1053                 tasklet_schedule(&host->finish_tasklet);
1054                 return;
1055         }
1056
1057         if (!(cmd->flags & MMC_RSP_PRESENT))
1058                 flags = SDHCI_CMD_RESP_NONE;
1059         else if (cmd->flags & MMC_RSP_136)
1060                 flags = SDHCI_CMD_RESP_LONG;
1061         else if (cmd->flags & MMC_RSP_BUSY)
1062                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1063         else
1064                 flags = SDHCI_CMD_RESP_SHORT;
1065
1066         if (cmd->flags & MMC_RSP_CRC)
1067                 flags |= SDHCI_CMD_CRC;
1068         if (cmd->flags & MMC_RSP_OPCODE)
1069                 flags |= SDHCI_CMD_INDEX;
1070
1071         /* CMD19 is special in that the Data Present Select should be set */
1072         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1073             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1074                 flags |= SDHCI_CMD_DATA;
1075
1076         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1077 }
1078 EXPORT_SYMBOL_GPL(sdhci_send_command);
1079
1080 static void sdhci_finish_command(struct sdhci_host *host)
1081 {
1082         int i;
1083
1084         BUG_ON(host->cmd == NULL);
1085
1086         if (host->cmd->flags & MMC_RSP_PRESENT) {
1087                 if (host->cmd->flags & MMC_RSP_136) {
1088                         /* CRC is stripped so we need to do some shifting. */
1089                         for (i = 0;i < 4;i++) {
1090                                 host->cmd->resp[i] = sdhci_readl(host,
1091                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1092                                 if (i != 3)
1093                                         host->cmd->resp[i] |=
1094                                                 sdhci_readb(host,
1095                                                 SDHCI_RESPONSE + (3-i)*4-1);
1096                         }
1097                 } else {
1098                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1099                 }
1100         }
1101
1102         host->cmd->error = 0;
1103
1104         /* Finished CMD23, now send actual command. */
1105         if (host->cmd == host->mrq->sbc) {
1106                 host->cmd = NULL;
1107                 sdhci_send_command(host, host->mrq->cmd);
1108         } else {
1109
1110                 /* Processed actual command. */
1111                 if (host->data && host->data_early)
1112                         sdhci_finish_data(host);
1113
1114                 if (!host->cmd->data)
1115                         tasklet_schedule(&host->finish_tasklet);
1116
1117                 host->cmd = NULL;
1118         }
1119 }
1120
1121 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1122 {
1123         u16 preset = 0;
1124
1125         switch (host->timing) {
1126         case MMC_TIMING_UHS_SDR12:
1127                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1128                 break;
1129         case MMC_TIMING_UHS_SDR25:
1130                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1131                 break;
1132         case MMC_TIMING_UHS_SDR50:
1133                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1134                 break;
1135         case MMC_TIMING_UHS_SDR104:
1136         case MMC_TIMING_MMC_HS200:
1137                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1138                 break;
1139         case MMC_TIMING_UHS_DDR50:
1140         case MMC_TIMING_MMC_DDR52:
1141                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1142                 break;
1143         case MMC_TIMING_MMC_HS400:
1144                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1145                 break;
1146         default:
1147                 pr_warn("%s: Invalid UHS-I mode selected\n",
1148                         mmc_hostname(host->mmc));
1149                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1150                 break;
1151         }
1152         return preset;
1153 }
1154
1155 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1156 {
1157         int div = 0; /* Initialized for compiler warning */
1158         int real_div = div, clk_mul = 1;
1159         u16 clk = 0;
1160         unsigned long timeout;
1161         bool switch_base_clk = false;
1162
1163         host->mmc->actual_clock = 0;
1164
1165         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1166         if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1167                 mdelay(1);
1168
1169         if (clock == 0)
1170                 return;
1171
1172         if (host->version >= SDHCI_SPEC_300) {
1173                 if (host->preset_enabled) {
1174                         u16 pre_val;
1175
1176                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1177                         pre_val = sdhci_get_preset_value(host);
1178                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1179                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1180                         if (host->clk_mul &&
1181                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1182                                 clk = SDHCI_PROG_CLOCK_MODE;
1183                                 real_div = div + 1;
1184                                 clk_mul = host->clk_mul;
1185                         } else {
1186                                 real_div = max_t(int, 1, div << 1);
1187                         }
1188                         goto clock_set;
1189                 }
1190
1191                 /*
1192                  * Check if the Host Controller supports Programmable Clock
1193                  * Mode.
1194                  */
1195                 if (host->clk_mul) {
1196                         for (div = 1; div <= 1024; div++) {
1197                                 if ((host->max_clk * host->clk_mul / div)
1198                                         <= clock)
1199                                         break;
1200                         }
1201                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1202                                 /*
1203                                  * Set Programmable Clock Mode in the Clock
1204                                  * Control register.
1205                                  */
1206                                 clk = SDHCI_PROG_CLOCK_MODE;
1207                                 real_div = div;
1208                                 clk_mul = host->clk_mul;
1209                                 div--;
1210                         } else {
1211                                 /*
1212                                  * Divisor can be too small to reach clock
1213                                  * speed requirement. Then use the base clock.
1214                                  */
1215                                 switch_base_clk = true;
1216                         }
1217                 }
1218
1219                 if (!host->clk_mul || switch_base_clk) {
1220                         /* Version 3.00 divisors must be a multiple of 2. */
1221                         if (host->max_clk <= clock)
1222                                 div = 1;
1223                         else {
1224                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1225                                      div += 2) {
1226                                         if ((host->max_clk / div) <= clock)
1227                                                 break;
1228                                 }
1229                         }
1230                         real_div = div;
1231                         div >>= 1;
1232                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1233                                 && !div && host->max_clk <= 25000000)
1234                                 div = 1;
1235                 }
1236         } else {
1237                 /* Version 2.00 divisors must be a power of 2. */
1238                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1239                         if ((host->max_clk / div) <= clock)
1240                                 break;
1241                 }
1242                 real_div = div;
1243                 div >>= 1;
1244         }
1245
1246 clock_set:
1247         if (real_div)
1248                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1249         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1250         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1251                 << SDHCI_DIVIDER_HI_SHIFT;
1252         clk |= SDHCI_CLOCK_INT_EN;
1253         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1254
1255         /* Wait max 20 ms */
1256         timeout = 20;
1257         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1258                 & SDHCI_CLOCK_INT_STABLE)) {
1259                 if (timeout == 0) {
1260                         pr_err("%s: Internal clock never "
1261                                 "stabilised.\n", mmc_hostname(host->mmc));
1262                         sdhci_dumpregs(host);
1263                         return;
1264                 }
1265                 timeout--;
1266                 mdelay(1);
1267         }
1268
1269         clk |= SDHCI_CLOCK_CARD_EN;
1270         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1271 }
1272 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1273
1274 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1275                             unsigned short vdd)
1276 {
1277         struct mmc_host *mmc = host->mmc;
1278         u8 pwr = 0;
1279
1280         if (!IS_ERR(mmc->supply.vmmc)) {
1281                 spin_unlock_irq(&host->lock);
1282                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1283                 spin_lock_irq(&host->lock);
1284
1285                 if (mode != MMC_POWER_OFF)
1286                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1287                 else
1288                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1289
1290                 return;
1291         }
1292
1293         if (mode != MMC_POWER_OFF) {
1294                 switch (1 << vdd) {
1295                 case MMC_VDD_165_195:
1296                         pwr = SDHCI_POWER_180;
1297                         break;
1298                 case MMC_VDD_29_30:
1299                 case MMC_VDD_30_31:
1300                         pwr = SDHCI_POWER_300;
1301                         break;
1302                 case MMC_VDD_32_33:
1303                 case MMC_VDD_33_34:
1304                         pwr = SDHCI_POWER_330;
1305                         break;
1306                 default:
1307                         BUG();
1308                 }
1309         }
1310
1311         if (host->pwr == pwr)
1312                 return;
1313
1314         host->pwr = pwr;
1315
1316         if (pwr == 0) {
1317                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1318                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1319                         sdhci_runtime_pm_bus_off(host);
1320                 vdd = 0;
1321         } else {
1322                 /*
1323                  * Spec says that we should clear the power reg before setting
1324                  * a new value. Some controllers don't seem to like this though.
1325                  */
1326                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1327                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1328
1329                 /*
1330                  * At least the Marvell CaFe chip gets confused if we set the
1331                  * voltage and set turn on power at the same time, so set the
1332                  * voltage first.
1333                  */
1334                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1335                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1336
1337                 pwr |= SDHCI_POWER_ON;
1338
1339                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1340
1341                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1342                         sdhci_runtime_pm_bus_on(host);
1343
1344                 /*
1345                  * Some controllers need an extra 10ms delay of 10ms before
1346                  * they can apply clock after applying power
1347                  */
1348                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1349                         mdelay(10);
1350         }
1351 }
1352
1353 /*****************************************************************************\
1354  *                                                                           *
1355  * MMC callbacks                                                             *
1356  *                                                                           *
1357 \*****************************************************************************/
1358
1359 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1360 {
1361         struct sdhci_host *host;
1362         int present;
1363         unsigned long flags;
1364
1365         host = mmc_priv(mmc);
1366
1367         sdhci_runtime_pm_get(host);
1368
1369         /* Firstly check card presence */
1370         present = mmc->ops->get_cd(mmc);
1371
1372         spin_lock_irqsave(&host->lock, flags);
1373
1374         WARN_ON(host->mrq != NULL);
1375
1376 #ifndef SDHCI_USE_LEDS_CLASS
1377         sdhci_activate_led(host);
1378 #endif
1379
1380         /*
1381          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1382          * requests if Auto-CMD12 is enabled.
1383          */
1384         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1385                 if (mrq->stop) {
1386                         mrq->data->stop = NULL;
1387                         mrq->stop = NULL;
1388                 }
1389         }
1390
1391         host->mrq = mrq;
1392
1393         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1394                 host->mrq->cmd->error = -ENOMEDIUM;
1395                 tasklet_schedule(&host->finish_tasklet);
1396         } else {
1397                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1398                         sdhci_send_command(host, mrq->sbc);
1399                 else
1400                         sdhci_send_command(host, mrq->cmd);
1401         }
1402
1403         mmiowb();
1404         spin_unlock_irqrestore(&host->lock, flags);
1405 }
1406
1407 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1408 {
1409         u8 ctrl;
1410
1411         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1412         if (width == MMC_BUS_WIDTH_8) {
1413                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1414                 if (host->version >= SDHCI_SPEC_300)
1415                         ctrl |= SDHCI_CTRL_8BITBUS;
1416         } else {
1417                 if (host->version >= SDHCI_SPEC_300)
1418                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1419                 if (width == MMC_BUS_WIDTH_4)
1420                         ctrl |= SDHCI_CTRL_4BITBUS;
1421                 else
1422                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1423         }
1424         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1425 }
1426 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1427
1428 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1429 {
1430         u16 ctrl_2;
1431
1432         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1433         /* Select Bus Speed Mode for host */
1434         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1435         if ((timing == MMC_TIMING_MMC_HS200) ||
1436             (timing == MMC_TIMING_UHS_SDR104))
1437                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1438         else if (timing == MMC_TIMING_UHS_SDR12)
1439                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1440         else if (timing == MMC_TIMING_UHS_SDR25)
1441                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1442         else if (timing == MMC_TIMING_UHS_SDR50)
1443                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1444         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1445                  (timing == MMC_TIMING_MMC_DDR52))
1446                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1447         else if (timing == MMC_TIMING_MMC_HS400)
1448                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1449         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1450 }
1451 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1452
1453 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1454 {
1455         unsigned long flags;
1456         u8 ctrl;
1457         struct mmc_host *mmc = host->mmc;
1458
1459         spin_lock_irqsave(&host->lock, flags);
1460
1461         if (host->flags & SDHCI_DEVICE_DEAD) {
1462                 spin_unlock_irqrestore(&host->lock, flags);
1463                 if (!IS_ERR(mmc->supply.vmmc) &&
1464                     ios->power_mode == MMC_POWER_OFF)
1465                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1466                 return;
1467         }
1468
1469         /*
1470          * Reset the chip on each power off.
1471          * Should clear out any weird states.
1472          */
1473         if (ios->power_mode == MMC_POWER_OFF) {
1474                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1475                 sdhci_reinit(host);
1476         }
1477
1478         if (host->version >= SDHCI_SPEC_300 &&
1479                 (ios->power_mode == MMC_POWER_UP) &&
1480                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1481                 sdhci_enable_preset_value(host, false);
1482
1483         if (!ios->clock || ios->clock != host->clock) {
1484                 host->ops->set_clock(host, ios->clock);
1485                 host->clock = ios->clock;
1486
1487                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1488                     host->clock) {
1489                         host->timeout_clk = host->mmc->actual_clock ?
1490                                                 host->mmc->actual_clock / 1000 :
1491                                                 host->clock / 1000;
1492                         host->mmc->max_busy_timeout =
1493                                 host->ops->get_max_timeout_count ?
1494                                 host->ops->get_max_timeout_count(host) :
1495                                 1 << 27;
1496                         host->mmc->max_busy_timeout /= host->timeout_clk;
1497                 }
1498         }
1499
1500         sdhci_set_power(host, ios->power_mode, ios->vdd);
1501
1502         if (host->ops->platform_send_init_74_clocks)
1503                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1504
1505         host->ops->set_bus_width(host, ios->bus_width);
1506
1507         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1508
1509         if ((ios->timing == MMC_TIMING_SD_HS ||
1510              ios->timing == MMC_TIMING_MMC_HS)
1511             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1512                 ctrl |= SDHCI_CTRL_HISPD;
1513         else
1514                 ctrl &= ~SDHCI_CTRL_HISPD;
1515
1516         if (host->version >= SDHCI_SPEC_300) {
1517                 u16 clk, ctrl_2;
1518
1519                 /* In case of UHS-I modes, set High Speed Enable */
1520                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1521                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1522                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1523                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1524                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1525                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1526                     (ios->timing == MMC_TIMING_UHS_SDR25))
1527                         ctrl |= SDHCI_CTRL_HISPD;
1528
1529                 if (!host->preset_enabled) {
1530                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1531                         /*
1532                          * We only need to set Driver Strength if the
1533                          * preset value enable is not set.
1534                          */
1535                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1536                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1537                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1538                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1539                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1540                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1541                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1542                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1543                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1544                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1545                         else {
1546                                 pr_warn("%s: invalid driver type, default to "
1547                                         "driver type B\n", mmc_hostname(mmc));
1548                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1549                         }
1550
1551                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1552                 } else {
1553                         /*
1554                          * According to SDHC Spec v3.00, if the Preset Value
1555                          * Enable in the Host Control 2 register is set, we
1556                          * need to reset SD Clock Enable before changing High
1557                          * Speed Enable to avoid generating clock gliches.
1558                          */
1559
1560                         /* Reset SD Clock Enable */
1561                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1562                         clk &= ~SDHCI_CLOCK_CARD_EN;
1563                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1564
1565                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1566
1567                         /* Re-enable SD Clock */
1568                         host->ops->set_clock(host, host->clock);
1569                 }
1570
1571                 /* Reset SD Clock Enable */
1572                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1573                 clk &= ~SDHCI_CLOCK_CARD_EN;
1574                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1575
1576                 host->ops->set_uhs_signaling(host, ios->timing);
1577                 host->timing = ios->timing;
1578
1579                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1580                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1581                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1582                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1583                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1584                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1585                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1586                         u16 preset;
1587
1588                         sdhci_enable_preset_value(host, true);
1589                         preset = sdhci_get_preset_value(host);
1590                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1591                                 >> SDHCI_PRESET_DRV_SHIFT;
1592                 }
1593
1594                 /* Re-enable SD Clock */
1595                 host->ops->set_clock(host, host->clock);
1596         } else
1597                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1598
1599         /*
1600          * Some (ENE) controllers go apeshit on some ios operation,
1601          * signalling timeout and CRC errors even on CMD0. Resetting
1602          * it on each ios seems to solve the problem.
1603          */
1604         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1605                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1606
1607         mmiowb();
1608         spin_unlock_irqrestore(&host->lock, flags);
1609 }
1610
1611 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1612 {
1613         struct sdhci_host *host = mmc_priv(mmc);
1614
1615         sdhci_runtime_pm_get(host);
1616         sdhci_do_set_ios(host, ios);
1617         sdhci_runtime_pm_put(host);
1618 }
1619
1620 static int sdhci_do_get_cd(struct sdhci_host *host)
1621 {
1622         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1623
1624         if (host->flags & SDHCI_DEVICE_DEAD)
1625                 return 0;
1626
1627         /*
1628          * Try slot gpio detect, if defined it take precedence
1629          * over build in controller functionality
1630          */
1631         if (!IS_ERR_VALUE(gpio_cd))
1632                 return !!gpio_cd;
1633
1634         /* If polling/nonremovable, assume that the card is always present. */
1635         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1636             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1637                 return 1;
1638
1639         /* Host native card detect */
1640         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1641 }
1642
1643 static int sdhci_get_cd(struct mmc_host *mmc)
1644 {
1645         struct sdhci_host *host = mmc_priv(mmc);
1646         int ret;
1647
1648         sdhci_runtime_pm_get(host);
1649         ret = sdhci_do_get_cd(host);
1650         sdhci_runtime_pm_put(host);
1651         return ret;
1652 }
1653
1654 static int sdhci_check_ro(struct sdhci_host *host)
1655 {
1656         unsigned long flags;
1657         int is_readonly;
1658
1659         spin_lock_irqsave(&host->lock, flags);
1660
1661         if (host->flags & SDHCI_DEVICE_DEAD)
1662                 is_readonly = 0;
1663         else if (host->ops->get_ro)
1664                 is_readonly = host->ops->get_ro(host);
1665         else
1666                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1667                                 & SDHCI_WRITE_PROTECT);
1668
1669         spin_unlock_irqrestore(&host->lock, flags);
1670
1671         /* This quirk needs to be replaced by a callback-function later */
1672         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1673                 !is_readonly : is_readonly;
1674 }
1675
1676 #define SAMPLE_COUNT    5
1677
1678 static int sdhci_do_get_ro(struct sdhci_host *host)
1679 {
1680         int i, ro_count;
1681
1682         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1683                 return sdhci_check_ro(host);
1684
1685         ro_count = 0;
1686         for (i = 0; i < SAMPLE_COUNT; i++) {
1687                 if (sdhci_check_ro(host)) {
1688                         if (++ro_count > SAMPLE_COUNT / 2)
1689                                 return 1;
1690                 }
1691                 msleep(30);
1692         }
1693         return 0;
1694 }
1695
1696 static void sdhci_hw_reset(struct mmc_host *mmc)
1697 {
1698         struct sdhci_host *host = mmc_priv(mmc);
1699
1700         if (host->ops && host->ops->hw_reset)
1701                 host->ops->hw_reset(host);
1702 }
1703
1704 static int sdhci_get_ro(struct mmc_host *mmc)
1705 {
1706         struct sdhci_host *host = mmc_priv(mmc);
1707         int ret;
1708
1709         sdhci_runtime_pm_get(host);
1710         ret = sdhci_do_get_ro(host);
1711         sdhci_runtime_pm_put(host);
1712         return ret;
1713 }
1714
1715 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1716 {
1717         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1718                 if (enable)
1719                         host->ier |= SDHCI_INT_CARD_INT;
1720                 else
1721                         host->ier &= ~SDHCI_INT_CARD_INT;
1722
1723                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1724                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1725                 mmiowb();
1726         }
1727 }
1728
1729 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1730 {
1731         struct sdhci_host *host = mmc_priv(mmc);
1732         unsigned long flags;
1733
1734         sdhci_runtime_pm_get(host);
1735
1736         spin_lock_irqsave(&host->lock, flags);
1737         if (enable)
1738                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1739         else
1740                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1741
1742         sdhci_enable_sdio_irq_nolock(host, enable);
1743         spin_unlock_irqrestore(&host->lock, flags);
1744
1745         sdhci_runtime_pm_put(host);
1746 }
1747
1748 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1749                                                 struct mmc_ios *ios)
1750 {
1751         struct mmc_host *mmc = host->mmc;
1752         u16 ctrl;
1753         int ret;
1754
1755         /*
1756          * Signal Voltage Switching is only applicable for Host Controllers
1757          * v3.00 and above.
1758          */
1759         if (host->version < SDHCI_SPEC_300)
1760                 return 0;
1761
1762         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1763
1764         switch (ios->signal_voltage) {
1765         case MMC_SIGNAL_VOLTAGE_330:
1766                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1767                 ctrl &= ~SDHCI_CTRL_VDD_180;
1768                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1769
1770                 if (!IS_ERR(mmc->supply.vqmmc)) {
1771                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1772                                                     3600000);
1773                         if (ret) {
1774                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1775                                         mmc_hostname(mmc));
1776                                 return -EIO;
1777                         }
1778                 }
1779                 /* Wait for 5ms */
1780                 usleep_range(5000, 5500);
1781
1782                 /* 3.3V regulator output should be stable within 5 ms */
1783                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1784                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1785                         return 0;
1786
1787                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1788                         mmc_hostname(mmc));
1789
1790                 return -EAGAIN;
1791         case MMC_SIGNAL_VOLTAGE_180:
1792                 if (!IS_ERR(mmc->supply.vqmmc)) {
1793                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1794                                         1700000, 1950000);
1795                         if (ret) {
1796                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1797                                         mmc_hostname(mmc));
1798                                 return -EIO;
1799                         }
1800                 }
1801
1802                 /*
1803                  * Enable 1.8V Signal Enable in the Host Control2
1804                  * register
1805                  */
1806                 ctrl |= SDHCI_CTRL_VDD_180;
1807                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1808
1809                 /* Some controller need to do more when switching */
1810                 if (host->ops->voltage_switch)
1811                         host->ops->voltage_switch(host);
1812
1813                 /* 1.8V regulator output should be stable within 5 ms */
1814                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1815                 if (ctrl & SDHCI_CTRL_VDD_180)
1816                         return 0;
1817
1818                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1819                         mmc_hostname(mmc));
1820
1821                 return -EAGAIN;
1822         case MMC_SIGNAL_VOLTAGE_120:
1823                 if (!IS_ERR(mmc->supply.vqmmc)) {
1824                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1825                                                     1300000);
1826                         if (ret) {
1827                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1828                                         mmc_hostname(mmc));
1829                                 return -EIO;
1830                         }
1831                 }
1832                 return 0;
1833         default:
1834                 /* No signal voltage switch required */
1835                 return 0;
1836         }
1837 }
1838
1839 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1840         struct mmc_ios *ios)
1841 {
1842         struct sdhci_host *host = mmc_priv(mmc);
1843         int err;
1844
1845         if (host->version < SDHCI_SPEC_300)
1846                 return 0;
1847         sdhci_runtime_pm_get(host);
1848         err = sdhci_do_start_signal_voltage_switch(host, ios);
1849         sdhci_runtime_pm_put(host);
1850         return err;
1851 }
1852
1853 static int sdhci_card_busy(struct mmc_host *mmc)
1854 {
1855         struct sdhci_host *host = mmc_priv(mmc);
1856         u32 present_state;
1857
1858         sdhci_runtime_pm_get(host);
1859         /* Check whether DAT[3:0] is 0000 */
1860         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1861         sdhci_runtime_pm_put(host);
1862
1863         return !(present_state & SDHCI_DATA_LVL_MASK);
1864 }
1865
1866 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1867 {
1868         struct sdhci_host *host = mmc_priv(mmc);
1869         unsigned long flags;
1870
1871         spin_lock_irqsave(&host->lock, flags);
1872         host->flags |= SDHCI_HS400_TUNING;
1873         spin_unlock_irqrestore(&host->lock, flags);
1874
1875         return 0;
1876 }
1877
1878 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1879 {
1880         struct sdhci_host *host = mmc_priv(mmc);
1881         u16 ctrl;
1882         int tuning_loop_counter = MAX_TUNING_LOOP;
1883         int err = 0;
1884         unsigned long flags;
1885         unsigned int tuning_count = 0;
1886         bool hs400_tuning;
1887
1888         sdhci_runtime_pm_get(host);
1889         spin_lock_irqsave(&host->lock, flags);
1890
1891         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1892         host->flags &= ~SDHCI_HS400_TUNING;
1893
1894         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1895                 tuning_count = host->tuning_count;
1896
1897         /*
1898          * The Host Controller needs tuning in case of SDR104 and DDR50
1899          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1900          * the Capabilities register.
1901          * If the Host Controller supports the HS200 mode then the
1902          * tuning function has to be executed.
1903          */
1904         switch (host->timing) {
1905         /* HS400 tuning is done in HS200 mode */
1906         case MMC_TIMING_MMC_HS400:
1907                 err = -EINVAL;
1908                 goto out_unlock;
1909
1910         case MMC_TIMING_MMC_HS200:
1911                 /*
1912                  * Periodic re-tuning for HS400 is not expected to be needed, so
1913                  * disable it here.
1914                  */
1915                 if (hs400_tuning)
1916                         tuning_count = 0;
1917                 break;
1918
1919         case MMC_TIMING_UHS_SDR104:
1920         case MMC_TIMING_UHS_DDR50:
1921                 break;
1922
1923         case MMC_TIMING_UHS_SDR50:
1924                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1925                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1926                         break;
1927                 /* FALLTHROUGH */
1928
1929         default:
1930                 goto out_unlock;
1931         }
1932
1933         if (host->ops->platform_execute_tuning) {
1934                 spin_unlock_irqrestore(&host->lock, flags);
1935                 err = host->ops->platform_execute_tuning(host, opcode);
1936                 sdhci_runtime_pm_put(host);
1937                 return err;
1938         }
1939
1940         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1941         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1942         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1943                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1944         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1945
1946         /*
1947          * As per the Host Controller spec v3.00, tuning command
1948          * generates Buffer Read Ready interrupt, so enable that.
1949          *
1950          * Note: The spec clearly says that when tuning sequence
1951          * is being performed, the controller does not generate
1952          * interrupts other than Buffer Read Ready interrupt. But
1953          * to make sure we don't hit a controller bug, we _only_
1954          * enable Buffer Read Ready interrupt here.
1955          */
1956         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1957         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1958
1959         /*
1960          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1961          * of loops reaches 40 times or a timeout of 150ms occurs.
1962          */
1963         do {
1964                 struct mmc_command cmd = {0};
1965                 struct mmc_request mrq = {NULL};
1966
1967                 cmd.opcode = opcode;
1968                 cmd.arg = 0;
1969                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1970                 cmd.retries = 0;
1971                 cmd.data = NULL;
1972                 cmd.error = 0;
1973
1974                 if (tuning_loop_counter-- == 0)
1975                         break;
1976
1977                 mrq.cmd = &cmd;
1978                 host->mrq = &mrq;
1979
1980                 /*
1981                  * In response to CMD19, the card sends 64 bytes of tuning
1982                  * block to the Host Controller. So we set the block size
1983                  * to 64 here.
1984                  */
1985                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1986                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1987                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1988                                              SDHCI_BLOCK_SIZE);
1989                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1990                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1991                                              SDHCI_BLOCK_SIZE);
1992                 } else {
1993                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1994                                      SDHCI_BLOCK_SIZE);
1995                 }
1996
1997                 /*
1998                  * The tuning block is sent by the card to the host controller.
1999                  * So we set the TRNS_READ bit in the Transfer Mode register.
2000                  * This also takes care of setting DMA Enable and Multi Block
2001                  * Select in the same register to 0.
2002                  */
2003                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2004
2005                 sdhci_send_command(host, &cmd);
2006
2007                 host->cmd = NULL;
2008                 host->mrq = NULL;
2009
2010                 spin_unlock_irqrestore(&host->lock, flags);
2011                 /* Wait for Buffer Read Ready interrupt */
2012                 wait_event_interruptible_timeout(host->buf_ready_int,
2013                                         (host->tuning_done == 1),
2014                                         msecs_to_jiffies(50));
2015                 spin_lock_irqsave(&host->lock, flags);
2016
2017                 if (!host->tuning_done) {
2018                         pr_info(DRIVER_NAME ": Timeout waiting for "
2019                                 "Buffer Read Ready interrupt during tuning "
2020                                 "procedure, falling back to fixed sampling "
2021                                 "clock\n");
2022                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2023                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2024                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2025                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2026
2027                         err = -EIO;
2028                         goto out;
2029                 }
2030
2031                 host->tuning_done = 0;
2032
2033                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2034
2035                 /* eMMC spec does not require a delay between tuning cycles */
2036                 if (opcode == MMC_SEND_TUNING_BLOCK)
2037                         mdelay(1);
2038         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2039
2040         /*
2041          * The Host Driver has exhausted the maximum number of loops allowed,
2042          * so use fixed sampling frequency.
2043          */
2044         if (tuning_loop_counter < 0) {
2045                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2046                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2047         }
2048         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2049                 pr_info(DRIVER_NAME ": Tuning procedure"
2050                         " failed, falling back to fixed sampling"
2051                         " clock\n");
2052                 err = -EIO;
2053         }
2054
2055 out:
2056         if (tuning_count) {
2057                 /*
2058                  * In case tuning fails, host controllers which support
2059                  * re-tuning can try tuning again at a later time, when the
2060                  * re-tuning timer expires.  So for these controllers, we
2061                  * return 0. Since there might be other controllers who do not
2062                  * have this capability, we return error for them.
2063                  */
2064                 err = 0;
2065         }
2066
2067         host->mmc->retune_period = err ? 0 : tuning_count;
2068
2069         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2070         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2071 out_unlock:
2072         spin_unlock_irqrestore(&host->lock, flags);
2073         sdhci_runtime_pm_put(host);
2074
2075         return err;
2076 }
2077
2078 static int sdhci_select_drive_strength(struct mmc_card *card,
2079                                        unsigned int max_dtr, int host_drv,
2080                                        int card_drv, int *drv_type)
2081 {
2082         struct sdhci_host *host = mmc_priv(card->host);
2083
2084         if (!host->ops->select_drive_strength)
2085                 return 0;
2086
2087         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2088                                                 card_drv, drv_type);
2089 }
2090
2091 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2092 {
2093         /* Host Controller v3.00 defines preset value registers */
2094         if (host->version < SDHCI_SPEC_300)
2095                 return;
2096
2097         /*
2098          * We only enable or disable Preset Value if they are not already
2099          * enabled or disabled respectively. Otherwise, we bail out.
2100          */
2101         if (host->preset_enabled != enable) {
2102                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2103
2104                 if (enable)
2105                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2106                 else
2107                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2108
2109                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2110
2111                 if (enable)
2112                         host->flags |= SDHCI_PV_ENABLED;
2113                 else
2114                         host->flags &= ~SDHCI_PV_ENABLED;
2115
2116                 host->preset_enabled = enable;
2117         }
2118 }
2119
2120 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2121                                 int err)
2122 {
2123         struct sdhci_host *host = mmc_priv(mmc);
2124         struct mmc_data *data = mrq->data;
2125
2126         if (host->flags & SDHCI_REQ_USE_DMA) {
2127                 if (data->host_cookie == COOKIE_GIVEN ||
2128                                 data->host_cookie == COOKIE_MAPPED)
2129                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2130                                          data->flags & MMC_DATA_WRITE ?
2131                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2132                 data->host_cookie = COOKIE_UNMAPPED;
2133         }
2134 }
2135
2136 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2137                                        struct mmc_data *data)
2138 {
2139         int sg_count;
2140
2141         if (data->host_cookie == COOKIE_MAPPED) {
2142                 data->host_cookie = COOKIE_GIVEN;
2143                 return data->sg_count;
2144         }
2145
2146         WARN_ON(data->host_cookie == COOKIE_GIVEN);
2147
2148         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2149                                 data->flags & MMC_DATA_WRITE ?
2150                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2151
2152         if (sg_count == 0)
2153                 return -ENOSPC;
2154
2155         data->sg_count = sg_count;
2156         data->host_cookie = COOKIE_MAPPED;
2157
2158         return sg_count;
2159 }
2160
2161 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2162                                bool is_first_req)
2163 {
2164         struct sdhci_host *host = mmc_priv(mmc);
2165
2166         mrq->data->host_cookie = COOKIE_UNMAPPED;
2167
2168         if (host->flags & SDHCI_REQ_USE_DMA)
2169                 sdhci_pre_dma_transfer(host, mrq->data);
2170 }
2171
2172 static void sdhci_card_event(struct mmc_host *mmc)
2173 {
2174         struct sdhci_host *host = mmc_priv(mmc);
2175         unsigned long flags;
2176         int present;
2177
2178         /* First check if client has provided their own card event */
2179         if (host->ops->card_event)
2180                 host->ops->card_event(host);
2181
2182         present = sdhci_do_get_cd(host);
2183
2184         spin_lock_irqsave(&host->lock, flags);
2185
2186         /* Check host->mrq first in case we are runtime suspended */
2187         if (host->mrq && !present) {
2188                 pr_err("%s: Card removed during transfer!\n",
2189                         mmc_hostname(host->mmc));
2190                 pr_err("%s: Resetting controller.\n",
2191                         mmc_hostname(host->mmc));
2192
2193                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2194                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2195
2196                 host->mrq->cmd->error = -ENOMEDIUM;
2197                 tasklet_schedule(&host->finish_tasklet);
2198         }
2199
2200         spin_unlock_irqrestore(&host->lock, flags);
2201 }
2202
2203 static const struct mmc_host_ops sdhci_ops = {
2204         .request        = sdhci_request,
2205         .post_req       = sdhci_post_req,
2206         .pre_req        = sdhci_pre_req,
2207         .set_ios        = sdhci_set_ios,
2208         .get_cd         = sdhci_get_cd,
2209         .get_ro         = sdhci_get_ro,
2210         .hw_reset       = sdhci_hw_reset,
2211         .enable_sdio_irq = sdhci_enable_sdio_irq,
2212         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2213         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2214         .execute_tuning                 = sdhci_execute_tuning,
2215         .select_drive_strength          = sdhci_select_drive_strength,
2216         .card_event                     = sdhci_card_event,
2217         .card_busy      = sdhci_card_busy,
2218 };
2219
2220 /*****************************************************************************\
2221  *                                                                           *
2222  * Tasklets                                                                  *
2223  *                                                                           *
2224 \*****************************************************************************/
2225
2226 static void sdhci_tasklet_finish(unsigned long param)
2227 {
2228         struct sdhci_host *host;
2229         unsigned long flags;
2230         struct mmc_request *mrq;
2231
2232         host = (struct sdhci_host*)param;
2233
2234         spin_lock_irqsave(&host->lock, flags);
2235
2236         /*
2237          * If this tasklet gets rescheduled while running, it will
2238          * be run again afterwards but without any active request.
2239          */
2240         if (!host->mrq) {
2241                 spin_unlock_irqrestore(&host->lock, flags);
2242                 return;
2243         }
2244
2245         del_timer(&host->timer);
2246
2247         mrq = host->mrq;
2248
2249         /*
2250          * The controller needs a reset of internal state machines
2251          * upon error conditions.
2252          */
2253         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2254             ((mrq->cmd && mrq->cmd->error) ||
2255              (mrq->sbc && mrq->sbc->error) ||
2256              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2257                             (mrq->data->stop && mrq->data->stop->error))) ||
2258              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2259
2260                 /* Some controllers need this kick or reset won't work here */
2261                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2262                         /* This is to force an update */
2263                         host->ops->set_clock(host, host->clock);
2264
2265                 /* Spec says we should do both at the same time, but Ricoh
2266                    controllers do not like that. */
2267                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2268                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2269         }
2270
2271         host->mrq = NULL;
2272         host->cmd = NULL;
2273         host->data = NULL;
2274
2275 #ifndef SDHCI_USE_LEDS_CLASS
2276         sdhci_deactivate_led(host);
2277 #endif
2278
2279         mmiowb();
2280         spin_unlock_irqrestore(&host->lock, flags);
2281
2282         mmc_request_done(host->mmc, mrq);
2283         sdhci_runtime_pm_put(host);
2284 }
2285
2286 static void sdhci_timeout_timer(unsigned long data)
2287 {
2288         struct sdhci_host *host;
2289         unsigned long flags;
2290
2291         host = (struct sdhci_host*)data;
2292
2293         spin_lock_irqsave(&host->lock, flags);
2294
2295         if (host->mrq) {
2296                 pr_err("%s: Timeout waiting for hardware "
2297                         "interrupt.\n", mmc_hostname(host->mmc));
2298                 sdhci_dumpregs(host);
2299
2300                 if (host->data) {
2301                         host->data->error = -ETIMEDOUT;
2302                         sdhci_finish_data(host);
2303                 } else {
2304                         if (host->cmd)
2305                                 host->cmd->error = -ETIMEDOUT;
2306                         else
2307                                 host->mrq->cmd->error = -ETIMEDOUT;
2308
2309                         tasklet_schedule(&host->finish_tasklet);
2310                 }
2311         }
2312
2313         mmiowb();
2314         spin_unlock_irqrestore(&host->lock, flags);
2315 }
2316
2317 /*****************************************************************************\
2318  *                                                                           *
2319  * Interrupt handling                                                        *
2320  *                                                                           *
2321 \*****************************************************************************/
2322
2323 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2324 {
2325         BUG_ON(intmask == 0);
2326
2327         if (!host->cmd) {
2328                 pr_err("%s: Got command interrupt 0x%08x even "
2329                         "though no command operation was in progress.\n",
2330                         mmc_hostname(host->mmc), (unsigned)intmask);
2331                 sdhci_dumpregs(host);
2332                 return;
2333         }
2334
2335         if (intmask & SDHCI_INT_TIMEOUT)
2336                 host->cmd->error = -ETIMEDOUT;
2337         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2338                         SDHCI_INT_INDEX))
2339                 host->cmd->error = -EILSEQ;
2340
2341         if (host->cmd->error) {
2342                 tasklet_schedule(&host->finish_tasklet);
2343                 return;
2344         }
2345
2346         /*
2347          * The host can send and interrupt when the busy state has
2348          * ended, allowing us to wait without wasting CPU cycles.
2349          * Unfortunately this is overloaded on the "data complete"
2350          * interrupt, so we need to take some care when handling
2351          * it.
2352          *
2353          * Note: The 1.0 specification is a bit ambiguous about this
2354          *       feature so there might be some problems with older
2355          *       controllers.
2356          */
2357         if (host->cmd->flags & MMC_RSP_BUSY) {
2358                 if (host->cmd->data)
2359                         DBG("Cannot wait for busy signal when also "
2360                                 "doing a data transfer");
2361                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2362                                 && !host->busy_handle) {
2363                         /* Mark that command complete before busy is ended */
2364                         host->busy_handle = 1;
2365                         return;
2366                 }
2367
2368                 /* The controller does not support the end-of-busy IRQ,
2369                  * fall through and take the SDHCI_INT_RESPONSE */
2370         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2371                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2372                 *mask &= ~SDHCI_INT_DATA_END;
2373         }
2374
2375         if (intmask & SDHCI_INT_RESPONSE)
2376                 sdhci_finish_command(host);
2377 }
2378
2379 #ifdef CONFIG_MMC_DEBUG
2380 static void sdhci_adma_show_error(struct sdhci_host *host)
2381 {
2382         const char *name = mmc_hostname(host->mmc);
2383         void *desc = host->adma_table;
2384
2385         sdhci_dumpregs(host);
2386
2387         while (true) {
2388                 struct sdhci_adma2_64_desc *dma_desc = desc;
2389
2390                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2391                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2392                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2393                             le32_to_cpu(dma_desc->addr_lo),
2394                             le16_to_cpu(dma_desc->len),
2395                             le16_to_cpu(dma_desc->cmd));
2396                 else
2397                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2398                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2399                             le16_to_cpu(dma_desc->len),
2400                             le16_to_cpu(dma_desc->cmd));
2401
2402                 desc += host->desc_sz;
2403
2404                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2405                         break;
2406         }
2407 }
2408 #else
2409 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2410 #endif
2411
2412 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2413 {
2414         u32 command;
2415         BUG_ON(intmask == 0);
2416
2417         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2418         if (intmask & SDHCI_INT_DATA_AVAIL) {
2419                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2420                 if (command == MMC_SEND_TUNING_BLOCK ||
2421                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2422                         host->tuning_done = 1;
2423                         wake_up(&host->buf_ready_int);
2424                         return;
2425                 }
2426         }
2427
2428         if (!host->data) {
2429                 /*
2430                  * The "data complete" interrupt is also used to
2431                  * indicate that a busy state has ended. See comment
2432                  * above in sdhci_cmd_irq().
2433                  */
2434                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2435                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2436                                 host->cmd->error = -ETIMEDOUT;
2437                                 tasklet_schedule(&host->finish_tasklet);
2438                                 return;
2439                         }
2440                         if (intmask & SDHCI_INT_DATA_END) {
2441                                 /*
2442                                  * Some cards handle busy-end interrupt
2443                                  * before the command completed, so make
2444                                  * sure we do things in the proper order.
2445                                  */
2446                                 if (host->busy_handle)
2447                                         sdhci_finish_command(host);
2448                                 else
2449                                         host->busy_handle = 1;
2450                                 return;
2451                         }
2452                 }
2453
2454                 pr_err("%s: Got data interrupt 0x%08x even "
2455                         "though no data operation was in progress.\n",
2456                         mmc_hostname(host->mmc), (unsigned)intmask);
2457                 sdhci_dumpregs(host);
2458
2459                 return;
2460         }
2461
2462         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2463                 host->data->error = -ETIMEDOUT;
2464         else if (intmask & SDHCI_INT_DATA_END_BIT)
2465                 host->data->error = -EILSEQ;
2466         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2467                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2468                         != MMC_BUS_TEST_R)
2469                 host->data->error = -EILSEQ;
2470         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2471                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2472                 sdhci_adma_show_error(host);
2473                 host->data->error = -EIO;
2474                 if (host->ops->adma_workaround)
2475                         host->ops->adma_workaround(host, intmask);
2476         }
2477
2478         if (host->data->error)
2479                 sdhci_finish_data(host);
2480         else {
2481                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2482                         sdhci_transfer_pio(host);
2483
2484                 /*
2485                  * We currently don't do anything fancy with DMA
2486                  * boundaries, but as we can't disable the feature
2487                  * we need to at least restart the transfer.
2488                  *
2489                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2490                  * should return a valid address to continue from, but as
2491                  * some controllers are faulty, don't trust them.
2492                  */
2493                 if (intmask & SDHCI_INT_DMA_END) {
2494                         u32 dmastart, dmanow;
2495                         dmastart = sg_dma_address(host->data->sg);
2496                         dmanow = dmastart + host->data->bytes_xfered;
2497                         /*
2498                          * Force update to the next DMA block boundary.
2499                          */
2500                         dmanow = (dmanow &
2501                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2502                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2503                         host->data->bytes_xfered = dmanow - dmastart;
2504                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2505                                 " next 0x%08x\n",
2506                                 mmc_hostname(host->mmc), dmastart,
2507                                 host->data->bytes_xfered, dmanow);
2508                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2509                 }
2510
2511                 if (intmask & SDHCI_INT_DATA_END) {
2512                         if (host->cmd) {
2513                                 /*
2514                                  * Data managed to finish before the
2515                                  * command completed. Make sure we do
2516                                  * things in the proper order.
2517                                  */
2518                                 host->data_early = 1;
2519                         } else {
2520                                 sdhci_finish_data(host);
2521                         }
2522                 }
2523         }
2524 }
2525
2526 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2527 {
2528         irqreturn_t result = IRQ_NONE;
2529         struct sdhci_host *host = dev_id;
2530         u32 intmask, mask, unexpected = 0;
2531         int max_loops = 16;
2532
2533         spin_lock(&host->lock);
2534
2535         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2536                 spin_unlock(&host->lock);
2537                 return IRQ_NONE;
2538         }
2539
2540         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2541         if (!intmask || intmask == 0xffffffff) {
2542                 result = IRQ_NONE;
2543                 goto out;
2544         }
2545
2546         do {
2547                 /* Clear selected interrupts. */
2548                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2549                                   SDHCI_INT_BUS_POWER);
2550                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2551
2552                 DBG("*** %s got interrupt: 0x%08x\n",
2553                         mmc_hostname(host->mmc), intmask);
2554
2555                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2556                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2557                                       SDHCI_CARD_PRESENT;
2558
2559                         /*
2560                          * There is a observation on i.mx esdhc.  INSERT
2561                          * bit will be immediately set again when it gets
2562                          * cleared, if a card is inserted.  We have to mask
2563                          * the irq to prevent interrupt storm which will
2564                          * freeze the system.  And the REMOVE gets the
2565                          * same situation.
2566                          *
2567                          * More testing are needed here to ensure it works
2568                          * for other platforms though.
2569                          */
2570                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2571                                        SDHCI_INT_CARD_REMOVE);
2572                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2573                                                SDHCI_INT_CARD_INSERT;
2574                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2575                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2576
2577                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2578                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2579
2580                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2581                                                        SDHCI_INT_CARD_REMOVE);
2582                         result = IRQ_WAKE_THREAD;
2583                 }
2584
2585                 if (intmask & SDHCI_INT_CMD_MASK)
2586                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2587                                       &intmask);
2588
2589                 if (intmask & SDHCI_INT_DATA_MASK)
2590                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2591
2592                 if (intmask & SDHCI_INT_BUS_POWER)
2593                         pr_err("%s: Card is consuming too much power!\n",
2594                                 mmc_hostname(host->mmc));
2595
2596                 if (intmask & SDHCI_INT_CARD_INT) {
2597                         sdhci_enable_sdio_irq_nolock(host, false);
2598                         host->thread_isr |= SDHCI_INT_CARD_INT;
2599                         result = IRQ_WAKE_THREAD;
2600                 }
2601
2602                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2603                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2604                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2605                              SDHCI_INT_CARD_INT);
2606
2607                 if (intmask) {
2608                         unexpected |= intmask;
2609                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2610                 }
2611
2612                 if (result == IRQ_NONE)
2613                         result = IRQ_HANDLED;
2614
2615                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2616         } while (intmask && --max_loops);
2617 out:
2618         spin_unlock(&host->lock);
2619
2620         if (unexpected) {
2621                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2622                            mmc_hostname(host->mmc), unexpected);
2623                 sdhci_dumpregs(host);
2624         }
2625
2626         return result;
2627 }
2628
2629 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2630 {
2631         struct sdhci_host *host = dev_id;
2632         unsigned long flags;
2633         u32 isr;
2634
2635         spin_lock_irqsave(&host->lock, flags);
2636         isr = host->thread_isr;
2637         host->thread_isr = 0;
2638         spin_unlock_irqrestore(&host->lock, flags);
2639
2640         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2641                 sdhci_card_event(host->mmc);
2642                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2643         }
2644
2645         if (isr & SDHCI_INT_CARD_INT) {
2646                 sdio_run_irqs(host->mmc);
2647
2648                 spin_lock_irqsave(&host->lock, flags);
2649                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2650                         sdhci_enable_sdio_irq_nolock(host, true);
2651                 spin_unlock_irqrestore(&host->lock, flags);
2652         }
2653
2654         return isr ? IRQ_HANDLED : IRQ_NONE;
2655 }
2656
2657 /*****************************************************************************\
2658  *                                                                           *
2659  * Suspend/resume                                                            *
2660  *                                                                           *
2661 \*****************************************************************************/
2662
2663 #ifdef CONFIG_PM
2664 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2665 {
2666         u8 val;
2667         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2668                         | SDHCI_WAKE_ON_INT;
2669
2670         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2671         val |= mask ;
2672         /* Avoid fake wake up */
2673         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2674                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2675         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2676 }
2677 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2678
2679 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2680 {
2681         u8 val;
2682         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2683                         | SDHCI_WAKE_ON_INT;
2684
2685         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2686         val &= ~mask;
2687         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2688 }
2689
2690 int sdhci_suspend_host(struct sdhci_host *host)
2691 {
2692         sdhci_disable_card_detection(host);
2693
2694         mmc_retune_timer_stop(host->mmc);
2695         mmc_retune_needed(host->mmc);
2696
2697         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2698                 host->ier = 0;
2699                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2700                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2701                 free_irq(host->irq, host);
2702         } else {
2703                 sdhci_enable_irq_wakeups(host);
2704                 enable_irq_wake(host->irq);
2705         }
2706         return 0;
2707 }
2708
2709 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2710
2711 int sdhci_resume_host(struct sdhci_host *host)
2712 {
2713         int ret = 0;
2714
2715         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2716                 if (host->ops->enable_dma)
2717                         host->ops->enable_dma(host);
2718         }
2719
2720         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2721             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2722                 /* Card keeps power but host controller does not */
2723                 sdhci_init(host, 0);
2724                 host->pwr = 0;
2725                 host->clock = 0;
2726                 sdhci_do_set_ios(host, &host->mmc->ios);
2727         } else {
2728                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2729                 mmiowb();
2730         }
2731
2732         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2733                 ret = request_threaded_irq(host->irq, sdhci_irq,
2734                                            sdhci_thread_irq, IRQF_SHARED,
2735                                            mmc_hostname(host->mmc), host);
2736                 if (ret)
2737                         return ret;
2738         } else {
2739                 sdhci_disable_irq_wakeups(host);
2740                 disable_irq_wake(host->irq);
2741         }
2742
2743         sdhci_enable_card_detection(host);
2744
2745         return ret;
2746 }
2747
2748 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2749
2750 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2751 {
2752         return pm_runtime_get_sync(host->mmc->parent);
2753 }
2754
2755 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2756 {
2757         pm_runtime_mark_last_busy(host->mmc->parent);
2758         return pm_runtime_put_autosuspend(host->mmc->parent);
2759 }
2760
2761 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2762 {
2763         if (host->bus_on)
2764                 return;
2765         host->bus_on = true;
2766         pm_runtime_get_noresume(host->mmc->parent);
2767 }
2768
2769 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2770 {
2771         if (!host->bus_on)
2772                 return;
2773         host->bus_on = false;
2774         pm_runtime_put_noidle(host->mmc->parent);
2775 }
2776
2777 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2778 {
2779         unsigned long flags;
2780
2781         mmc_retune_timer_stop(host->mmc);
2782         mmc_retune_needed(host->mmc);
2783
2784         spin_lock_irqsave(&host->lock, flags);
2785         host->ier &= SDHCI_INT_CARD_INT;
2786         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2787         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2788         spin_unlock_irqrestore(&host->lock, flags);
2789
2790         synchronize_hardirq(host->irq);
2791
2792         spin_lock_irqsave(&host->lock, flags);
2793         host->runtime_suspended = true;
2794         spin_unlock_irqrestore(&host->lock, flags);
2795
2796         return 0;
2797 }
2798 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2799
2800 int sdhci_runtime_resume_host(struct sdhci_host *host)
2801 {
2802         unsigned long flags;
2803         int host_flags = host->flags;
2804
2805         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2806                 if (host->ops->enable_dma)
2807                         host->ops->enable_dma(host);
2808         }
2809
2810         sdhci_init(host, 0);
2811
2812         /* Force clock and power re-program */
2813         host->pwr = 0;
2814         host->clock = 0;
2815         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2816         sdhci_do_set_ios(host, &host->mmc->ios);
2817
2818         if ((host_flags & SDHCI_PV_ENABLED) &&
2819                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2820                 spin_lock_irqsave(&host->lock, flags);
2821                 sdhci_enable_preset_value(host, true);
2822                 spin_unlock_irqrestore(&host->lock, flags);
2823         }
2824
2825         spin_lock_irqsave(&host->lock, flags);
2826
2827         host->runtime_suspended = false;
2828
2829         /* Enable SDIO IRQ */
2830         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2831                 sdhci_enable_sdio_irq_nolock(host, true);
2832
2833         /* Enable Card Detection */
2834         sdhci_enable_card_detection(host);
2835
2836         spin_unlock_irqrestore(&host->lock, flags);
2837
2838         return 0;
2839 }
2840 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2841
2842 #endif /* CONFIG_PM */
2843
2844 /*****************************************************************************\
2845  *                                                                           *
2846  * Device allocation/registration                                            *
2847  *                                                                           *
2848 \*****************************************************************************/
2849
2850 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2851         size_t priv_size)
2852 {
2853         struct mmc_host *mmc;
2854         struct sdhci_host *host;
2855
2856         WARN_ON(dev == NULL);
2857
2858         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2859         if (!mmc)
2860                 return ERR_PTR(-ENOMEM);
2861
2862         host = mmc_priv(mmc);
2863         host->mmc = mmc;
2864         host->mmc_host_ops = sdhci_ops;
2865         mmc->ops = &host->mmc_host_ops;
2866
2867         return host;
2868 }
2869
2870 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2871
2872 int sdhci_add_host(struct sdhci_host *host)
2873 {
2874         struct mmc_host *mmc;
2875         u32 caps[2] = {0, 0};
2876         u32 max_current_caps;
2877         unsigned int ocr_avail;
2878         unsigned int override_timeout_clk;
2879         u32 max_clk;
2880         int ret;
2881
2882         WARN_ON(host == NULL);
2883         if (host == NULL)
2884                 return -EINVAL;
2885
2886         mmc = host->mmc;
2887
2888         if (debug_quirks)
2889                 host->quirks = debug_quirks;
2890         if (debug_quirks2)
2891                 host->quirks2 = debug_quirks2;
2892
2893         override_timeout_clk = host->timeout_clk;
2894
2895         sdhci_do_reset(host, SDHCI_RESET_ALL);
2896
2897         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2898         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2899                                 >> SDHCI_SPEC_VER_SHIFT;
2900         if (host->version > SDHCI_SPEC_300) {
2901                 pr_err("%s: Unknown controller version (%d). "
2902                         "You may experience problems.\n", mmc_hostname(mmc),
2903                         host->version);
2904         }
2905
2906         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2907                 sdhci_readl(host, SDHCI_CAPABILITIES);
2908
2909         if (host->version >= SDHCI_SPEC_300)
2910                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2911                         host->caps1 :
2912                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2913
2914         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2915                 host->flags |= SDHCI_USE_SDMA;
2916         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2917                 DBG("Controller doesn't have SDMA capability\n");
2918         else
2919                 host->flags |= SDHCI_USE_SDMA;
2920
2921         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2922                 (host->flags & SDHCI_USE_SDMA)) {
2923                 DBG("Disabling DMA as it is marked broken\n");
2924                 host->flags &= ~SDHCI_USE_SDMA;
2925         }
2926
2927         if ((host->version >= SDHCI_SPEC_200) &&
2928                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2929                 host->flags |= SDHCI_USE_ADMA;
2930
2931         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2932                 (host->flags & SDHCI_USE_ADMA)) {
2933                 DBG("Disabling ADMA as it is marked broken\n");
2934                 host->flags &= ~SDHCI_USE_ADMA;
2935         }
2936
2937         /*
2938          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2939          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2940          * that during the first call to ->enable_dma().  Similarly
2941          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2942          * implement.
2943          */
2944         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2945                 host->flags |= SDHCI_USE_64_BIT_DMA;
2946
2947         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2948                 if (host->ops->enable_dma) {
2949                         if (host->ops->enable_dma(host)) {
2950                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2951                                         mmc_hostname(mmc));
2952                                 host->flags &=
2953                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2954                         }
2955                 }
2956         }
2957
2958         /* SDMA does not support 64-bit DMA */
2959         if (host->flags & SDHCI_USE_64_BIT_DMA)
2960                 host->flags &= ~SDHCI_USE_SDMA;
2961
2962         if (host->flags & SDHCI_USE_ADMA) {
2963                 /*
2964                  * The DMA descriptor table size is calculated as the maximum
2965                  * number of segments times 2, to allow for an alignment
2966                  * descriptor for each segment, plus 1 for a nop end descriptor,
2967                  * all multipled by the descriptor size.
2968                  */
2969                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2970                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2971                                               SDHCI_ADMA2_64_DESC_SZ;
2972                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2973                                                 SDHCI_ADMA2_64_ALIGN;
2974                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2975                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
2976                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2977                 } else {
2978                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2979                                               SDHCI_ADMA2_32_DESC_SZ;
2980                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2981                                                 SDHCI_ADMA2_32_ALIGN;
2982                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2983                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
2984                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2985                 }
2986                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2987                                                       host->adma_table_sz,
2988                                                       &host->adma_addr,
2989                                                       GFP_KERNEL);
2990                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2991                 if (!host->adma_table || !host->align_buffer) {
2992                         if (host->adma_table)
2993                                 dma_free_coherent(mmc_dev(mmc),
2994                                                   host->adma_table_sz,
2995                                                   host->adma_table,
2996                                                   host->adma_addr);
2997                         kfree(host->align_buffer);
2998                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2999                                 mmc_hostname(mmc));
3000                         host->flags &= ~SDHCI_USE_ADMA;
3001                         host->adma_table = NULL;
3002                         host->align_buffer = NULL;
3003                 } else if (host->adma_addr & host->align_mask) {
3004                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3005                                 mmc_hostname(mmc));
3006                         host->flags &= ~SDHCI_USE_ADMA;
3007                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3008                                           host->adma_table, host->adma_addr);
3009                         kfree(host->align_buffer);
3010                         host->adma_table = NULL;
3011                         host->align_buffer = NULL;
3012                 }
3013         }
3014
3015         /*
3016          * If we use DMA, then it's up to the caller to set the DMA
3017          * mask, but PIO does not need the hw shim so we set a new
3018          * mask here in that case.
3019          */
3020         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3021                 host->dma_mask = DMA_BIT_MASK(64);
3022                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3023         }
3024
3025         if (host->version >= SDHCI_SPEC_300)
3026                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3027                         >> SDHCI_CLOCK_BASE_SHIFT;
3028         else
3029                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3030                         >> SDHCI_CLOCK_BASE_SHIFT;
3031
3032         host->max_clk *= 1000000;
3033         if (host->max_clk == 0 || host->quirks &
3034                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3035                 if (!host->ops->get_max_clock) {
3036                         pr_err("%s: Hardware doesn't specify base clock "
3037                                "frequency.\n", mmc_hostname(mmc));
3038                         return -ENODEV;
3039                 }
3040                 host->max_clk = host->ops->get_max_clock(host);
3041         }
3042
3043         /*
3044          * In case of Host Controller v3.00, find out whether clock
3045          * multiplier is supported.
3046          */
3047         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3048                         SDHCI_CLOCK_MUL_SHIFT;
3049
3050         /*
3051          * In case the value in Clock Multiplier is 0, then programmable
3052          * clock mode is not supported, otherwise the actual clock
3053          * multiplier is one more than the value of Clock Multiplier
3054          * in the Capabilities Register.
3055          */
3056         if (host->clk_mul)
3057                 host->clk_mul += 1;
3058
3059         /*
3060          * Set host parameters.
3061          */
3062         max_clk = host->max_clk;
3063
3064         if (host->ops->get_min_clock)
3065                 mmc->f_min = host->ops->get_min_clock(host);
3066         else if (host->version >= SDHCI_SPEC_300) {
3067                 if (host->clk_mul) {
3068                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3069                         max_clk = host->max_clk * host->clk_mul;
3070                 } else
3071                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3072         } else
3073                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3074
3075         if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3076                 mmc->f_max = max_clk;
3077
3078         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3079                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3080                                         SDHCI_TIMEOUT_CLK_SHIFT;
3081                 if (host->timeout_clk == 0) {
3082                         if (host->ops->get_timeout_clock) {
3083                                 host->timeout_clk =
3084                                         host->ops->get_timeout_clock(host);
3085                         } else {
3086                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3087                                         mmc_hostname(mmc));
3088                                 return -ENODEV;
3089                         }
3090                 }
3091
3092                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3093                         host->timeout_clk *= 1000;
3094
3095                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3096                         host->ops->get_max_timeout_count(host) : 1 << 27;
3097                 mmc->max_busy_timeout /= host->timeout_clk;
3098         }
3099
3100         if (override_timeout_clk)
3101                 host->timeout_clk = override_timeout_clk;
3102
3103         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3104         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3105
3106         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3107                 host->flags |= SDHCI_AUTO_CMD12;
3108
3109         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3110         if ((host->version >= SDHCI_SPEC_300) &&
3111             ((host->flags & SDHCI_USE_ADMA) ||
3112              !(host->flags & SDHCI_USE_SDMA)) &&
3113              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3114                 host->flags |= SDHCI_AUTO_CMD23;
3115                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3116         } else {
3117                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3118         }
3119
3120         /*
3121          * A controller may support 8-bit width, but the board itself
3122          * might not have the pins brought out.  Boards that support
3123          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3124          * their platform code before calling sdhci_add_host(), and we
3125          * won't assume 8-bit width for hosts without that CAP.
3126          */
3127         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3128                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3129
3130         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3131                 mmc->caps &= ~MMC_CAP_CMD23;
3132
3133         if (caps[0] & SDHCI_CAN_DO_HISPD)
3134                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3135
3136         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3137             !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3138             IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3139                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3140
3141         /* If there are external regulators, get them */
3142         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3143                 return -EPROBE_DEFER;
3144
3145         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3146         if (!IS_ERR(mmc->supply.vqmmc)) {
3147                 ret = regulator_enable(mmc->supply.vqmmc);
3148                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3149                                                     1950000))
3150                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3151                                         SDHCI_SUPPORT_SDR50 |
3152                                         SDHCI_SUPPORT_DDR50);
3153                 if (ret) {
3154                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3155                                 mmc_hostname(mmc), ret);
3156                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3157                 }
3158         }
3159
3160         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3161                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3162                        SDHCI_SUPPORT_DDR50);
3163
3164         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3165         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3166                        SDHCI_SUPPORT_DDR50))
3167                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3168
3169         /* SDR104 supports also implies SDR50 support */
3170         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3171                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3172                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3173                  * field can be promoted to support HS200.
3174                  */
3175                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3176                         mmc->caps2 |= MMC_CAP2_HS200;
3177         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3178                 mmc->caps |= MMC_CAP_UHS_SDR50;
3179
3180         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3181             (caps[1] & SDHCI_SUPPORT_HS400))
3182                 mmc->caps2 |= MMC_CAP2_HS400;
3183
3184         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3185             (IS_ERR(mmc->supply.vqmmc) ||
3186              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3187                                              1300000)))
3188                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3189
3190         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3191                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3192                 mmc->caps |= MMC_CAP_UHS_DDR50;
3193
3194         /* Does the host need tuning for SDR50? */
3195         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3196                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3197
3198         /* Does the host need tuning for SDR104 / HS200? */
3199         if (mmc->caps2 & MMC_CAP2_HS200)
3200                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3201
3202         /* Driver Type(s) (A, C, D) supported by the host */
3203         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3204                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3205         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3206                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3207         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3208                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3209
3210         /* Initial value for re-tuning timer count */
3211         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3212                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3213
3214         /*
3215          * In case Re-tuning Timer is not disabled, the actual value of
3216          * re-tuning timer will be 2 ^ (n - 1).
3217          */
3218         if (host->tuning_count)
3219                 host->tuning_count = 1 << (host->tuning_count - 1);
3220
3221         /* Re-tuning mode supported by the Host Controller */
3222         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3223                              SDHCI_RETUNING_MODE_SHIFT;
3224
3225         ocr_avail = 0;
3226
3227         /*
3228          * According to SD Host Controller spec v3.00, if the Host System
3229          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3230          * the value is meaningful only if Voltage Support in the Capabilities
3231          * register is set. The actual current value is 4 times the register
3232          * value.
3233          */
3234         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3235         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3236                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3237                 if (curr > 0) {
3238
3239                         /* convert to SDHCI_MAX_CURRENT format */
3240                         curr = curr/1000;  /* convert to mA */
3241                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3242
3243                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3244                         max_current_caps =
3245                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3246                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3247                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3248                 }
3249         }
3250
3251         if (caps[0] & SDHCI_CAN_VDD_330) {
3252                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3253
3254                 mmc->max_current_330 = ((max_current_caps &
3255                                    SDHCI_MAX_CURRENT_330_MASK) >>
3256                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3257                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3258         }
3259         if (caps[0] & SDHCI_CAN_VDD_300) {
3260                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3261
3262                 mmc->max_current_300 = ((max_current_caps &
3263                                    SDHCI_MAX_CURRENT_300_MASK) >>
3264                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3265                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3266         }
3267         if (caps[0] & SDHCI_CAN_VDD_180) {
3268                 ocr_avail |= MMC_VDD_165_195;
3269
3270                 mmc->max_current_180 = ((max_current_caps &
3271                                    SDHCI_MAX_CURRENT_180_MASK) >>
3272                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3273                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3274         }
3275
3276         /* If OCR set by host, use it instead. */
3277         if (host->ocr_mask)
3278                 ocr_avail = host->ocr_mask;
3279
3280         /* If OCR set by external regulators, give it highest prio. */
3281         if (mmc->ocr_avail)
3282                 ocr_avail = mmc->ocr_avail;
3283
3284         mmc->ocr_avail = ocr_avail;
3285         mmc->ocr_avail_sdio = ocr_avail;
3286         if (host->ocr_avail_sdio)
3287                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3288         mmc->ocr_avail_sd = ocr_avail;
3289         if (host->ocr_avail_sd)
3290                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3291         else /* normal SD controllers don't support 1.8V */
3292                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3293         mmc->ocr_avail_mmc = ocr_avail;
3294         if (host->ocr_avail_mmc)
3295                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3296
3297         if (mmc->ocr_avail == 0) {
3298                 pr_err("%s: Hardware doesn't report any "
3299                         "support voltages.\n", mmc_hostname(mmc));
3300                 return -ENODEV;
3301         }
3302
3303         spin_lock_init(&host->lock);
3304
3305         /*
3306          * Maximum number of segments. Depends on if the hardware
3307          * can do scatter/gather or not.
3308          */
3309         if (host->flags & SDHCI_USE_ADMA)
3310                 mmc->max_segs = SDHCI_MAX_SEGS;
3311         else if (host->flags & SDHCI_USE_SDMA)
3312                 mmc->max_segs = 1;
3313         else /* PIO */
3314                 mmc->max_segs = SDHCI_MAX_SEGS;
3315
3316         /*
3317          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3318          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3319          * is less anyway.
3320          */
3321         mmc->max_req_size = 524288;
3322
3323         /*
3324          * Maximum segment size. Could be one segment with the maximum number
3325          * of bytes. When doing hardware scatter/gather, each entry cannot
3326          * be larger than 64 KiB though.
3327          */
3328         if (host->flags & SDHCI_USE_ADMA) {
3329                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3330                         mmc->max_seg_size = 65535;
3331                 else
3332                         mmc->max_seg_size = 65536;
3333         } else {
3334                 mmc->max_seg_size = mmc->max_req_size;
3335         }
3336
3337         /*
3338          * Maximum block size. This varies from controller to controller and
3339          * is specified in the capabilities register.
3340          */
3341         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3342                 mmc->max_blk_size = 2;
3343         } else {
3344                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3345                                 SDHCI_MAX_BLOCK_SHIFT;
3346                 if (mmc->max_blk_size >= 3) {
3347                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3348                                 mmc_hostname(mmc));
3349                         mmc->max_blk_size = 0;
3350                 }
3351         }
3352
3353         mmc->max_blk_size = 512 << mmc->max_blk_size;
3354
3355         /*
3356          * Maximum block count.
3357          */
3358         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3359
3360         /*
3361          * Init tasklets.
3362          */
3363         tasklet_init(&host->finish_tasklet,
3364                 sdhci_tasklet_finish, (unsigned long)host);
3365
3366         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3367
3368         init_waitqueue_head(&host->buf_ready_int);
3369
3370         sdhci_init(host, 0);
3371
3372         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3373                                    IRQF_SHARED, mmc_hostname(mmc), host);
3374         if (ret) {
3375                 pr_err("%s: Failed to request IRQ %d: %d\n",
3376                        mmc_hostname(mmc), host->irq, ret);
3377                 goto untasklet;
3378         }
3379
3380 #ifdef CONFIG_MMC_DEBUG
3381         sdhci_dumpregs(host);
3382 #endif
3383
3384 #ifdef SDHCI_USE_LEDS_CLASS
3385         snprintf(host->led_name, sizeof(host->led_name),
3386                 "%s::", mmc_hostname(mmc));
3387         host->led.name = host->led_name;
3388         host->led.brightness = LED_OFF;
3389         host->led.default_trigger = mmc_hostname(mmc);
3390         host->led.brightness_set = sdhci_led_control;
3391
3392         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3393         if (ret) {
3394                 pr_err("%s: Failed to register LED device: %d\n",
3395                        mmc_hostname(mmc), ret);
3396                 goto reset;
3397         }
3398 #endif
3399
3400         mmiowb();
3401
3402         mmc_add_host(mmc);
3403
3404         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3405                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3406                 (host->flags & SDHCI_USE_ADMA) ?
3407                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3408                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3409
3410         sdhci_enable_card_detection(host);
3411
3412         return 0;
3413
3414 #ifdef SDHCI_USE_LEDS_CLASS
3415 reset:
3416         sdhci_do_reset(host, SDHCI_RESET_ALL);
3417         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3418         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3419         free_irq(host->irq, host);
3420 #endif
3421 untasklet:
3422         tasklet_kill(&host->finish_tasklet);
3423
3424         return ret;
3425 }
3426
3427 EXPORT_SYMBOL_GPL(sdhci_add_host);
3428
3429 void sdhci_remove_host(struct sdhci_host *host, int dead)
3430 {
3431         struct mmc_host *mmc = host->mmc;
3432         unsigned long flags;
3433
3434         if (dead) {
3435                 spin_lock_irqsave(&host->lock, flags);
3436
3437                 host->flags |= SDHCI_DEVICE_DEAD;
3438
3439                 if (host->mrq) {
3440                         pr_err("%s: Controller removed during "
3441                                 " transfer!\n", mmc_hostname(mmc));
3442
3443                         host->mrq->cmd->error = -ENOMEDIUM;
3444                         tasklet_schedule(&host->finish_tasklet);
3445                 }
3446
3447                 spin_unlock_irqrestore(&host->lock, flags);
3448         }
3449
3450         sdhci_disable_card_detection(host);
3451
3452         mmc_remove_host(mmc);
3453
3454 #ifdef SDHCI_USE_LEDS_CLASS
3455         led_classdev_unregister(&host->led);
3456 #endif
3457
3458         if (!dead)
3459                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3460
3461         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3462         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3463         free_irq(host->irq, host);
3464
3465         del_timer_sync(&host->timer);
3466
3467         tasklet_kill(&host->finish_tasklet);
3468
3469         if (!IS_ERR(mmc->supply.vqmmc))
3470                 regulator_disable(mmc->supply.vqmmc);
3471
3472         if (host->adma_table)
3473                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3474                                   host->adma_table, host->adma_addr);
3475         kfree(host->align_buffer);
3476
3477         host->adma_table = NULL;
3478         host->align_buffer = NULL;
3479 }
3480
3481 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3482
3483 void sdhci_free_host(struct sdhci_host *host)
3484 {
3485         mmc_free_host(host->mmc);
3486 }
3487
3488 EXPORT_SYMBOL_GPL(sdhci_free_host);
3489
3490 /*****************************************************************************\
3491  *                                                                           *
3492  * Driver init/exit                                                          *
3493  *                                                                           *
3494 \*****************************************************************************/
3495
3496 static int __init sdhci_drv_init(void)
3497 {
3498         pr_info(DRIVER_NAME
3499                 ": Secure Digital Host Controller Interface driver\n");
3500         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3501
3502         return 0;
3503 }
3504
3505 static void __exit sdhci_drv_exit(void)
3506 {
3507 }
3508
3509 module_init(sdhci_drv_init);
3510 module_exit(sdhci_drv_exit);
3511
3512 module_param(debug_quirks, uint, 0444);
3513 module_param(debug_quirks2, uint, 0444);
3514
3515 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3516 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3517 MODULE_LICENSE("GPL");
3518
3519 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3520 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");