2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
50 static void sdhci_finish_data(struct sdhci_host *);
52 static void sdhci_finish_command(struct sdhci_host *);
53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54 static void sdhci_tuning_timer(unsigned long data);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57 #ifdef CONFIG_PM_RUNTIME
58 static int sdhci_runtime_pm_get(struct sdhci_host *host);
59 static int sdhci_runtime_pm_put(struct sdhci_host *host);
60 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
63 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79 static void sdhci_dumpregs(struct sdhci_host *host)
81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
82 mmc_hostname(host->mmc));
84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
112 sdhci_readl(host, SDHCI_CAPABILITIES),
113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
115 sdhci_readw(host, SDHCI_COMMAND),
116 sdhci_readl(host, SDHCI_MAX_CURRENT));
117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
120 if (host->flags & SDHCI_USE_ADMA)
121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
125 pr_debug(DRIVER_NAME ": ===========================================\n");
128 /*****************************************************************************\
130 * Low level functions *
132 \*****************************************************************************/
134 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
138 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
141 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
142 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
145 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
147 sdhci_clear_set_irqs(host, 0, irqs);
150 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
152 sdhci_clear_set_irqs(host, irqs, 0);
155 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
160 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
165 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
168 sdhci_unmask_irqs(host, irqs);
170 sdhci_mask_irqs(host, irqs);
173 static void sdhci_enable_card_detection(struct sdhci_host *host)
175 sdhci_set_card_detection(host, true);
178 static void sdhci_disable_card_detection(struct sdhci_host *host)
180 sdhci_set_card_detection(host, false);
183 static void sdhci_reset(struct sdhci_host *host, u8 mask)
185 unsigned long timeout;
186 u32 uninitialized_var(ier);
188 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
189 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
194 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
195 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
197 if (host->ops->platform_reset_enter)
198 host->ops->platform_reset_enter(host, mask);
200 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
202 if (mask & SDHCI_RESET_ALL) {
204 /* Reset-all turns off SD Bus Power */
205 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
206 sdhci_runtime_pm_bus_off(host);
209 /* Wait max 100 ms */
212 /* hw clears the bit when it's done */
213 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
215 pr_err("%s: Reset 0x%x never completed.\n",
216 mmc_hostname(host->mmc), (int)mask);
217 sdhci_dumpregs(host);
224 if (host->ops->platform_reset_exit)
225 host->ops->platform_reset_exit(host, mask);
227 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
228 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
230 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
231 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
232 host->ops->enable_dma(host);
236 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
238 static void sdhci_init(struct sdhci_host *host, int soft)
241 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
243 sdhci_reset(host, SDHCI_RESET_ALL);
245 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
246 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
247 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
248 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
249 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
252 /* force clock reconfiguration */
254 sdhci_set_ios(host->mmc, &host->mmc->ios);
258 static void sdhci_reinit(struct sdhci_host *host)
262 * Retuning stuffs are affected by different cards inserted and only
263 * applicable to UHS-I cards. So reset these fields to their initial
264 * value when card is removed.
266 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
267 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
269 del_timer_sync(&host->tuning_timer);
270 host->flags &= ~SDHCI_NEEDS_RETUNING;
271 host->mmc->max_blk_count =
272 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
274 sdhci_enable_card_detection(host);
277 static void sdhci_activate_led(struct sdhci_host *host)
281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
282 ctrl |= SDHCI_CTRL_LED;
283 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
286 static void sdhci_deactivate_led(struct sdhci_host *host)
290 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
291 ctrl &= ~SDHCI_CTRL_LED;
292 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
295 #ifdef SDHCI_USE_LEDS_CLASS
296 static void sdhci_led_control(struct led_classdev *led,
297 enum led_brightness brightness)
299 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
302 spin_lock_irqsave(&host->lock, flags);
304 if (host->runtime_suspended)
307 if (brightness == LED_OFF)
308 sdhci_deactivate_led(host);
310 sdhci_activate_led(host);
312 spin_unlock_irqrestore(&host->lock, flags);
316 /*****************************************************************************\
320 \*****************************************************************************/
322 static void sdhci_read_block_pio(struct sdhci_host *host)
325 size_t blksize, len, chunk;
326 u32 uninitialized_var(scratch);
329 DBG("PIO reading\n");
331 blksize = host->data->blksz;
334 local_irq_save(flags);
337 if (!sg_miter_next(&host->sg_miter))
340 len = min(host->sg_miter.length, blksize);
343 host->sg_miter.consumed = len;
345 buf = host->sg_miter.addr;
349 scratch = sdhci_readl(host, SDHCI_BUFFER);
353 *buf = scratch & 0xFF;
362 sg_miter_stop(&host->sg_miter);
364 local_irq_restore(flags);
367 static void sdhci_write_block_pio(struct sdhci_host *host)
370 size_t blksize, len, chunk;
374 DBG("PIO writing\n");
376 blksize = host->data->blksz;
380 local_irq_save(flags);
383 if (!sg_miter_next(&host->sg_miter))
386 len = min(host->sg_miter.length, blksize);
389 host->sg_miter.consumed = len;
391 buf = host->sg_miter.addr;
394 scratch |= (u32)*buf << (chunk * 8);
400 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
401 sdhci_writel(host, scratch, SDHCI_BUFFER);
408 sg_miter_stop(&host->sg_miter);
410 local_irq_restore(flags);
413 static void sdhci_transfer_pio(struct sdhci_host *host)
419 if (host->blocks == 0)
422 if (host->data->flags & MMC_DATA_READ)
423 mask = SDHCI_DATA_AVAILABLE;
425 mask = SDHCI_SPACE_AVAILABLE;
428 * Some controllers (JMicron JMB38x) mess up the buffer bits
429 * for transfers < 4 bytes. As long as it is just one block,
430 * we can ignore the bits.
432 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
433 (host->data->blocks == 1))
436 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
437 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
440 if (host->data->flags & MMC_DATA_READ)
441 sdhci_read_block_pio(host);
443 sdhci_write_block_pio(host);
446 if (host->blocks == 0)
450 DBG("PIO transfer complete.\n");
453 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455 local_irq_save(*flags);
456 return kmap_atomic(sg_page(sg)) + sg->offset;
459 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461 kunmap_atomic(buffer);
462 local_irq_restore(*flags);
465 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
467 __le32 *dataddr = (__le32 __force *)(desc + 4);
468 __le16 *cmdlen = (__le16 __force *)desc;
470 /* SDHCI specification says ADMA descriptors should be 4 byte
471 * aligned, so using 16 or 32bit operations should be safe. */
473 cmdlen[0] = cpu_to_le16(cmd);
474 cmdlen[1] = cpu_to_le16(len);
476 dataddr[0] = cpu_to_le32(addr);
479 static int sdhci_adma_table_pre(struct sdhci_host *host,
480 struct mmc_data *data)
487 dma_addr_t align_addr;
490 struct scatterlist *sg;
496 * The spec does not specify endianness of descriptor table.
497 * We currently guess that it is LE.
500 if (data->flags & MMC_DATA_READ)
501 direction = DMA_FROM_DEVICE;
503 direction = DMA_TO_DEVICE;
506 * The ADMA descriptor table is mapped further down as we
507 * need to fill it with data first.
510 host->align_addr = dma_map_single(mmc_dev(host->mmc),
511 host->align_buffer, 128 * 4, direction);
512 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
514 BUG_ON(host->align_addr & 0x3);
516 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
517 data->sg, data->sg_len, direction);
518 if (host->sg_count == 0)
521 desc = host->adma_desc;
522 align = host->align_buffer;
524 align_addr = host->align_addr;
526 for_each_sg(data->sg, sg, host->sg_count, i) {
527 addr = sg_dma_address(sg);
528 len = sg_dma_len(sg);
531 * The SDHCI specification states that ADMA
532 * addresses must be 32-bit aligned. If they
533 * aren't, then we use a bounce buffer for
534 * the (up to three) bytes that screw up the
537 offset = (4 - (addr & 0x3)) & 0x3;
539 if (data->flags & MMC_DATA_WRITE) {
540 buffer = sdhci_kmap_atomic(sg, &flags);
541 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
542 memcpy(align, buffer, offset);
543 sdhci_kunmap_atomic(buffer, &flags);
547 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
549 BUG_ON(offset > 65536);
563 sdhci_set_adma_desc(desc, addr, len, 0x21);
567 * If this triggers then we have a calculation bug
570 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
573 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
575 * Mark the last descriptor as the terminating descriptor
577 if (desc != host->adma_desc) {
579 desc[0] |= 0x2; /* end */
583 * Add a terminating entry.
586 /* nop, end, valid */
587 sdhci_set_adma_desc(desc, 0, 0, 0x3);
591 * Resync align buffer as we might have changed it.
593 if (data->flags & MMC_DATA_WRITE) {
594 dma_sync_single_for_device(mmc_dev(host->mmc),
595 host->align_addr, 128 * 4, direction);
598 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
599 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
600 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
602 BUG_ON(host->adma_addr & 0x3);
607 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
608 data->sg_len, direction);
610 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
616 static void sdhci_adma_table_post(struct sdhci_host *host,
617 struct mmc_data *data)
621 struct scatterlist *sg;
627 if (data->flags & MMC_DATA_READ)
628 direction = DMA_FROM_DEVICE;
630 direction = DMA_TO_DEVICE;
632 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
633 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
635 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
638 if (data->flags & MMC_DATA_READ) {
639 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
640 data->sg_len, direction);
642 align = host->align_buffer;
644 for_each_sg(data->sg, sg, host->sg_count, i) {
645 if (sg_dma_address(sg) & 0x3) {
646 size = 4 - (sg_dma_address(sg) & 0x3);
648 buffer = sdhci_kmap_atomic(sg, &flags);
649 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
650 memcpy(buffer, align, size);
651 sdhci_kunmap_atomic(buffer, &flags);
658 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
659 data->sg_len, direction);
662 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
665 struct mmc_data *data = cmd->data;
666 unsigned target_timeout, current_timeout;
669 * If the host controller provides us with an incorrect timeout
670 * value, just skip the check and use 0xE. The hardware may take
671 * longer to time out, but that's much better than having a too-short
674 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
677 /* Unspecified timeout, assume max */
678 if (!data && !cmd->cmd_timeout_ms)
683 target_timeout = cmd->cmd_timeout_ms * 1000;
685 target_timeout = data->timeout_ns / 1000;
687 target_timeout += data->timeout_clks / host->clock;
691 * Figure out needed cycles.
692 * We do this in steps in order to fit inside a 32 bit int.
693 * The first step is the minimum timeout, which will have a
694 * minimum resolution of 6 bits:
695 * (1) 2^13*1000 > 2^22,
696 * (2) host->timeout_clk < 2^16
701 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
702 while (current_timeout < target_timeout) {
704 current_timeout <<= 1;
710 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
711 mmc_hostname(host->mmc), count, cmd->opcode);
718 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
720 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
721 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
723 if (host->flags & SDHCI_REQ_USE_DMA)
724 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
726 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
729 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
733 struct mmc_data *data = cmd->data;
738 if (data || (cmd->flags & MMC_RSP_BUSY)) {
739 count = sdhci_calc_timeout(host, cmd);
740 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
747 BUG_ON(data->blksz * data->blocks > 524288);
748 BUG_ON(data->blksz > host->mmc->max_blk_size);
749 BUG_ON(data->blocks > 65535);
752 host->data_early = 0;
753 host->data->bytes_xfered = 0;
755 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
756 host->flags |= SDHCI_REQ_USE_DMA;
759 * FIXME: This doesn't account for merging when mapping the
762 if (host->flags & SDHCI_REQ_USE_DMA) {
764 struct scatterlist *sg;
767 if (host->flags & SDHCI_USE_ADMA) {
768 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
771 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
775 if (unlikely(broken)) {
776 for_each_sg(data->sg, sg, data->sg_len, i) {
777 if (sg->length & 0x3) {
778 DBG("Reverting to PIO because of "
779 "transfer size (%d)\n",
781 host->flags &= ~SDHCI_REQ_USE_DMA;
789 * The assumption here being that alignment is the same after
790 * translation to device address space.
792 if (host->flags & SDHCI_REQ_USE_DMA) {
794 struct scatterlist *sg;
797 if (host->flags & SDHCI_USE_ADMA) {
799 * As we use 3 byte chunks to work around
800 * alignment problems, we need to check this
803 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
806 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
810 if (unlikely(broken)) {
811 for_each_sg(data->sg, sg, data->sg_len, i) {
812 if (sg->offset & 0x3) {
813 DBG("Reverting to PIO because of "
815 host->flags &= ~SDHCI_REQ_USE_DMA;
822 if (host->flags & SDHCI_REQ_USE_DMA) {
823 if (host->flags & SDHCI_USE_ADMA) {
824 ret = sdhci_adma_table_pre(host, data);
827 * This only happens when someone fed
828 * us an invalid request.
831 host->flags &= ~SDHCI_REQ_USE_DMA;
833 sdhci_writel(host, host->adma_addr,
839 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
840 data->sg, data->sg_len,
841 (data->flags & MMC_DATA_READ) ?
846 * This only happens when someone fed
847 * us an invalid request.
850 host->flags &= ~SDHCI_REQ_USE_DMA;
852 WARN_ON(sg_cnt != 1);
853 sdhci_writel(host, sg_dma_address(data->sg),
860 * Always adjust the DMA selection as some controllers
861 * (e.g. JMicron) can't do PIO properly when the selection
864 if (host->version >= SDHCI_SPEC_200) {
865 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
866 ctrl &= ~SDHCI_CTRL_DMA_MASK;
867 if ((host->flags & SDHCI_REQ_USE_DMA) &&
868 (host->flags & SDHCI_USE_ADMA))
869 ctrl |= SDHCI_CTRL_ADMA32;
871 ctrl |= SDHCI_CTRL_SDMA;
872 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
875 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
878 flags = SG_MITER_ATOMIC;
879 if (host->data->flags & MMC_DATA_READ)
880 flags |= SG_MITER_TO_SG;
882 flags |= SG_MITER_FROM_SG;
883 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
884 host->blocks = data->blocks;
887 sdhci_set_transfer_irqs(host);
889 /* Set the DMA boundary value and block size */
890 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
891 data->blksz), SDHCI_BLOCK_SIZE);
892 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
895 static void sdhci_set_transfer_mode(struct sdhci_host *host,
896 struct mmc_command *cmd)
899 struct mmc_data *data = cmd->data;
902 /* clear Auto CMD settings for no data CMDs */
903 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
904 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
905 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
909 WARN_ON(!host->data);
911 mode = SDHCI_TRNS_BLK_CNT_EN;
912 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
913 mode |= SDHCI_TRNS_MULTI;
915 * If we are sending CMD23, CMD12 never gets sent
916 * on successful completion (so no Auto-CMD12).
918 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
919 mode |= SDHCI_TRNS_AUTO_CMD12;
920 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
921 mode |= SDHCI_TRNS_AUTO_CMD23;
922 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
926 if (data->flags & MMC_DATA_READ)
927 mode |= SDHCI_TRNS_READ;
928 if (host->flags & SDHCI_REQ_USE_DMA)
929 mode |= SDHCI_TRNS_DMA;
931 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
934 static void sdhci_finish_data(struct sdhci_host *host)
936 struct mmc_data *data;
943 if (host->flags & SDHCI_REQ_USE_DMA) {
944 if (host->flags & SDHCI_USE_ADMA)
945 sdhci_adma_table_post(host, data);
947 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
948 data->sg_len, (data->flags & MMC_DATA_READ) ?
949 DMA_FROM_DEVICE : DMA_TO_DEVICE);
954 * The specification states that the block count register must
955 * be updated, but it does not specify at what point in the
956 * data flow. That makes the register entirely useless to read
957 * back so we have to assume that nothing made it to the card
958 * in the event of an error.
961 data->bytes_xfered = 0;
963 data->bytes_xfered = data->blksz * data->blocks;
966 * Need to send CMD12 if -
967 * a) open-ended multiblock transfer (no CMD23)
968 * b) error in multiblock transfer
975 * The controller needs a reset of internal state machines
976 * upon error conditions.
979 sdhci_reset(host, SDHCI_RESET_CMD);
980 sdhci_reset(host, SDHCI_RESET_DATA);
983 sdhci_send_command(host, data->stop);
985 tasklet_schedule(&host->finish_tasklet);
988 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
992 unsigned long timeout;
999 mask = SDHCI_CMD_INHIBIT;
1000 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1001 mask |= SDHCI_DATA_INHIBIT;
1003 /* We shouldn't wait for data inihibit for stop commands, even
1004 though they might use busy signaling */
1005 if (host->mrq->data && (cmd == host->mrq->data->stop))
1006 mask &= ~SDHCI_DATA_INHIBIT;
1008 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1010 pr_err("%s: Controller never released "
1011 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1012 sdhci_dumpregs(host);
1014 tasklet_schedule(&host->finish_tasklet);
1021 mod_timer(&host->timer, jiffies + 10 * HZ);
1025 sdhci_prepare_data(host, cmd);
1027 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1029 sdhci_set_transfer_mode(host, cmd);
1031 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1032 pr_err("%s: Unsupported response type!\n",
1033 mmc_hostname(host->mmc));
1034 cmd->error = -EINVAL;
1035 tasklet_schedule(&host->finish_tasklet);
1039 if (!(cmd->flags & MMC_RSP_PRESENT))
1040 flags = SDHCI_CMD_RESP_NONE;
1041 else if (cmd->flags & MMC_RSP_136)
1042 flags = SDHCI_CMD_RESP_LONG;
1043 else if (cmd->flags & MMC_RSP_BUSY)
1044 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1046 flags = SDHCI_CMD_RESP_SHORT;
1048 if (cmd->flags & MMC_RSP_CRC)
1049 flags |= SDHCI_CMD_CRC;
1050 if (cmd->flags & MMC_RSP_OPCODE)
1051 flags |= SDHCI_CMD_INDEX;
1053 /* CMD19 is special in that the Data Present Select should be set */
1054 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1055 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1056 flags |= SDHCI_CMD_DATA;
1058 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1060 EXPORT_SYMBOL_GPL(sdhci_send_command);
1062 static void sdhci_finish_command(struct sdhci_host *host)
1066 BUG_ON(host->cmd == NULL);
1068 if (host->cmd->flags & MMC_RSP_PRESENT) {
1069 if (host->cmd->flags & MMC_RSP_136) {
1070 /* CRC is stripped so we need to do some shifting. */
1071 for (i = 0;i < 4;i++) {
1072 host->cmd->resp[i] = sdhci_readl(host,
1073 SDHCI_RESPONSE + (3-i)*4) << 8;
1075 host->cmd->resp[i] |=
1077 SDHCI_RESPONSE + (3-i)*4-1);
1080 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1084 host->cmd->error = 0;
1086 /* Finished CMD23, now send actual command. */
1087 if (host->cmd == host->mrq->sbc) {
1089 sdhci_send_command(host, host->mrq->cmd);
1092 /* Processed actual command. */
1093 if (host->data && host->data_early)
1094 sdhci_finish_data(host);
1096 if (!host->cmd->data)
1097 tasklet_schedule(&host->finish_tasklet);
1103 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1105 u16 ctrl, preset = 0;
1107 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1109 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1110 case SDHCI_CTRL_UHS_SDR12:
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1113 case SDHCI_CTRL_UHS_SDR25:
1114 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1116 case SDHCI_CTRL_UHS_SDR50:
1117 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1119 case SDHCI_CTRL_UHS_SDR104:
1120 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1122 case SDHCI_CTRL_UHS_DDR50:
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1126 pr_warn("%s: Invalid UHS-I mode selected\n",
1127 mmc_hostname(host->mmc));
1128 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1134 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1136 int div = 0; /* Initialized for compiler warning */
1137 int real_div = div, clk_mul = 1;
1139 unsigned long timeout;
1141 if (clock && clock == host->clock)
1144 host->mmc->actual_clock = 0;
1146 if (host->ops->set_clock) {
1147 host->ops->set_clock(host, clock);
1148 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1152 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1157 if (host->version >= SDHCI_SPEC_300) {
1158 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1159 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1162 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1163 pre_val = sdhci_get_preset_value(host);
1164 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1165 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1166 if (host->clk_mul &&
1167 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1168 clk = SDHCI_PROG_CLOCK_MODE;
1170 clk_mul = host->clk_mul;
1172 real_div = max_t(int, 1, div << 1);
1178 * Check if the Host Controller supports Programmable Clock
1181 if (host->clk_mul) {
1182 for (div = 1; div <= 1024; div++) {
1183 if ((host->max_clk * host->clk_mul / div)
1188 * Set Programmable Clock Mode in the Clock
1191 clk = SDHCI_PROG_CLOCK_MODE;
1193 clk_mul = host->clk_mul;
1196 /* Version 3.00 divisors must be a multiple of 2. */
1197 if (host->max_clk <= clock)
1200 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1202 if ((host->max_clk / div) <= clock)
1210 /* Version 2.00 divisors must be a power of 2. */
1211 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1212 if ((host->max_clk / div) <= clock)
1221 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1223 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1224 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1225 << SDHCI_DIVIDER_HI_SHIFT;
1226 clk |= SDHCI_CLOCK_INT_EN;
1227 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1229 /* Wait max 20 ms */
1231 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1232 & SDHCI_CLOCK_INT_STABLE)) {
1234 pr_err("%s: Internal clock never "
1235 "stabilised.\n", mmc_hostname(host->mmc));
1236 sdhci_dumpregs(host);
1243 clk |= SDHCI_CLOCK_CARD_EN;
1244 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1247 host->clock = clock;
1250 static inline void sdhci_update_clock(struct sdhci_host *host)
1254 clock = host->clock;
1256 sdhci_set_clock(host, clock);
1259 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1263 if (power != (unsigned short)-1) {
1264 switch (1 << power) {
1265 case MMC_VDD_165_195:
1266 pwr = SDHCI_POWER_180;
1270 pwr = SDHCI_POWER_300;
1274 pwr = SDHCI_POWER_330;
1281 if (host->pwr == pwr)
1287 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1288 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1289 sdhci_runtime_pm_bus_off(host);
1294 * Spec says that we should clear the power reg before setting
1295 * a new value. Some controllers don't seem to like this though.
1297 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1298 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1301 * At least the Marvell CaFe chip gets confused if we set the voltage
1302 * and set turn on power at the same time, so set the voltage first.
1304 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1305 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1307 pwr |= SDHCI_POWER_ON;
1309 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1311 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1312 sdhci_runtime_pm_bus_on(host);
1315 * Some controllers need an extra 10ms delay of 10ms before they
1316 * can apply clock after applying power
1318 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1324 /*****************************************************************************\
1328 \*****************************************************************************/
1330 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1332 struct sdhci_host *host;
1334 unsigned long flags;
1337 host = mmc_priv(mmc);
1339 sdhci_runtime_pm_get(host);
1341 spin_lock_irqsave(&host->lock, flags);
1343 WARN_ON(host->mrq != NULL);
1345 #ifndef SDHCI_USE_LEDS_CLASS
1346 sdhci_activate_led(host);
1350 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1351 * requests if Auto-CMD12 is enabled.
1353 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1355 mrq->data->stop = NULL;
1363 * Firstly check card presence from cd-gpio. The return could
1364 * be one of the following possibilities:
1365 * negative: cd-gpio is not available
1366 * zero: cd-gpio is used, and card is removed
1367 * one: cd-gpio is used, and card is present
1369 present = mmc_gpio_get_cd(host->mmc);
1371 /* If polling, assume that the card is always present. */
1372 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1375 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1379 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1380 host->mrq->cmd->error = -ENOMEDIUM;
1381 tasklet_schedule(&host->finish_tasklet);
1385 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1387 * Check if the re-tuning timer has already expired and there
1388 * is no on-going data transfer. If so, we need to execute
1389 * tuning procedure before sending command.
1391 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1392 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1394 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1396 mmc->card->type == MMC_TYPE_MMC ?
1397 MMC_SEND_TUNING_BLOCK_HS200 :
1398 MMC_SEND_TUNING_BLOCK;
1400 /* Here we need to set the host->mrq to NULL,
1401 * in case the pending finish_tasklet
1402 * finishes it incorrectly.
1406 spin_unlock_irqrestore(&host->lock, flags);
1407 sdhci_execute_tuning(mmc, tuning_opcode);
1408 spin_lock_irqsave(&host->lock, flags);
1410 /* Restore original mmc_request structure */
1415 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1416 sdhci_send_command(host, mrq->sbc);
1418 sdhci_send_command(host, mrq->cmd);
1422 spin_unlock_irqrestore(&host->lock, flags);
1425 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1427 unsigned long flags;
1431 spin_lock_irqsave(&host->lock, flags);
1433 if (host->flags & SDHCI_DEVICE_DEAD) {
1434 spin_unlock_irqrestore(&host->lock, flags);
1435 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1436 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1441 * Reset the chip on each power off.
1442 * Should clear out any weird states.
1444 if (ios->power_mode == MMC_POWER_OFF) {
1445 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1449 if (host->version >= SDHCI_SPEC_300 &&
1450 (ios->power_mode == MMC_POWER_UP) &&
1451 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1452 sdhci_enable_preset_value(host, false);
1454 sdhci_set_clock(host, ios->clock);
1456 if (ios->power_mode == MMC_POWER_OFF)
1457 vdd_bit = sdhci_set_power(host, -1);
1459 vdd_bit = sdhci_set_power(host, ios->vdd);
1461 if (host->vmmc && vdd_bit != -1) {
1462 spin_unlock_irqrestore(&host->lock, flags);
1463 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1464 spin_lock_irqsave(&host->lock, flags);
1467 if (host->ops->platform_send_init_74_clocks)
1468 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1471 * If your platform has 8-bit width support but is not a v3 controller,
1472 * or if it requires special setup code, you should implement that in
1473 * platform_bus_width().
1475 if (host->ops->platform_bus_width) {
1476 host->ops->platform_bus_width(host, ios->bus_width);
1478 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1479 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1480 ctrl &= ~SDHCI_CTRL_4BITBUS;
1481 if (host->version >= SDHCI_SPEC_300)
1482 ctrl |= SDHCI_CTRL_8BITBUS;
1484 if (host->version >= SDHCI_SPEC_300)
1485 ctrl &= ~SDHCI_CTRL_8BITBUS;
1486 if (ios->bus_width == MMC_BUS_WIDTH_4)
1487 ctrl |= SDHCI_CTRL_4BITBUS;
1489 ctrl &= ~SDHCI_CTRL_4BITBUS;
1491 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1494 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1496 if ((ios->timing == MMC_TIMING_SD_HS ||
1497 ios->timing == MMC_TIMING_MMC_HS)
1498 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1499 ctrl |= SDHCI_CTRL_HISPD;
1501 ctrl &= ~SDHCI_CTRL_HISPD;
1503 if (host->version >= SDHCI_SPEC_300) {
1506 /* In case of UHS-I modes, set High Speed Enable */
1507 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1508 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1509 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1510 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1511 (ios->timing == MMC_TIMING_UHS_SDR25))
1512 ctrl |= SDHCI_CTRL_HISPD;
1514 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1515 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1516 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1518 * We only need to set Driver Strength if the
1519 * preset value enable is not set.
1521 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1522 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1523 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1524 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1525 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1527 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1530 * According to SDHC Spec v3.00, if the Preset Value
1531 * Enable in the Host Control 2 register is set, we
1532 * need to reset SD Clock Enable before changing High
1533 * Speed Enable to avoid generating clock gliches.
1536 /* Reset SD Clock Enable */
1537 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1538 clk &= ~SDHCI_CLOCK_CARD_EN;
1539 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1541 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1543 /* Re-enable SD Clock */
1544 sdhci_update_clock(host);
1548 /* Reset SD Clock Enable */
1549 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1550 clk &= ~SDHCI_CLOCK_CARD_EN;
1551 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1553 if (host->ops->set_uhs_signaling)
1554 host->ops->set_uhs_signaling(host, ios->timing);
1556 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1557 /* Select Bus Speed Mode for host */
1558 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1559 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1560 (ios->timing == MMC_TIMING_UHS_SDR104))
1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1562 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1564 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1565 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1566 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1567 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1568 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1569 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1570 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1573 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1574 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1575 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1576 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1577 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1578 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1581 sdhci_enable_preset_value(host, true);
1582 preset = sdhci_get_preset_value(host);
1583 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1584 >> SDHCI_PRESET_DRV_SHIFT;
1587 /* Re-enable SD Clock */
1588 sdhci_update_clock(host);
1590 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1593 * Some (ENE) controllers go apeshit on some ios operation,
1594 * signalling timeout and CRC errors even on CMD0. Resetting
1595 * it on each ios seems to solve the problem.
1597 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1598 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1601 spin_unlock_irqrestore(&host->lock, flags);
1604 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1606 struct sdhci_host *host = mmc_priv(mmc);
1608 sdhci_runtime_pm_get(host);
1609 sdhci_do_set_ios(host, ios);
1610 sdhci_runtime_pm_put(host);
1613 static int sdhci_do_get_cd(struct sdhci_host *host)
1615 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1617 if (host->flags & SDHCI_DEVICE_DEAD)
1620 /* If polling/nonremovable, assume that the card is always present. */
1621 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1622 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1625 /* Try slot gpio detect */
1626 if (!IS_ERR_VALUE(gpio_cd))
1629 /* Host native card detect */
1630 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1633 static int sdhci_get_cd(struct mmc_host *mmc)
1635 struct sdhci_host *host = mmc_priv(mmc);
1638 sdhci_runtime_pm_get(host);
1639 ret = sdhci_do_get_cd(host);
1640 sdhci_runtime_pm_put(host);
1644 static int sdhci_check_ro(struct sdhci_host *host)
1646 unsigned long flags;
1649 spin_lock_irqsave(&host->lock, flags);
1651 if (host->flags & SDHCI_DEVICE_DEAD)
1653 else if (host->ops->get_ro)
1654 is_readonly = host->ops->get_ro(host);
1656 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1657 & SDHCI_WRITE_PROTECT);
1659 spin_unlock_irqrestore(&host->lock, flags);
1661 /* This quirk needs to be replaced by a callback-function later */
1662 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1663 !is_readonly : is_readonly;
1666 #define SAMPLE_COUNT 5
1668 static int sdhci_do_get_ro(struct sdhci_host *host)
1672 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1673 return sdhci_check_ro(host);
1676 for (i = 0; i < SAMPLE_COUNT; i++) {
1677 if (sdhci_check_ro(host)) {
1678 if (++ro_count > SAMPLE_COUNT / 2)
1686 static void sdhci_hw_reset(struct mmc_host *mmc)
1688 struct sdhci_host *host = mmc_priv(mmc);
1690 if (host->ops && host->ops->hw_reset)
1691 host->ops->hw_reset(host);
1694 static int sdhci_get_ro(struct mmc_host *mmc)
1696 struct sdhci_host *host = mmc_priv(mmc);
1699 sdhci_runtime_pm_get(host);
1700 ret = sdhci_do_get_ro(host);
1701 sdhci_runtime_pm_put(host);
1705 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1707 if (host->flags & SDHCI_DEVICE_DEAD)
1711 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1713 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1715 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1716 if (host->runtime_suspended)
1720 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1722 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1727 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1729 struct sdhci_host *host = mmc_priv(mmc);
1730 unsigned long flags;
1732 spin_lock_irqsave(&host->lock, flags);
1733 sdhci_enable_sdio_irq_nolock(host, enable);
1734 spin_unlock_irqrestore(&host->lock, flags);
1737 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1738 struct mmc_ios *ios)
1744 * Signal Voltage Switching is only applicable for Host Controllers
1747 if (host->version < SDHCI_SPEC_300)
1750 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1752 switch (ios->signal_voltage) {
1753 case MMC_SIGNAL_VOLTAGE_330:
1754 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1755 ctrl &= ~SDHCI_CTRL_VDD_180;
1756 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1759 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1761 pr_warning("%s: Switching to 3.3V signalling voltage "
1762 " failed\n", mmc_hostname(host->mmc));
1767 usleep_range(5000, 5500);
1769 /* 3.3V regulator output should be stable within 5 ms */
1770 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1771 if (!(ctrl & SDHCI_CTRL_VDD_180))
1774 pr_warning("%s: 3.3V regulator output did not became stable\n",
1775 mmc_hostname(host->mmc));
1778 case MMC_SIGNAL_VOLTAGE_180:
1780 ret = regulator_set_voltage(host->vqmmc,
1783 pr_warning("%s: Switching to 1.8V signalling voltage "
1784 " failed\n", mmc_hostname(host->mmc));
1790 * Enable 1.8V Signal Enable in the Host Control2
1793 ctrl |= SDHCI_CTRL_VDD_180;
1794 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1797 usleep_range(5000, 5500);
1799 /* 1.8V regulator output should be stable within 5 ms */
1800 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1801 if (ctrl & SDHCI_CTRL_VDD_180)
1804 pr_warning("%s: 1.8V regulator output did not became stable\n",
1805 mmc_hostname(host->mmc));
1808 case MMC_SIGNAL_VOLTAGE_120:
1810 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1812 pr_warning("%s: Switching to 1.2V signalling voltage "
1813 " failed\n", mmc_hostname(host->mmc));
1819 /* No signal voltage switch required */
1824 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1825 struct mmc_ios *ios)
1827 struct sdhci_host *host = mmc_priv(mmc);
1830 if (host->version < SDHCI_SPEC_300)
1832 sdhci_runtime_pm_get(host);
1833 err = sdhci_do_start_signal_voltage_switch(host, ios);
1834 sdhci_runtime_pm_put(host);
1838 static int sdhci_card_busy(struct mmc_host *mmc)
1840 struct sdhci_host *host = mmc_priv(mmc);
1843 sdhci_runtime_pm_get(host);
1844 /* Check whether DAT[3:0] is 0000 */
1845 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1846 sdhci_runtime_pm_put(host);
1848 return !(present_state & SDHCI_DATA_LVL_MASK);
1851 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1853 struct sdhci_host *host;
1856 int tuning_loop_counter = MAX_TUNING_LOOP;
1857 unsigned long timeout;
1859 bool requires_tuning_nonuhs = false;
1861 host = mmc_priv(mmc);
1863 sdhci_runtime_pm_get(host);
1864 disable_irq(host->irq);
1865 spin_lock(&host->lock);
1867 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1870 * The Host Controller needs tuning only in case of SDR104 mode
1871 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1872 * Capabilities register.
1873 * If the Host Controller supports the HS200 mode then the
1874 * tuning function has to be executed.
1876 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1877 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1878 host->flags & SDHCI_SDR104_NEEDS_TUNING))
1879 requires_tuning_nonuhs = true;
1881 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1882 requires_tuning_nonuhs)
1883 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1885 spin_unlock(&host->lock);
1886 enable_irq(host->irq);
1887 sdhci_runtime_pm_put(host);
1891 if (host->ops->platform_execute_tuning) {
1892 spin_unlock(&host->lock);
1893 enable_irq(host->irq);
1894 err = host->ops->platform_execute_tuning(host, opcode);
1895 sdhci_runtime_pm_put(host);
1899 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1902 * As per the Host Controller spec v3.00, tuning command
1903 * generates Buffer Read Ready interrupt, so enable that.
1905 * Note: The spec clearly says that when tuning sequence
1906 * is being performed, the controller does not generate
1907 * interrupts other than Buffer Read Ready interrupt. But
1908 * to make sure we don't hit a controller bug, we _only_
1909 * enable Buffer Read Ready interrupt here.
1911 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1912 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1915 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1916 * of loops reaches 40 times or a timeout of 150ms occurs.
1920 struct mmc_command cmd = {0};
1921 struct mmc_request mrq = {NULL};
1923 if (!tuning_loop_counter && !timeout)
1926 cmd.opcode = opcode;
1928 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1937 * In response to CMD19, the card sends 64 bytes of tuning
1938 * block to the Host Controller. So we set the block size
1941 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1942 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1943 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1945 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1946 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1949 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1954 * The tuning block is sent by the card to the host controller.
1955 * So we set the TRNS_READ bit in the Transfer Mode register.
1956 * This also takes care of setting DMA Enable and Multi Block
1957 * Select in the same register to 0.
1959 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1961 sdhci_send_command(host, &cmd);
1966 spin_unlock(&host->lock);
1967 enable_irq(host->irq);
1969 /* Wait for Buffer Read Ready interrupt */
1970 wait_event_interruptible_timeout(host->buf_ready_int,
1971 (host->tuning_done == 1),
1972 msecs_to_jiffies(50));
1973 disable_irq(host->irq);
1974 spin_lock(&host->lock);
1976 if (!host->tuning_done) {
1977 pr_info(DRIVER_NAME ": Timeout waiting for "
1978 "Buffer Read Ready interrupt during tuning "
1979 "procedure, falling back to fixed sampling "
1981 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1982 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1983 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1984 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1990 host->tuning_done = 0;
1992 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1993 tuning_loop_counter--;
1996 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1999 * The Host Driver has exhausted the maximum number of loops allowed,
2000 * so use fixed sampling frequency.
2002 if (!tuning_loop_counter || !timeout) {
2003 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2004 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2007 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2008 pr_info(DRIVER_NAME ": Tuning procedure"
2009 " failed, falling back to fixed sampling"
2017 * If this is the very first time we are here, we start the retuning
2018 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2019 * flag won't be set, we check this condition before actually starting
2022 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2023 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2024 host->flags |= SDHCI_USING_RETUNING_TIMER;
2025 mod_timer(&host->tuning_timer, jiffies +
2026 host->tuning_count * HZ);
2027 /* Tuning mode 1 limits the maximum data length to 4MB */
2028 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2030 host->flags &= ~SDHCI_NEEDS_RETUNING;
2031 /* Reload the new initial value for timer */
2032 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2033 mod_timer(&host->tuning_timer, jiffies +
2034 host->tuning_count * HZ);
2038 * In case tuning fails, host controllers which support re-tuning can
2039 * try tuning again at a later time, when the re-tuning timer expires.
2040 * So for these controllers, we return 0. Since there might be other
2041 * controllers who do not have this capability, we return error for
2042 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2043 * a retuning timer to do the retuning for the card.
2045 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2048 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2049 spin_unlock(&host->lock);
2050 enable_irq(host->irq);
2051 sdhci_runtime_pm_put(host);
2057 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2061 /* Host Controller v3.00 defines preset value registers */
2062 if (host->version < SDHCI_SPEC_300)
2065 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2068 * We only enable or disable Preset Value if they are not already
2069 * enabled or disabled respectively. Otherwise, we bail out.
2071 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2072 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2073 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2074 host->flags |= SDHCI_PV_ENABLED;
2075 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2076 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2077 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2078 host->flags &= ~SDHCI_PV_ENABLED;
2082 static void sdhci_card_event(struct mmc_host *mmc)
2084 struct sdhci_host *host = mmc_priv(mmc);
2085 unsigned long flags;
2087 /* First check if client has provided their own card event */
2088 if (host->ops->card_event)
2089 host->ops->card_event(host);
2091 spin_lock_irqsave(&host->lock, flags);
2093 /* Check host->mrq first in case we are runtime suspended */
2094 if (host->mrq && !sdhci_do_get_cd(host)) {
2095 pr_err("%s: Card removed during transfer!\n",
2096 mmc_hostname(host->mmc));
2097 pr_err("%s: Resetting controller.\n",
2098 mmc_hostname(host->mmc));
2100 sdhci_reset(host, SDHCI_RESET_CMD);
2101 sdhci_reset(host, SDHCI_RESET_DATA);
2103 host->mrq->cmd->error = -ENOMEDIUM;
2104 tasklet_schedule(&host->finish_tasklet);
2107 spin_unlock_irqrestore(&host->lock, flags);
2110 static const struct mmc_host_ops sdhci_ops = {
2111 .request = sdhci_request,
2112 .set_ios = sdhci_set_ios,
2113 .get_cd = sdhci_get_cd,
2114 .get_ro = sdhci_get_ro,
2115 .hw_reset = sdhci_hw_reset,
2116 .enable_sdio_irq = sdhci_enable_sdio_irq,
2117 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2118 .execute_tuning = sdhci_execute_tuning,
2119 .card_event = sdhci_card_event,
2120 .card_busy = sdhci_card_busy,
2123 /*****************************************************************************\
2127 \*****************************************************************************/
2129 static void sdhci_tasklet_card(unsigned long param)
2131 struct sdhci_host *host = (struct sdhci_host*)param;
2133 sdhci_card_event(host->mmc);
2135 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2138 static void sdhci_tasklet_finish(unsigned long param)
2140 struct sdhci_host *host;
2141 unsigned long flags;
2142 struct mmc_request *mrq;
2144 host = (struct sdhci_host*)param;
2146 spin_lock_irqsave(&host->lock, flags);
2149 * If this tasklet gets rescheduled while running, it will
2150 * be run again afterwards but without any active request.
2153 spin_unlock_irqrestore(&host->lock, flags);
2157 del_timer(&host->timer);
2162 * The controller needs a reset of internal state machines
2163 * upon error conditions.
2165 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2166 ((mrq->cmd && mrq->cmd->error) ||
2167 (mrq->data && (mrq->data->error ||
2168 (mrq->data->stop && mrq->data->stop->error))) ||
2169 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2171 /* Some controllers need this kick or reset won't work here */
2172 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2173 /* This is to force an update */
2174 sdhci_update_clock(host);
2176 /* Spec says we should do both at the same time, but Ricoh
2177 controllers do not like that. */
2178 sdhci_reset(host, SDHCI_RESET_CMD);
2179 sdhci_reset(host, SDHCI_RESET_DATA);
2186 #ifndef SDHCI_USE_LEDS_CLASS
2187 sdhci_deactivate_led(host);
2191 spin_unlock_irqrestore(&host->lock, flags);
2193 mmc_request_done(host->mmc, mrq);
2194 sdhci_runtime_pm_put(host);
2197 static void sdhci_timeout_timer(unsigned long data)
2199 struct sdhci_host *host;
2200 unsigned long flags;
2202 host = (struct sdhci_host*)data;
2204 spin_lock_irqsave(&host->lock, flags);
2207 pr_err("%s: Timeout waiting for hardware "
2208 "interrupt.\n", mmc_hostname(host->mmc));
2209 sdhci_dumpregs(host);
2212 host->data->error = -ETIMEDOUT;
2213 sdhci_finish_data(host);
2216 host->cmd->error = -ETIMEDOUT;
2218 host->mrq->cmd->error = -ETIMEDOUT;
2220 tasklet_schedule(&host->finish_tasklet);
2225 spin_unlock_irqrestore(&host->lock, flags);
2228 static void sdhci_tuning_timer(unsigned long data)
2230 struct sdhci_host *host;
2231 unsigned long flags;
2233 host = (struct sdhci_host *)data;
2235 spin_lock_irqsave(&host->lock, flags);
2237 host->flags |= SDHCI_NEEDS_RETUNING;
2239 spin_unlock_irqrestore(&host->lock, flags);
2242 /*****************************************************************************\
2244 * Interrupt handling *
2246 \*****************************************************************************/
2248 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2250 BUG_ON(intmask == 0);
2253 pr_err("%s: Got command interrupt 0x%08x even "
2254 "though no command operation was in progress.\n",
2255 mmc_hostname(host->mmc), (unsigned)intmask);
2256 sdhci_dumpregs(host);
2260 if (intmask & SDHCI_INT_TIMEOUT)
2261 host->cmd->error = -ETIMEDOUT;
2262 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2264 host->cmd->error = -EILSEQ;
2266 if (host->cmd->error) {
2267 tasklet_schedule(&host->finish_tasklet);
2272 * The host can send and interrupt when the busy state has
2273 * ended, allowing us to wait without wasting CPU cycles.
2274 * Unfortunately this is overloaded on the "data complete"
2275 * interrupt, so we need to take some care when handling
2278 * Note: The 1.0 specification is a bit ambiguous about this
2279 * feature so there might be some problems with older
2282 if (host->cmd->flags & MMC_RSP_BUSY) {
2283 if (host->cmd->data)
2284 DBG("Cannot wait for busy signal when also "
2285 "doing a data transfer");
2286 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2289 /* The controller does not support the end-of-busy IRQ,
2290 * fall through and take the SDHCI_INT_RESPONSE */
2293 if (intmask & SDHCI_INT_RESPONSE)
2294 sdhci_finish_command(host);
2297 #ifdef CONFIG_MMC_DEBUG
2298 static void sdhci_show_adma_error(struct sdhci_host *host)
2300 const char *name = mmc_hostname(host->mmc);
2301 u8 *desc = host->adma_desc;
2306 sdhci_dumpregs(host);
2309 dma = (__le32 *)(desc + 4);
2310 len = (__le16 *)(desc + 2);
2313 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2314 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2323 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2326 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2329 BUG_ON(intmask == 0);
2331 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2332 if (intmask & SDHCI_INT_DATA_AVAIL) {
2333 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2334 if (command == MMC_SEND_TUNING_BLOCK ||
2335 command == MMC_SEND_TUNING_BLOCK_HS200) {
2336 host->tuning_done = 1;
2337 wake_up(&host->buf_ready_int);
2344 * The "data complete" interrupt is also used to
2345 * indicate that a busy state has ended. See comment
2346 * above in sdhci_cmd_irq().
2348 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2349 if (intmask & SDHCI_INT_DATA_END) {
2350 sdhci_finish_command(host);
2355 pr_err("%s: Got data interrupt 0x%08x even "
2356 "though no data operation was in progress.\n",
2357 mmc_hostname(host->mmc), (unsigned)intmask);
2358 sdhci_dumpregs(host);
2363 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2364 host->data->error = -ETIMEDOUT;
2365 else if (intmask & SDHCI_INT_DATA_END_BIT)
2366 host->data->error = -EILSEQ;
2367 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2368 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2370 host->data->error = -EILSEQ;
2371 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2372 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2373 sdhci_show_adma_error(host);
2374 host->data->error = -EIO;
2375 if (host->ops->adma_workaround)
2376 host->ops->adma_workaround(host, intmask);
2379 if (host->data->error)
2380 sdhci_finish_data(host);
2382 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2383 sdhci_transfer_pio(host);
2386 * We currently don't do anything fancy with DMA
2387 * boundaries, but as we can't disable the feature
2388 * we need to at least restart the transfer.
2390 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2391 * should return a valid address to continue from, but as
2392 * some controllers are faulty, don't trust them.
2394 if (intmask & SDHCI_INT_DMA_END) {
2395 u32 dmastart, dmanow;
2396 dmastart = sg_dma_address(host->data->sg);
2397 dmanow = dmastart + host->data->bytes_xfered;
2399 * Force update to the next DMA block boundary.
2402 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2403 SDHCI_DEFAULT_BOUNDARY_SIZE;
2404 host->data->bytes_xfered = dmanow - dmastart;
2405 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2407 mmc_hostname(host->mmc), dmastart,
2408 host->data->bytes_xfered, dmanow);
2409 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2412 if (intmask & SDHCI_INT_DATA_END) {
2415 * Data managed to finish before the
2416 * command completed. Make sure we do
2417 * things in the proper order.
2419 host->data_early = 1;
2421 sdhci_finish_data(host);
2427 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2430 struct sdhci_host *host = dev_id;
2431 u32 intmask, unexpected = 0;
2432 int cardint = 0, max_loops = 16;
2434 spin_lock(&host->lock);
2436 if (host->runtime_suspended) {
2437 spin_unlock(&host->lock);
2438 pr_warning("%s: got irq while runtime suspended\n",
2439 mmc_hostname(host->mmc));
2443 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2445 if (!intmask || intmask == 0xffffffff) {
2451 DBG("*** %s got interrupt: 0x%08x\n",
2452 mmc_hostname(host->mmc), intmask);
2454 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2455 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2459 * There is a observation on i.mx esdhc. INSERT bit will be
2460 * immediately set again when it gets cleared, if a card is
2461 * inserted. We have to mask the irq to prevent interrupt
2462 * storm which will freeze the system. And the REMOVE gets
2463 * the same situation.
2465 * More testing are needed here to ensure it works for other
2468 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2469 SDHCI_INT_CARD_REMOVE);
2470 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2471 SDHCI_INT_CARD_INSERT);
2473 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2474 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2475 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2476 tasklet_schedule(&host->card_tasklet);
2479 if (intmask & SDHCI_INT_CMD_MASK) {
2480 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2482 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2485 if (intmask & SDHCI_INT_DATA_MASK) {
2486 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2488 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2491 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2493 intmask &= ~SDHCI_INT_ERROR;
2495 if (intmask & SDHCI_INT_BUS_POWER) {
2496 pr_err("%s: Card is consuming too much power!\n",
2497 mmc_hostname(host->mmc));
2498 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2501 intmask &= ~SDHCI_INT_BUS_POWER;
2503 if (intmask & SDHCI_INT_CARD_INT)
2506 intmask &= ~SDHCI_INT_CARD_INT;
2509 unexpected |= intmask;
2510 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2513 result = IRQ_HANDLED;
2515 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2518 * If we know we'll call the driver to signal SDIO IRQ, disregard
2519 * further indications of Card Interrupt in the status to avoid a
2523 intmask &= ~SDHCI_INT_CARD_INT;
2524 if (intmask && --max_loops)
2527 spin_unlock(&host->lock);
2530 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2531 mmc_hostname(host->mmc), unexpected);
2532 sdhci_dumpregs(host);
2535 * We have to delay this as it calls back into the driver.
2538 mmc_signal_sdio_irq(host->mmc);
2543 /*****************************************************************************\
2547 \*****************************************************************************/
2550 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2553 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2554 | SDHCI_WAKE_ON_INT;
2556 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2558 /* Avoid fake wake up */
2559 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2560 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2561 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2563 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2565 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2568 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2569 | SDHCI_WAKE_ON_INT;
2571 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2573 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2575 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2577 int sdhci_suspend_host(struct sdhci_host *host)
2579 if (host->ops->platform_suspend)
2580 host->ops->platform_suspend(host);
2582 sdhci_disable_card_detection(host);
2584 /* Disable tuning since we are suspending */
2585 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2586 del_timer_sync(&host->tuning_timer);
2587 host->flags &= ~SDHCI_NEEDS_RETUNING;
2590 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2591 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2592 free_irq(host->irq, host);
2594 sdhci_enable_irq_wakeups(host);
2595 enable_irq_wake(host->irq);
2600 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2602 int sdhci_resume_host(struct sdhci_host *host)
2606 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2607 if (host->ops->enable_dma)
2608 host->ops->enable_dma(host);
2611 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2612 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2613 mmc_hostname(host->mmc), host);
2617 sdhci_disable_irq_wakeups(host);
2618 disable_irq_wake(host->irq);
2621 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2622 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2623 /* Card keeps power but host controller does not */
2624 sdhci_init(host, 0);
2627 sdhci_do_set_ios(host, &host->mmc->ios);
2629 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2633 sdhci_enable_card_detection(host);
2635 if (host->ops->platform_resume)
2636 host->ops->platform_resume(host);
2638 /* Set the re-tuning expiration flag */
2639 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2640 host->flags |= SDHCI_NEEDS_RETUNING;
2645 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2646 #endif /* CONFIG_PM */
2648 #ifdef CONFIG_PM_RUNTIME
2650 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2652 return pm_runtime_get_sync(host->mmc->parent);
2655 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2657 pm_runtime_mark_last_busy(host->mmc->parent);
2658 return pm_runtime_put_autosuspend(host->mmc->parent);
2661 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2663 if (host->runtime_suspended || host->bus_on)
2665 host->bus_on = true;
2666 pm_runtime_get_noresume(host->mmc->parent);
2669 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2671 if (host->runtime_suspended || !host->bus_on)
2673 host->bus_on = false;
2674 pm_runtime_put_noidle(host->mmc->parent);
2677 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2679 unsigned long flags;
2682 /* Disable tuning since we are suspending */
2683 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2684 del_timer_sync(&host->tuning_timer);
2685 host->flags &= ~SDHCI_NEEDS_RETUNING;
2688 spin_lock_irqsave(&host->lock, flags);
2689 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2690 spin_unlock_irqrestore(&host->lock, flags);
2692 synchronize_irq(host->irq);
2694 spin_lock_irqsave(&host->lock, flags);
2695 host->runtime_suspended = true;
2696 spin_unlock_irqrestore(&host->lock, flags);
2700 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2702 int sdhci_runtime_resume_host(struct sdhci_host *host)
2704 unsigned long flags;
2705 int ret = 0, host_flags = host->flags;
2707 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2708 if (host->ops->enable_dma)
2709 host->ops->enable_dma(host);
2712 sdhci_init(host, 0);
2714 /* Force clock and power re-program */
2717 sdhci_do_set_ios(host, &host->mmc->ios);
2719 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2720 if ((host_flags & SDHCI_PV_ENABLED) &&
2721 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2722 spin_lock_irqsave(&host->lock, flags);
2723 sdhci_enable_preset_value(host, true);
2724 spin_unlock_irqrestore(&host->lock, flags);
2727 /* Set the re-tuning expiration flag */
2728 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2729 host->flags |= SDHCI_NEEDS_RETUNING;
2731 spin_lock_irqsave(&host->lock, flags);
2733 host->runtime_suspended = false;
2735 /* Enable SDIO IRQ */
2736 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2737 sdhci_enable_sdio_irq_nolock(host, true);
2739 /* Enable Card Detection */
2740 sdhci_enable_card_detection(host);
2742 spin_unlock_irqrestore(&host->lock, flags);
2746 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2750 /*****************************************************************************\
2752 * Device allocation/registration *
2754 \*****************************************************************************/
2756 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2759 struct mmc_host *mmc;
2760 struct sdhci_host *host;
2762 WARN_ON(dev == NULL);
2764 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2766 return ERR_PTR(-ENOMEM);
2768 host = mmc_priv(mmc);
2774 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2776 int sdhci_add_host(struct sdhci_host *host)
2778 struct mmc_host *mmc;
2779 u32 caps[2] = {0, 0};
2780 u32 max_current_caps;
2781 unsigned int ocr_avail;
2784 WARN_ON(host == NULL);
2791 host->quirks = debug_quirks;
2793 host->quirks2 = debug_quirks2;
2795 sdhci_reset(host, SDHCI_RESET_ALL);
2797 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2798 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2799 >> SDHCI_SPEC_VER_SHIFT;
2800 if (host->version > SDHCI_SPEC_300) {
2801 pr_err("%s: Unknown controller version (%d). "
2802 "You may experience problems.\n", mmc_hostname(mmc),
2806 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2807 sdhci_readl(host, SDHCI_CAPABILITIES);
2809 if (host->version >= SDHCI_SPEC_300)
2810 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2812 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2814 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2815 host->flags |= SDHCI_USE_SDMA;
2816 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2817 DBG("Controller doesn't have SDMA capability\n");
2819 host->flags |= SDHCI_USE_SDMA;
2821 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2822 (host->flags & SDHCI_USE_SDMA)) {
2823 DBG("Disabling DMA as it is marked broken\n");
2824 host->flags &= ~SDHCI_USE_SDMA;
2827 if ((host->version >= SDHCI_SPEC_200) &&
2828 (caps[0] & SDHCI_CAN_DO_ADMA2))
2829 host->flags |= SDHCI_USE_ADMA;
2831 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2832 (host->flags & SDHCI_USE_ADMA)) {
2833 DBG("Disabling ADMA as it is marked broken\n");
2834 host->flags &= ~SDHCI_USE_ADMA;
2837 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2838 if (host->ops->enable_dma) {
2839 if (host->ops->enable_dma(host)) {
2840 pr_warning("%s: No suitable DMA "
2841 "available. Falling back to PIO.\n",
2844 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2849 if (host->flags & SDHCI_USE_ADMA) {
2851 * We need to allocate descriptors for all sg entries
2852 * (128) and potentially one alignment transfer for
2853 * each of those entries.
2855 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2856 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2857 if (!host->adma_desc || !host->align_buffer) {
2858 kfree(host->adma_desc);
2859 kfree(host->align_buffer);
2860 pr_warning("%s: Unable to allocate ADMA "
2861 "buffers. Falling back to standard DMA.\n",
2863 host->flags &= ~SDHCI_USE_ADMA;
2868 * If we use DMA, then it's up to the caller to set the DMA
2869 * mask, but PIO does not need the hw shim so we set a new
2870 * mask here in that case.
2872 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2873 host->dma_mask = DMA_BIT_MASK(64);
2874 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2877 if (host->version >= SDHCI_SPEC_300)
2878 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2879 >> SDHCI_CLOCK_BASE_SHIFT;
2881 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2882 >> SDHCI_CLOCK_BASE_SHIFT;
2884 host->max_clk *= 1000000;
2885 if (host->max_clk == 0 || host->quirks &
2886 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2887 if (!host->ops->get_max_clock) {
2888 pr_err("%s: Hardware doesn't specify base clock "
2889 "frequency.\n", mmc_hostname(mmc));
2892 host->max_clk = host->ops->get_max_clock(host);
2896 * In case of Host Controller v3.00, find out whether clock
2897 * multiplier is supported.
2899 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2900 SDHCI_CLOCK_MUL_SHIFT;
2903 * In case the value in Clock Multiplier is 0, then programmable
2904 * clock mode is not supported, otherwise the actual clock
2905 * multiplier is one more than the value of Clock Multiplier
2906 * in the Capabilities Register.
2912 * Set host parameters.
2914 mmc->ops = &sdhci_ops;
2915 mmc->f_max = host->max_clk;
2916 if (host->ops->get_min_clock)
2917 mmc->f_min = host->ops->get_min_clock(host);
2918 else if (host->version >= SDHCI_SPEC_300) {
2919 if (host->clk_mul) {
2920 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2921 mmc->f_max = host->max_clk * host->clk_mul;
2923 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2925 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2928 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2929 if (host->timeout_clk == 0) {
2930 if (host->ops->get_timeout_clock) {
2931 host->timeout_clk = host->ops->get_timeout_clock(host);
2932 } else if (!(host->quirks &
2933 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2934 pr_err("%s: Hardware doesn't specify timeout clock "
2935 "frequency.\n", mmc_hostname(mmc));
2939 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2940 host->timeout_clk *= 1000;
2942 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2943 host->timeout_clk = mmc->f_max / 1000;
2945 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2947 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2949 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2950 host->flags |= SDHCI_AUTO_CMD12;
2952 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2953 if ((host->version >= SDHCI_SPEC_300) &&
2954 ((host->flags & SDHCI_USE_ADMA) ||
2955 !(host->flags & SDHCI_USE_SDMA))) {
2956 host->flags |= SDHCI_AUTO_CMD23;
2957 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2959 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2963 * A controller may support 8-bit width, but the board itself
2964 * might not have the pins brought out. Boards that support
2965 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2966 * their platform code before calling sdhci_add_host(), and we
2967 * won't assume 8-bit width for hosts without that CAP.
2969 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2970 mmc->caps |= MMC_CAP_4_BIT_DATA;
2972 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2973 mmc->caps &= ~MMC_CAP_CMD23;
2975 if (caps[0] & SDHCI_CAN_DO_HISPD)
2976 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2978 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2979 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2980 mmc->caps |= MMC_CAP_NEEDS_POLL;
2982 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2983 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
2984 if (IS_ERR_OR_NULL(host->vqmmc)) {
2985 if (PTR_ERR(host->vqmmc) < 0) {
2986 pr_info("%s: no vqmmc regulator found\n",
2991 ret = regulator_enable(host->vqmmc);
2992 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2994 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2995 SDHCI_SUPPORT_SDR50 |
2996 SDHCI_SUPPORT_DDR50);
2998 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2999 mmc_hostname(mmc), ret);
3004 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3005 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3006 SDHCI_SUPPORT_DDR50);
3008 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3009 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3010 SDHCI_SUPPORT_DDR50))
3011 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3013 /* SDR104 supports also implies SDR50 support */
3014 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3015 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3016 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3017 * field can be promoted to support HS200.
3019 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3020 mmc->caps2 |= MMC_CAP2_HS200;
3021 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3022 mmc->caps |= MMC_CAP_UHS_SDR50;
3024 if (caps[1] & SDHCI_SUPPORT_DDR50)
3025 mmc->caps |= MMC_CAP_UHS_DDR50;
3027 /* Does the host need tuning for SDR50? */
3028 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3029 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3031 /* Does the host need tuning for SDR104 / HS200? */
3032 if (mmc->caps2 & MMC_CAP2_HS200)
3033 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3035 /* Driver Type(s) (A, C, D) supported by the host */
3036 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3037 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3038 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3039 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3040 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3041 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3043 /* Initial value for re-tuning timer count */
3044 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3045 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3048 * In case Re-tuning Timer is not disabled, the actual value of
3049 * re-tuning timer will be 2 ^ (n - 1).
3051 if (host->tuning_count)
3052 host->tuning_count = 1 << (host->tuning_count - 1);
3054 /* Re-tuning mode supported by the Host Controller */
3055 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3056 SDHCI_RETUNING_MODE_SHIFT;
3060 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
3061 if (IS_ERR_OR_NULL(host->vmmc)) {
3062 if (PTR_ERR(host->vmmc) < 0) {
3063 pr_info("%s: no vmmc regulator found\n",
3069 #ifdef CONFIG_REGULATOR
3071 * Voltage range check makes sense only if regulator reports
3072 * any voltage value.
3074 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3075 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3077 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3078 caps[0] &= ~SDHCI_CAN_VDD_330;
3079 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3080 caps[0] &= ~SDHCI_CAN_VDD_300;
3081 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3083 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3084 caps[0] &= ~SDHCI_CAN_VDD_180;
3086 #endif /* CONFIG_REGULATOR */
3089 * According to SD Host Controller spec v3.00, if the Host System
3090 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3091 * the value is meaningful only if Voltage Support in the Capabilities
3092 * register is set. The actual current value is 4 times the register
3095 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3096 if (!max_current_caps && host->vmmc) {
3097 u32 curr = regulator_get_current_limit(host->vmmc);
3100 /* convert to SDHCI_MAX_CURRENT format */
3101 curr = curr/1000; /* convert to mA */
3102 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3104 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3106 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3107 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3108 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3112 if (caps[0] & SDHCI_CAN_VDD_330) {
3113 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3115 mmc->max_current_330 = ((max_current_caps &
3116 SDHCI_MAX_CURRENT_330_MASK) >>
3117 SDHCI_MAX_CURRENT_330_SHIFT) *
3118 SDHCI_MAX_CURRENT_MULTIPLIER;
3120 if (caps[0] & SDHCI_CAN_VDD_300) {
3121 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3123 mmc->max_current_300 = ((max_current_caps &
3124 SDHCI_MAX_CURRENT_300_MASK) >>
3125 SDHCI_MAX_CURRENT_300_SHIFT) *
3126 SDHCI_MAX_CURRENT_MULTIPLIER;
3128 if (caps[0] & SDHCI_CAN_VDD_180) {
3129 ocr_avail |= MMC_VDD_165_195;
3131 mmc->max_current_180 = ((max_current_caps &
3132 SDHCI_MAX_CURRENT_180_MASK) >>
3133 SDHCI_MAX_CURRENT_180_SHIFT) *
3134 SDHCI_MAX_CURRENT_MULTIPLIER;
3138 ocr_avail = host->ocr_mask;
3140 mmc->ocr_avail = ocr_avail;
3141 mmc->ocr_avail_sdio = ocr_avail;
3142 if (host->ocr_avail_sdio)
3143 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3144 mmc->ocr_avail_sd = ocr_avail;
3145 if (host->ocr_avail_sd)
3146 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3147 else /* normal SD controllers don't support 1.8V */
3148 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3149 mmc->ocr_avail_mmc = ocr_avail;
3150 if (host->ocr_avail_mmc)
3151 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3153 if (mmc->ocr_avail == 0) {
3154 pr_err("%s: Hardware doesn't report any "
3155 "support voltages.\n", mmc_hostname(mmc));
3159 spin_lock_init(&host->lock);
3162 * Maximum number of segments. Depends on if the hardware
3163 * can do scatter/gather or not.
3165 if (host->flags & SDHCI_USE_ADMA)
3166 mmc->max_segs = 128;
3167 else if (host->flags & SDHCI_USE_SDMA)
3170 mmc->max_segs = 128;
3173 * Maximum number of sectors in one transfer. Limited by DMA boundary
3176 mmc->max_req_size = 524288;
3179 * Maximum segment size. Could be one segment with the maximum number
3180 * of bytes. When doing hardware scatter/gather, each entry cannot
3181 * be larger than 64 KiB though.
3183 if (host->flags & SDHCI_USE_ADMA) {
3184 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3185 mmc->max_seg_size = 65535;
3187 mmc->max_seg_size = 65536;
3189 mmc->max_seg_size = mmc->max_req_size;
3193 * Maximum block size. This varies from controller to controller and
3194 * is specified in the capabilities register.
3196 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3197 mmc->max_blk_size = 2;
3199 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3200 SDHCI_MAX_BLOCK_SHIFT;
3201 if (mmc->max_blk_size >= 3) {
3202 pr_warning("%s: Invalid maximum block size, "
3203 "assuming 512 bytes\n", mmc_hostname(mmc));
3204 mmc->max_blk_size = 0;
3208 mmc->max_blk_size = 512 << mmc->max_blk_size;
3211 * Maximum block count.
3213 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3218 tasklet_init(&host->card_tasklet,
3219 sdhci_tasklet_card, (unsigned long)host);
3220 tasklet_init(&host->finish_tasklet,
3221 sdhci_tasklet_finish, (unsigned long)host);
3223 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3225 if (host->version >= SDHCI_SPEC_300) {
3226 init_waitqueue_head(&host->buf_ready_int);
3228 /* Initialize re-tuning timer */
3229 init_timer(&host->tuning_timer);
3230 host->tuning_timer.data = (unsigned long)host;
3231 host->tuning_timer.function = sdhci_tuning_timer;
3234 sdhci_init(host, 0);
3236 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3237 mmc_hostname(mmc), host);
3239 pr_err("%s: Failed to request IRQ %d: %d\n",
3240 mmc_hostname(mmc), host->irq, ret);
3244 #ifdef CONFIG_MMC_DEBUG
3245 sdhci_dumpregs(host);
3248 #ifdef SDHCI_USE_LEDS_CLASS
3249 snprintf(host->led_name, sizeof(host->led_name),
3250 "%s::", mmc_hostname(mmc));
3251 host->led.name = host->led_name;
3252 host->led.brightness = LED_OFF;
3253 host->led.default_trigger = mmc_hostname(mmc);
3254 host->led.brightness_set = sdhci_led_control;
3256 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3258 pr_err("%s: Failed to register LED device: %d\n",
3259 mmc_hostname(mmc), ret);
3268 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3269 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3270 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3271 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3273 sdhci_enable_card_detection(host);
3277 #ifdef SDHCI_USE_LEDS_CLASS
3279 sdhci_reset(host, SDHCI_RESET_ALL);
3280 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3281 free_irq(host->irq, host);
3284 tasklet_kill(&host->card_tasklet);
3285 tasklet_kill(&host->finish_tasklet);
3290 EXPORT_SYMBOL_GPL(sdhci_add_host);
3292 void sdhci_remove_host(struct sdhci_host *host, int dead)
3294 unsigned long flags;
3297 spin_lock_irqsave(&host->lock, flags);
3299 host->flags |= SDHCI_DEVICE_DEAD;
3302 pr_err("%s: Controller removed during "
3303 " transfer!\n", mmc_hostname(host->mmc));
3305 host->mrq->cmd->error = -ENOMEDIUM;
3306 tasklet_schedule(&host->finish_tasklet);
3309 spin_unlock_irqrestore(&host->lock, flags);
3312 sdhci_disable_card_detection(host);
3314 mmc_remove_host(host->mmc);
3316 #ifdef SDHCI_USE_LEDS_CLASS
3317 led_classdev_unregister(&host->led);
3321 sdhci_reset(host, SDHCI_RESET_ALL);
3323 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3324 free_irq(host->irq, host);
3326 del_timer_sync(&host->timer);
3328 tasklet_kill(&host->card_tasklet);
3329 tasklet_kill(&host->finish_tasklet);
3332 regulator_disable(host->vmmc);
3333 regulator_put(host->vmmc);
3337 regulator_disable(host->vqmmc);
3338 regulator_put(host->vqmmc);
3341 kfree(host->adma_desc);
3342 kfree(host->align_buffer);
3344 host->adma_desc = NULL;
3345 host->align_buffer = NULL;
3348 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3350 void sdhci_free_host(struct sdhci_host *host)
3352 mmc_free_host(host->mmc);
3355 EXPORT_SYMBOL_GPL(sdhci_free_host);
3357 /*****************************************************************************\
3359 * Driver init/exit *
3361 \*****************************************************************************/
3363 static int __init sdhci_drv_init(void)
3366 ": Secure Digital Host Controller Interface driver\n");
3367 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3372 static void __exit sdhci_drv_exit(void)
3376 module_init(sdhci_drv_init);
3377 module_exit(sdhci_drv_exit);
3379 module_param(debug_quirks, uint, 0444);
3380 module_param(debug_quirks2, uint, 0444);
3382 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3383 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3384 MODULE_LICENSE("GPL");
3386 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3387 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");