2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
27 #include <linux/leds.h>
29 #include <linux/mmc/mmc.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/card.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
37 #define DRIVER_NAME "sdhci"
39 #define DBG(f, x...) \
40 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
42 #define MAX_TUNING_LOOP 40
44 static unsigned int debug_quirks = 0;
45 static unsigned int debug_quirks2;
47 static void sdhci_finish_data(struct sdhci_host *);
49 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51 static void sdhci_dumpregs(struct sdhci_host *host)
53 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
54 mmc_hostname(host->mmc));
56 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
57 sdhci_readl(host, SDHCI_DMA_ADDRESS),
58 sdhci_readw(host, SDHCI_HOST_VERSION));
59 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
60 sdhci_readw(host, SDHCI_BLOCK_SIZE),
61 sdhci_readw(host, SDHCI_BLOCK_COUNT));
62 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
63 sdhci_readl(host, SDHCI_ARGUMENT),
64 sdhci_readw(host, SDHCI_TRANSFER_MODE));
65 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
66 sdhci_readl(host, SDHCI_PRESENT_STATE),
67 sdhci_readb(host, SDHCI_HOST_CONTROL));
68 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
69 sdhci_readb(host, SDHCI_POWER_CONTROL),
70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
71 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
73 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
74 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
76 sdhci_readl(host, SDHCI_INT_STATUS));
77 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
78 sdhci_readl(host, SDHCI_INT_ENABLE),
79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
80 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
81 sdhci_readw(host, SDHCI_ACMD12_ERR),
82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
83 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
84 sdhci_readl(host, SDHCI_CAPABILITIES),
85 sdhci_readl(host, SDHCI_CAPABILITIES_1));
86 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
87 sdhci_readw(host, SDHCI_COMMAND),
88 sdhci_readl(host, SDHCI_MAX_CURRENT));
89 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
90 sdhci_readw(host, SDHCI_HOST_CONTROL2));
92 if (host->flags & SDHCI_USE_ADMA) {
93 if (host->flags & SDHCI_USE_64_BIT_DMA)
94 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
97 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
99 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
100 readl(host->ioaddr + SDHCI_ADMA_ERROR),
101 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
104 pr_err(DRIVER_NAME ": ===========================================\n");
107 /*****************************************************************************\
109 * Low level functions *
111 \*****************************************************************************/
113 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
115 return cmd->data || cmd->flags & MMC_RSP_BUSY;
118 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
122 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
123 !mmc_card_is_removable(host->mmc))
127 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
130 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
131 SDHCI_INT_CARD_INSERT;
133 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
136 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
137 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
140 static void sdhci_enable_card_detection(struct sdhci_host *host)
142 sdhci_set_card_detection(host, true);
145 static void sdhci_disable_card_detection(struct sdhci_host *host)
147 sdhci_set_card_detection(host, false);
150 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
155 pm_runtime_get_noresume(host->mmc->parent);
158 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
162 host->bus_on = false;
163 pm_runtime_put_noidle(host->mmc->parent);
166 void sdhci_reset(struct sdhci_host *host, u8 mask)
168 unsigned long timeout;
170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
172 if (mask & SDHCI_RESET_ALL) {
174 /* Reset-all turns off SD Bus Power */
175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
176 sdhci_runtime_pm_bus_off(host);
179 /* Wait max 100 ms */
182 /* hw clears the bit when it's done */
183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
185 pr_err("%s: Reset 0x%x never completed.\n",
186 mmc_hostname(host->mmc), (int)mask);
187 sdhci_dumpregs(host);
194 EXPORT_SYMBOL_GPL(sdhci_reset);
196 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
199 struct mmc_host *mmc = host->mmc;
201 if (!mmc->ops->get_cd(mmc))
205 host->ops->reset(host, mask);
207 if (mask & SDHCI_RESET_ALL) {
208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if (host->ops->enable_dma)
210 host->ops->enable_dma(host);
213 /* Resetting the controller clears many */
214 host->preset_enabled = false;
218 static void sdhci_init(struct sdhci_host *host, int soft)
220 struct mmc_host *mmc = host->mmc;
223 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
225 sdhci_do_reset(host, SDHCI_RESET_ALL);
227 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
229 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
230 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
233 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
234 host->tuning_mode == SDHCI_TUNING_MODE_3)
235 host->ier |= SDHCI_INT_RETUNE;
237 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
238 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
241 /* force clock reconfiguration */
243 mmc->ops->set_ios(mmc, &mmc->ios);
247 static void sdhci_reinit(struct sdhci_host *host)
250 sdhci_enable_card_detection(host);
253 static void __sdhci_led_activate(struct sdhci_host *host)
257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
258 ctrl |= SDHCI_CTRL_LED;
259 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
262 static void __sdhci_led_deactivate(struct sdhci_host *host)
266 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
267 ctrl &= ~SDHCI_CTRL_LED;
268 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
271 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
272 static void sdhci_led_control(struct led_classdev *led,
273 enum led_brightness brightness)
275 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 spin_lock_irqsave(&host->lock, flags);
280 if (host->runtime_suspended)
283 if (brightness == LED_OFF)
284 __sdhci_led_deactivate(host);
286 __sdhci_led_activate(host);
288 spin_unlock_irqrestore(&host->lock, flags);
291 static int sdhci_led_register(struct sdhci_host *host)
293 struct mmc_host *mmc = host->mmc;
295 snprintf(host->led_name, sizeof(host->led_name),
296 "%s::", mmc_hostname(mmc));
298 host->led.name = host->led_name;
299 host->led.brightness = LED_OFF;
300 host->led.default_trigger = mmc_hostname(mmc);
301 host->led.brightness_set = sdhci_led_control;
303 return led_classdev_register(mmc_dev(mmc), &host->led);
306 static void sdhci_led_unregister(struct sdhci_host *host)
308 led_classdev_unregister(&host->led);
311 static inline void sdhci_led_activate(struct sdhci_host *host)
315 static inline void sdhci_led_deactivate(struct sdhci_host *host)
321 static inline int sdhci_led_register(struct sdhci_host *host)
326 static inline void sdhci_led_unregister(struct sdhci_host *host)
330 static inline void sdhci_led_activate(struct sdhci_host *host)
332 __sdhci_led_activate(host);
335 static inline void sdhci_led_deactivate(struct sdhci_host *host)
337 __sdhci_led_deactivate(host);
342 /*****************************************************************************\
346 \*****************************************************************************/
348 static void sdhci_read_block_pio(struct sdhci_host *host)
351 size_t blksize, len, chunk;
352 u32 uninitialized_var(scratch);
355 DBG("PIO reading\n");
357 blksize = host->data->blksz;
360 local_irq_save(flags);
363 BUG_ON(!sg_miter_next(&host->sg_miter));
365 len = min(host->sg_miter.length, blksize);
368 host->sg_miter.consumed = len;
370 buf = host->sg_miter.addr;
374 scratch = sdhci_readl(host, SDHCI_BUFFER);
378 *buf = scratch & 0xFF;
387 sg_miter_stop(&host->sg_miter);
389 local_irq_restore(flags);
392 static void sdhci_write_block_pio(struct sdhci_host *host)
395 size_t blksize, len, chunk;
399 DBG("PIO writing\n");
401 blksize = host->data->blksz;
405 local_irq_save(flags);
408 BUG_ON(!sg_miter_next(&host->sg_miter));
410 len = min(host->sg_miter.length, blksize);
413 host->sg_miter.consumed = len;
415 buf = host->sg_miter.addr;
418 scratch |= (u32)*buf << (chunk * 8);
424 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
425 sdhci_writel(host, scratch, SDHCI_BUFFER);
432 sg_miter_stop(&host->sg_miter);
434 local_irq_restore(flags);
437 static void sdhci_transfer_pio(struct sdhci_host *host)
441 if (host->blocks == 0)
444 if (host->data->flags & MMC_DATA_READ)
445 mask = SDHCI_DATA_AVAILABLE;
447 mask = SDHCI_SPACE_AVAILABLE;
450 * Some controllers (JMicron JMB38x) mess up the buffer bits
451 * for transfers < 4 bytes. As long as it is just one block,
452 * we can ignore the bits.
454 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
455 (host->data->blocks == 1))
458 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
459 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
462 if (host->data->flags & MMC_DATA_READ)
463 sdhci_read_block_pio(host);
465 sdhci_write_block_pio(host);
468 if (host->blocks == 0)
472 DBG("PIO transfer complete.\n");
475 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
476 struct mmc_data *data, int cookie)
481 * If the data buffers are already mapped, return the previous
482 * dma_map_sg() result.
484 if (data->host_cookie == COOKIE_PRE_MAPPED)
485 return data->sg_count;
487 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
488 data->flags & MMC_DATA_WRITE ?
489 DMA_TO_DEVICE : DMA_FROM_DEVICE);
494 data->sg_count = sg_count;
495 data->host_cookie = cookie;
500 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
502 local_irq_save(*flags);
503 return kmap_atomic(sg_page(sg)) + sg->offset;
506 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
508 kunmap_atomic(buffer);
509 local_irq_restore(*flags);
512 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
513 dma_addr_t addr, int len, unsigned cmd)
515 struct sdhci_adma2_64_desc *dma_desc = desc;
517 /* 32-bit and 64-bit descriptors have these members in same position */
518 dma_desc->cmd = cpu_to_le16(cmd);
519 dma_desc->len = cpu_to_le16(len);
520 dma_desc->addr_lo = cpu_to_le32((u32)addr);
522 if (host->flags & SDHCI_USE_64_BIT_DMA)
523 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
526 static void sdhci_adma_mark_end(void *desc)
528 struct sdhci_adma2_64_desc *dma_desc = desc;
530 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
531 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
534 static void sdhci_adma_table_pre(struct sdhci_host *host,
535 struct mmc_data *data, int sg_count)
537 struct scatterlist *sg;
539 dma_addr_t addr, align_addr;
545 * The spec does not specify endianness of descriptor table.
546 * We currently guess that it is LE.
549 host->sg_count = sg_count;
551 desc = host->adma_table;
552 align = host->align_buffer;
554 align_addr = host->align_addr;
556 for_each_sg(data->sg, sg, host->sg_count, i) {
557 addr = sg_dma_address(sg);
558 len = sg_dma_len(sg);
561 * The SDHCI specification states that ADMA addresses must
562 * be 32-bit aligned. If they aren't, then we use a bounce
563 * buffer for the (up to three) bytes that screw up the
566 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
569 if (data->flags & MMC_DATA_WRITE) {
570 buffer = sdhci_kmap_atomic(sg, &flags);
571 memcpy(align, buffer, offset);
572 sdhci_kunmap_atomic(buffer, &flags);
576 sdhci_adma_write_desc(host, desc, align_addr, offset,
579 BUG_ON(offset > 65536);
581 align += SDHCI_ADMA2_ALIGN;
582 align_addr += SDHCI_ADMA2_ALIGN;
584 desc += host->desc_sz;
594 sdhci_adma_write_desc(host, desc, addr, len,
596 desc += host->desc_sz;
600 * If this triggers then we have a calculation bug
603 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
606 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
607 /* Mark the last descriptor as the terminating descriptor */
608 if (desc != host->adma_table) {
609 desc -= host->desc_sz;
610 sdhci_adma_mark_end(desc);
613 /* Add a terminating entry - nop, end, valid */
614 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
618 static void sdhci_adma_table_post(struct sdhci_host *host,
619 struct mmc_data *data)
621 struct scatterlist *sg;
627 if (data->flags & MMC_DATA_READ) {
628 bool has_unaligned = false;
630 /* Do a quick scan of the SG list for any unaligned mappings */
631 for_each_sg(data->sg, sg, host->sg_count, i)
632 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
633 has_unaligned = true;
638 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
639 data->sg_len, DMA_FROM_DEVICE);
641 align = host->align_buffer;
643 for_each_sg(data->sg, sg, host->sg_count, i) {
644 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
645 size = SDHCI_ADMA2_ALIGN -
646 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
648 buffer = sdhci_kmap_atomic(sg, &flags);
649 memcpy(buffer, align, size);
650 sdhci_kunmap_atomic(buffer, &flags);
652 align += SDHCI_ADMA2_ALIGN;
659 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
662 struct mmc_data *data = cmd->data;
663 unsigned target_timeout, current_timeout;
666 * If the host controller provides us with an incorrect timeout
667 * value, just skip the check and use 0xE. The hardware may take
668 * longer to time out, but that's much better than having a too-short
671 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
674 /* Unspecified timeout, assume max */
675 if (!data && !cmd->busy_timeout)
680 target_timeout = cmd->busy_timeout * 1000;
682 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
683 if (host->clock && data->timeout_clks) {
684 unsigned long long val;
687 * data->timeout_clks is in units of clock cycles.
688 * host->clock is in Hz. target_timeout is in us.
689 * Hence, us = 1000000 * cycles / Hz. Round up.
691 val = 1000000ULL * data->timeout_clks;
692 if (do_div(val, host->clock))
694 target_timeout += val;
699 * Figure out needed cycles.
700 * We do this in steps in order to fit inside a 32 bit int.
701 * The first step is the minimum timeout, which will have a
702 * minimum resolution of 6 bits:
703 * (1) 2^13*1000 > 2^22,
704 * (2) host->timeout_clk < 2^16
709 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
710 while (current_timeout < target_timeout) {
712 current_timeout <<= 1;
718 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
719 mmc_hostname(host->mmc), count, cmd->opcode);
726 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
728 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
729 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
731 if (host->flags & SDHCI_REQ_USE_DMA)
732 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
734 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
740 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
744 if (host->ops->set_timeout) {
745 host->ops->set_timeout(host, cmd);
747 count = sdhci_calc_timeout(host, cmd);
748 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
752 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
755 struct mmc_data *data = cmd->data;
757 if (sdhci_data_line_cmd(cmd))
758 sdhci_set_timeout(host, cmd);
766 BUG_ON(data->blksz * data->blocks > 524288);
767 BUG_ON(data->blksz > host->mmc->max_blk_size);
768 BUG_ON(data->blocks > 65535);
771 host->data_early = 0;
772 host->data->bytes_xfered = 0;
774 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
775 struct scatterlist *sg;
776 unsigned int length_mask, offset_mask;
779 host->flags |= SDHCI_REQ_USE_DMA;
782 * FIXME: This doesn't account for merging when mapping the
785 * The assumption here being that alignment and lengths are
786 * the same after DMA mapping to device address space.
790 if (host->flags & SDHCI_USE_ADMA) {
791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
794 * As we use up to 3 byte chunks to work
795 * around alignment problems, we need to
796 * check the offset as well.
801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
803 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
807 if (unlikely(length_mask | offset_mask)) {
808 for_each_sg(data->sg, sg, data->sg_len, i) {
809 if (sg->length & length_mask) {
810 DBG("Reverting to PIO because of transfer size (%d)\n",
812 host->flags &= ~SDHCI_REQ_USE_DMA;
815 if (sg->offset & offset_mask) {
816 DBG("Reverting to PIO because of bad alignment\n");
817 host->flags &= ~SDHCI_REQ_USE_DMA;
824 if (host->flags & SDHCI_REQ_USE_DMA) {
825 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
829 * This only happens when someone fed
830 * us an invalid request.
833 host->flags &= ~SDHCI_REQ_USE_DMA;
834 } else if (host->flags & SDHCI_USE_ADMA) {
835 sdhci_adma_table_pre(host, data, sg_cnt);
837 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
838 if (host->flags & SDHCI_USE_64_BIT_DMA)
840 (u64)host->adma_addr >> 32,
841 SDHCI_ADMA_ADDRESS_HI);
843 WARN_ON(sg_cnt != 1);
844 sdhci_writel(host, sg_dma_address(data->sg),
850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
854 if (host->version >= SDHCI_SPEC_200) {
855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
858 (host->flags & SDHCI_USE_ADMA)) {
859 if (host->flags & SDHCI_USE_64_BIT_DMA)
860 ctrl |= SDHCI_CTRL_ADMA64;
862 ctrl |= SDHCI_CTRL_ADMA32;
864 ctrl |= SDHCI_CTRL_SDMA;
866 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
869 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
872 flags = SG_MITER_ATOMIC;
873 if (host->data->flags & MMC_DATA_READ)
874 flags |= SG_MITER_TO_SG;
876 flags |= SG_MITER_FROM_SG;
877 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
878 host->blocks = data->blocks;
881 sdhci_set_transfer_irqs(host);
883 /* Set the DMA boundary value and block size */
884 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
885 data->blksz), SDHCI_BLOCK_SIZE);
886 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
889 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
890 struct mmc_request *mrq)
892 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
893 !mrq->cap_cmd_during_tfr;
896 static void sdhci_set_transfer_mode(struct sdhci_host *host,
897 struct mmc_command *cmd)
900 struct mmc_data *data = cmd->data;
904 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
905 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
907 /* clear Auto CMD settings for no data CMDs */
908 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
909 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
910 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
915 WARN_ON(!host->data);
917 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
918 mode = SDHCI_TRNS_BLK_CNT_EN;
920 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
921 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
923 * If we are sending CMD23, CMD12 never gets sent
924 * on successful completion (so no Auto-CMD12).
926 if (sdhci_auto_cmd12(host, cmd->mrq) &&
927 (cmd->opcode != SD_IO_RW_EXTENDED))
928 mode |= SDHCI_TRNS_AUTO_CMD12;
929 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
930 mode |= SDHCI_TRNS_AUTO_CMD23;
931 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
935 if (data->flags & MMC_DATA_READ)
936 mode |= SDHCI_TRNS_READ;
937 if (host->flags & SDHCI_REQ_USE_DMA)
938 mode |= SDHCI_TRNS_DMA;
940 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
943 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
945 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
946 ((mrq->cmd && mrq->cmd->error) ||
947 (mrq->sbc && mrq->sbc->error) ||
948 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
949 (mrq->data->stop && mrq->data->stop->error))) ||
950 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
953 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
957 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
958 if (host->mrqs_done[i] == mrq) {
964 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
965 if (!host->mrqs_done[i]) {
966 host->mrqs_done[i] = mrq;
971 WARN_ON(i >= SDHCI_MAX_MRQS);
973 tasklet_schedule(&host->finish_tasklet);
976 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
978 if (host->cmd && host->cmd->mrq == mrq)
981 if (host->data_cmd && host->data_cmd->mrq == mrq)
982 host->data_cmd = NULL;
984 if (host->data && host->data->mrq == mrq)
987 if (sdhci_needs_reset(host, mrq))
988 host->pending_reset = true;
990 __sdhci_finish_mrq(host, mrq);
993 static void sdhci_finish_data(struct sdhci_host *host)
995 struct mmc_command *data_cmd = host->data_cmd;
996 struct mmc_data *data = host->data;
999 host->data_cmd = NULL;
1001 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1002 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1003 sdhci_adma_table_post(host, data);
1006 * The specification states that the block count register must
1007 * be updated, but it does not specify at what point in the
1008 * data flow. That makes the register entirely useless to read
1009 * back so we have to assume that nothing made it to the card
1010 * in the event of an error.
1013 data->bytes_xfered = 0;
1015 data->bytes_xfered = data->blksz * data->blocks;
1018 * Need to send CMD12 if -
1019 * a) open-ended multiblock transfer (no CMD23)
1020 * b) error in multiblock transfer
1027 * The controller needs a reset of internal state machines
1028 * upon error conditions.
1031 if (!host->cmd || host->cmd == data_cmd)
1032 sdhci_do_reset(host, SDHCI_RESET_CMD);
1033 sdhci_do_reset(host, SDHCI_RESET_DATA);
1037 * 'cap_cmd_during_tfr' request must not use the command line
1038 * after mmc_command_done() has been called. It is upper layer's
1039 * responsibility to send the stop command if required.
1041 if (data->mrq->cap_cmd_during_tfr) {
1042 sdhci_finish_mrq(host, data->mrq);
1044 /* Avoid triggering warning in sdhci_send_command() */
1046 sdhci_send_command(host, data->stop);
1049 sdhci_finish_mrq(host, data->mrq);
1053 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1054 unsigned long timeout)
1056 if (sdhci_data_line_cmd(mrq->cmd))
1057 mod_timer(&host->data_timer, timeout);
1059 mod_timer(&host->timer, timeout);
1062 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1064 if (sdhci_data_line_cmd(mrq->cmd))
1065 del_timer(&host->data_timer);
1067 del_timer(&host->timer);
1070 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1074 unsigned long timeout;
1078 /* Initially, a command has no error */
1081 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1082 cmd->opcode == MMC_STOP_TRANSMISSION)
1083 cmd->flags |= MMC_RSP_BUSY;
1085 /* Wait max 10 ms */
1088 mask = SDHCI_CMD_INHIBIT;
1089 if (sdhci_data_line_cmd(cmd))
1090 mask |= SDHCI_DATA_INHIBIT;
1092 /* We shouldn't wait for data inihibit for stop commands, even
1093 though they might use busy signaling */
1094 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1095 mask &= ~SDHCI_DATA_INHIBIT;
1097 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1099 pr_err("%s: Controller never released inhibit bit(s).\n",
1100 mmc_hostname(host->mmc));
1101 sdhci_dumpregs(host);
1103 sdhci_finish_mrq(host, cmd->mrq);
1111 if (!cmd->data && cmd->busy_timeout > 9000)
1112 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1115 sdhci_mod_timer(host, cmd->mrq, timeout);
1118 if (sdhci_data_line_cmd(cmd)) {
1119 WARN_ON(host->data_cmd);
1120 host->data_cmd = cmd;
1123 sdhci_prepare_data(host, cmd);
1125 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1127 sdhci_set_transfer_mode(host, cmd);
1129 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1130 pr_err("%s: Unsupported response type!\n",
1131 mmc_hostname(host->mmc));
1132 cmd->error = -EINVAL;
1133 sdhci_finish_mrq(host, cmd->mrq);
1137 if (!(cmd->flags & MMC_RSP_PRESENT))
1138 flags = SDHCI_CMD_RESP_NONE;
1139 else if (cmd->flags & MMC_RSP_136)
1140 flags = SDHCI_CMD_RESP_LONG;
1141 else if (cmd->flags & MMC_RSP_BUSY)
1142 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1144 flags = SDHCI_CMD_RESP_SHORT;
1146 if (cmd->flags & MMC_RSP_CRC)
1147 flags |= SDHCI_CMD_CRC;
1148 if (cmd->flags & MMC_RSP_OPCODE)
1149 flags |= SDHCI_CMD_INDEX;
1151 /* CMD19 is special in that the Data Present Select should be set */
1152 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1153 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1154 flags |= SDHCI_CMD_DATA;
1156 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1158 EXPORT_SYMBOL_GPL(sdhci_send_command);
1160 static void sdhci_finish_command(struct sdhci_host *host)
1162 struct mmc_command *cmd = host->cmd;
1167 if (cmd->flags & MMC_RSP_PRESENT) {
1168 if (cmd->flags & MMC_RSP_136) {
1169 /* CRC is stripped so we need to do some shifting. */
1170 for (i = 0;i < 4;i++) {
1171 cmd->resp[i] = sdhci_readl(host,
1172 SDHCI_RESPONSE + (3-i)*4) << 8;
1176 SDHCI_RESPONSE + (3-i)*4-1);
1179 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1183 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1184 mmc_command_done(host->mmc, cmd->mrq);
1187 * The host can send and interrupt when the busy state has
1188 * ended, allowing us to wait without wasting CPU cycles.
1189 * The busy signal uses DAT0 so this is similar to waiting
1190 * for data to complete.
1192 * Note: The 1.0 specification is a bit ambiguous about this
1193 * feature so there might be some problems with older
1196 if (cmd->flags & MMC_RSP_BUSY) {
1198 DBG("Cannot wait for busy signal when also doing a data transfer");
1199 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1200 cmd == host->data_cmd) {
1201 /* Command complete before busy is ended */
1206 /* Finished CMD23, now send actual command. */
1207 if (cmd == cmd->mrq->sbc) {
1208 sdhci_send_command(host, cmd->mrq->cmd);
1211 /* Processed actual command. */
1212 if (host->data && host->data_early)
1213 sdhci_finish_data(host);
1216 sdhci_finish_mrq(host, cmd->mrq);
1220 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1224 switch (host->timing) {
1225 case MMC_TIMING_UHS_SDR12:
1226 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1228 case MMC_TIMING_UHS_SDR25:
1229 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1231 case MMC_TIMING_UHS_SDR50:
1232 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1234 case MMC_TIMING_UHS_SDR104:
1235 case MMC_TIMING_MMC_HS200:
1236 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1238 case MMC_TIMING_UHS_DDR50:
1239 case MMC_TIMING_MMC_DDR52:
1240 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1242 case MMC_TIMING_MMC_HS400:
1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1246 pr_warn("%s: Invalid UHS-I mode selected\n",
1247 mmc_hostname(host->mmc));
1248 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1254 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1255 unsigned int *actual_clock)
1257 int div = 0; /* Initialized for compiler warning */
1258 int real_div = div, clk_mul = 1;
1260 bool switch_base_clk = false;
1262 if (host->version >= SDHCI_SPEC_300) {
1263 if (host->preset_enabled) {
1266 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1267 pre_val = sdhci_get_preset_value(host);
1268 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1269 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1270 if (host->clk_mul &&
1271 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1272 clk = SDHCI_PROG_CLOCK_MODE;
1274 clk_mul = host->clk_mul;
1276 real_div = max_t(int, 1, div << 1);
1282 * Check if the Host Controller supports Programmable Clock
1285 if (host->clk_mul) {
1286 for (div = 1; div <= 1024; div++) {
1287 if ((host->max_clk * host->clk_mul / div)
1291 if ((host->max_clk * host->clk_mul / div) <= clock) {
1293 * Set Programmable Clock Mode in the Clock
1296 clk = SDHCI_PROG_CLOCK_MODE;
1298 clk_mul = host->clk_mul;
1302 * Divisor can be too small to reach clock
1303 * speed requirement. Then use the base clock.
1305 switch_base_clk = true;
1309 if (!host->clk_mul || switch_base_clk) {
1310 /* Version 3.00 divisors must be a multiple of 2. */
1311 if (host->max_clk <= clock)
1314 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1316 if ((host->max_clk / div) <= clock)
1322 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1323 && !div && host->max_clk <= 25000000)
1327 /* Version 2.00 divisors must be a power of 2. */
1328 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1329 if ((host->max_clk / div) <= clock)
1338 *actual_clock = (host->max_clk * clk_mul) / real_div;
1339 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1340 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1341 << SDHCI_DIVIDER_HI_SHIFT;
1345 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1347 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1349 unsigned long timeout;
1351 clk |= SDHCI_CLOCK_INT_EN;
1352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1354 /* Wait max 20 ms */
1356 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1357 & SDHCI_CLOCK_INT_STABLE)) {
1359 pr_err("%s: Internal clock never stabilised.\n",
1360 mmc_hostname(host->mmc));
1361 sdhci_dumpregs(host);
1365 spin_unlock_irq(&host->lock);
1366 usleep_range(900, 1100);
1367 spin_lock_irq(&host->lock);
1370 clk |= SDHCI_CLOCK_CARD_EN;
1371 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1373 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1375 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1379 host->mmc->actual_clock = 0;
1381 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1386 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1387 sdhci_enable_clk(host, clk);
1389 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1391 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1394 struct mmc_host *mmc = host->mmc;
1396 spin_unlock_irq(&host->lock);
1397 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1398 spin_lock_irq(&host->lock);
1400 if (mode != MMC_POWER_OFF)
1401 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1403 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1406 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1411 if (mode != MMC_POWER_OFF) {
1413 case MMC_VDD_165_195:
1414 pwr = SDHCI_POWER_180;
1418 pwr = SDHCI_POWER_300;
1422 pwr = SDHCI_POWER_330;
1425 WARN(1, "%s: Invalid vdd %#x\n",
1426 mmc_hostname(host->mmc), vdd);
1431 if (host->pwr == pwr)
1437 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1438 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1439 sdhci_runtime_pm_bus_off(host);
1442 * Spec says that we should clear the power reg before setting
1443 * a new value. Some controllers don't seem to like this though.
1445 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1446 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1449 * At least the Marvell CaFe chip gets confused if we set the
1450 * voltage and set turn on power at the same time, so set the
1453 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1454 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1456 pwr |= SDHCI_POWER_ON;
1458 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1460 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1461 sdhci_runtime_pm_bus_on(host);
1464 * Some controllers need an extra 10ms delay of 10ms before
1465 * they can apply clock after applying power
1467 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1471 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1473 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1476 if (IS_ERR(host->mmc->supply.vmmc))
1477 sdhci_set_power_noreg(host, mode, vdd);
1479 sdhci_set_power_reg(host, mode, vdd);
1481 EXPORT_SYMBOL_GPL(sdhci_set_power);
1483 /*****************************************************************************\
1487 \*****************************************************************************/
1489 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1491 struct sdhci_host *host;
1493 unsigned long flags;
1495 host = mmc_priv(mmc);
1497 /* Firstly check card presence */
1498 present = mmc->ops->get_cd(mmc);
1500 spin_lock_irqsave(&host->lock, flags);
1502 sdhci_led_activate(host);
1505 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1506 * requests if Auto-CMD12 is enabled.
1508 if (sdhci_auto_cmd12(host, mrq)) {
1510 mrq->data->stop = NULL;
1515 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1516 mrq->cmd->error = -ENOMEDIUM;
1517 sdhci_finish_mrq(host, mrq);
1519 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1520 sdhci_send_command(host, mrq->sbc);
1522 sdhci_send_command(host, mrq->cmd);
1526 spin_unlock_irqrestore(&host->lock, flags);
1529 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1533 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1534 if (width == MMC_BUS_WIDTH_8) {
1535 ctrl &= ~SDHCI_CTRL_4BITBUS;
1536 if (host->version >= SDHCI_SPEC_300)
1537 ctrl |= SDHCI_CTRL_8BITBUS;
1539 if (host->version >= SDHCI_SPEC_300)
1540 ctrl &= ~SDHCI_CTRL_8BITBUS;
1541 if (width == MMC_BUS_WIDTH_4)
1542 ctrl |= SDHCI_CTRL_4BITBUS;
1544 ctrl &= ~SDHCI_CTRL_4BITBUS;
1546 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1548 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1550 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1554 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1555 /* Select Bus Speed Mode for host */
1556 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1557 if ((timing == MMC_TIMING_MMC_HS200) ||
1558 (timing == MMC_TIMING_UHS_SDR104))
1559 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1560 else if (timing == MMC_TIMING_UHS_SDR12)
1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1562 else if (timing == MMC_TIMING_UHS_SDR25)
1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1564 else if (timing == MMC_TIMING_UHS_SDR50)
1565 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1566 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1567 (timing == MMC_TIMING_MMC_DDR52))
1568 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1569 else if (timing == MMC_TIMING_MMC_HS400)
1570 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1571 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1573 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1575 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1577 struct sdhci_host *host = mmc_priv(mmc);
1578 unsigned long flags;
1581 if (ios->power_mode == MMC_POWER_UNDEFINED)
1584 spin_lock_irqsave(&host->lock, flags);
1586 if (host->flags & SDHCI_DEVICE_DEAD) {
1587 spin_unlock_irqrestore(&host->lock, flags);
1588 if (!IS_ERR(mmc->supply.vmmc) &&
1589 ios->power_mode == MMC_POWER_OFF)
1590 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1595 * Reset the chip on each power off.
1596 * Should clear out any weird states.
1598 if (ios->power_mode == MMC_POWER_OFF) {
1599 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1603 if (host->version >= SDHCI_SPEC_300 &&
1604 (ios->power_mode == MMC_POWER_UP) &&
1605 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1606 sdhci_enable_preset_value(host, false);
1608 if (!ios->clock || ios->clock != host->clock) {
1609 host->ops->set_clock(host, ios->clock);
1610 host->clock = ios->clock;
1612 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1614 host->timeout_clk = host->mmc->actual_clock ?
1615 host->mmc->actual_clock / 1000 :
1617 host->mmc->max_busy_timeout =
1618 host->ops->get_max_timeout_count ?
1619 host->ops->get_max_timeout_count(host) :
1621 host->mmc->max_busy_timeout /= host->timeout_clk;
1625 if (host->ops->set_power)
1626 host->ops->set_power(host, ios->power_mode, ios->vdd);
1628 sdhci_set_power(host, ios->power_mode, ios->vdd);
1630 if (host->ops->platform_send_init_74_clocks)
1631 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1633 host->ops->set_bus_width(host, ios->bus_width);
1635 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1637 if ((ios->timing == MMC_TIMING_SD_HS ||
1638 ios->timing == MMC_TIMING_MMC_HS ||
1639 ios->timing == MMC_TIMING_MMC_HS400 ||
1640 ios->timing == MMC_TIMING_MMC_HS200 ||
1641 ios->timing == MMC_TIMING_MMC_DDR52 ||
1642 ios->timing == MMC_TIMING_UHS_SDR50 ||
1643 ios->timing == MMC_TIMING_UHS_SDR104 ||
1644 ios->timing == MMC_TIMING_UHS_DDR50 ||
1645 ios->timing == MMC_TIMING_UHS_SDR25)
1646 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1647 ctrl |= SDHCI_CTRL_HISPD;
1649 ctrl &= ~SDHCI_CTRL_HISPD;
1651 if (host->version >= SDHCI_SPEC_300) {
1654 if (!host->preset_enabled) {
1655 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1657 * We only need to set Driver Strength if the
1658 * preset value enable is not set.
1660 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1661 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1662 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1663 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1664 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1665 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1666 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1667 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1668 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1669 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1671 pr_warn("%s: invalid driver type, default to driver type B\n",
1673 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1676 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1679 * According to SDHC Spec v3.00, if the Preset Value
1680 * Enable in the Host Control 2 register is set, we
1681 * need to reset SD Clock Enable before changing High
1682 * Speed Enable to avoid generating clock gliches.
1685 /* Reset SD Clock Enable */
1686 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1687 clk &= ~SDHCI_CLOCK_CARD_EN;
1688 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1690 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1692 /* Re-enable SD Clock */
1693 host->ops->set_clock(host, host->clock);
1696 /* Reset SD Clock Enable */
1697 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1698 clk &= ~SDHCI_CLOCK_CARD_EN;
1699 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1701 host->ops->set_uhs_signaling(host, ios->timing);
1702 host->timing = ios->timing;
1704 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1705 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1706 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1707 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1708 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1709 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1710 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1713 sdhci_enable_preset_value(host, true);
1714 preset = sdhci_get_preset_value(host);
1715 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1716 >> SDHCI_PRESET_DRV_SHIFT;
1719 /* Re-enable SD Clock */
1720 host->ops->set_clock(host, host->clock);
1722 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1725 * Some (ENE) controllers go apeshit on some ios operation,
1726 * signalling timeout and CRC errors even on CMD0. Resetting
1727 * it on each ios seems to solve the problem.
1729 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1730 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1733 spin_unlock_irqrestore(&host->lock, flags);
1736 static int sdhci_get_cd(struct mmc_host *mmc)
1738 struct sdhci_host *host = mmc_priv(mmc);
1739 int gpio_cd = mmc_gpio_get_cd(mmc);
1741 if (host->flags & SDHCI_DEVICE_DEAD)
1744 /* If nonremovable, assume that the card is always present. */
1745 if (!mmc_card_is_removable(host->mmc))
1749 * Try slot gpio detect, if defined it take precedence
1750 * over build in controller functionality
1755 /* If polling, assume that the card is always present. */
1756 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1759 /* Host native card detect */
1760 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1763 static int sdhci_check_ro(struct sdhci_host *host)
1765 unsigned long flags;
1768 spin_lock_irqsave(&host->lock, flags);
1770 if (host->flags & SDHCI_DEVICE_DEAD)
1772 else if (host->ops->get_ro)
1773 is_readonly = host->ops->get_ro(host);
1775 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1776 & SDHCI_WRITE_PROTECT);
1778 spin_unlock_irqrestore(&host->lock, flags);
1780 /* This quirk needs to be replaced by a callback-function later */
1781 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1782 !is_readonly : is_readonly;
1785 #define SAMPLE_COUNT 5
1787 static int sdhci_get_ro(struct mmc_host *mmc)
1789 struct sdhci_host *host = mmc_priv(mmc);
1792 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1793 return sdhci_check_ro(host);
1796 for (i = 0; i < SAMPLE_COUNT; i++) {
1797 if (sdhci_check_ro(host)) {
1798 if (++ro_count > SAMPLE_COUNT / 2)
1806 static void sdhci_hw_reset(struct mmc_host *mmc)
1808 struct sdhci_host *host = mmc_priv(mmc);
1810 if (host->ops && host->ops->hw_reset)
1811 host->ops->hw_reset(host);
1814 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1816 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1818 host->ier |= SDHCI_INT_CARD_INT;
1820 host->ier &= ~SDHCI_INT_CARD_INT;
1822 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1823 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1828 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1830 struct sdhci_host *host = mmc_priv(mmc);
1831 unsigned long flags;
1833 spin_lock_irqsave(&host->lock, flags);
1835 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1837 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1839 sdhci_enable_sdio_irq_nolock(host, enable);
1840 spin_unlock_irqrestore(&host->lock, flags);
1843 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1844 struct mmc_ios *ios)
1846 struct sdhci_host *host = mmc_priv(mmc);
1851 * Signal Voltage Switching is only applicable for Host Controllers
1854 if (host->version < SDHCI_SPEC_300)
1857 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1859 switch (ios->signal_voltage) {
1860 case MMC_SIGNAL_VOLTAGE_330:
1861 if (!(host->flags & SDHCI_SIGNALING_330))
1863 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1864 ctrl &= ~SDHCI_CTRL_VDD_180;
1865 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1867 if (!IS_ERR(mmc->supply.vqmmc)) {
1868 ret = mmc_regulator_set_vqmmc(mmc, ios);
1870 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1876 usleep_range(5000, 5500);
1878 /* 3.3V regulator output should be stable within 5 ms */
1879 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1880 if (!(ctrl & SDHCI_CTRL_VDD_180))
1883 pr_warn("%s: 3.3V regulator output did not became stable\n",
1887 case MMC_SIGNAL_VOLTAGE_180:
1888 if (!(host->flags & SDHCI_SIGNALING_180))
1890 if (!IS_ERR(mmc->supply.vqmmc)) {
1891 ret = mmc_regulator_set_vqmmc(mmc, ios);
1893 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1900 * Enable 1.8V Signal Enable in the Host Control2
1903 ctrl |= SDHCI_CTRL_VDD_180;
1904 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1906 /* Some controller need to do more when switching */
1907 if (host->ops->voltage_switch)
1908 host->ops->voltage_switch(host);
1910 /* 1.8V regulator output should be stable within 5 ms */
1911 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1912 if (ctrl & SDHCI_CTRL_VDD_180)
1915 pr_warn("%s: 1.8V regulator output did not became stable\n",
1919 case MMC_SIGNAL_VOLTAGE_120:
1920 if (!(host->flags & SDHCI_SIGNALING_120))
1922 if (!IS_ERR(mmc->supply.vqmmc)) {
1923 ret = mmc_regulator_set_vqmmc(mmc, ios);
1925 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1932 /* No signal voltage switch required */
1937 static int sdhci_card_busy(struct mmc_host *mmc)
1939 struct sdhci_host *host = mmc_priv(mmc);
1942 /* Check whether DAT[0] is 0 */
1943 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1945 return !(present_state & SDHCI_DATA_0_LVL_MASK);
1948 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1950 struct sdhci_host *host = mmc_priv(mmc);
1951 unsigned long flags;
1953 spin_lock_irqsave(&host->lock, flags);
1954 host->flags |= SDHCI_HS400_TUNING;
1955 spin_unlock_irqrestore(&host->lock, flags);
1960 static void sdhci_start_tuning(struct sdhci_host *host)
1964 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1965 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1966 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1967 ctrl |= SDHCI_CTRL_TUNED_CLK;
1968 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1971 * As per the Host Controller spec v3.00, tuning command
1972 * generates Buffer Read Ready interrupt, so enable that.
1974 * Note: The spec clearly says that when tuning sequence
1975 * is being performed, the controller does not generate
1976 * interrupts other than Buffer Read Ready interrupt. But
1977 * to make sure we don't hit a controller bug, we _only_
1978 * enable Buffer Read Ready interrupt here.
1980 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1981 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1984 static void sdhci_end_tuning(struct sdhci_host *host)
1986 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1987 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1990 static void sdhci_reset_tuning(struct sdhci_host *host)
1994 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1995 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1996 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1997 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2000 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode,
2001 unsigned long flags)
2003 sdhci_reset_tuning(host);
2005 sdhci_do_reset(host, SDHCI_RESET_CMD);
2006 sdhci_do_reset(host, SDHCI_RESET_DATA);
2008 sdhci_end_tuning(host);
2010 spin_unlock_irqrestore(&host->lock, flags);
2011 mmc_abort_tuning(host->mmc, opcode);
2012 spin_lock_irqsave(&host->lock, flags);
2016 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2017 * tuning command does not have a data payload (or rather the hardware does it
2018 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2019 * interrupt setup is different to other commands and there is no timeout
2020 * interrupt so special handling is needed.
2022 static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode,
2023 unsigned long flags)
2025 struct mmc_host *mmc = host->mmc;
2026 struct mmc_command cmd = {};
2027 struct mmc_request mrq = {};
2029 cmd.opcode = opcode;
2030 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2035 * In response to CMD19, the card sends 64 bytes of tuning
2036 * block to the Host Controller. So we set the block size
2039 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2040 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2041 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
2043 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
2046 * The tuning block is sent by the card to the host controller.
2047 * So we set the TRNS_READ bit in the Transfer Mode register.
2048 * This also takes care of setting DMA Enable and Multi Block
2049 * Select in the same register to 0.
2051 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2053 sdhci_send_command(host, &cmd);
2057 sdhci_del_timer(host, &mrq);
2059 host->tuning_done = 0;
2061 spin_unlock_irqrestore(&host->lock, flags);
2063 /* Wait for Buffer Read Ready interrupt */
2064 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2065 msecs_to_jiffies(50));
2067 spin_lock_irqsave(&host->lock, flags);
2070 static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode,
2071 unsigned long flags)
2076 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2077 * of loops reaches 40 times.
2079 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2082 sdhci_send_tuning(host, opcode, flags);
2084 if (!host->tuning_done) {
2085 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2086 mmc_hostname(host->mmc));
2087 sdhci_abort_tuning(host, opcode, flags);
2091 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2092 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2093 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2094 return; /* Success! */
2098 /* eMMC spec does not require a delay between tuning cycles */
2099 if (opcode == MMC_SEND_TUNING_BLOCK)
2103 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2104 mmc_hostname(host->mmc));
2105 sdhci_reset_tuning(host);
2108 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2110 struct sdhci_host *host = mmc_priv(mmc);
2112 unsigned long flags;
2113 unsigned int tuning_count = 0;
2116 spin_lock_irqsave(&host->lock, flags);
2118 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2120 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2121 tuning_count = host->tuning_count;
2124 * The Host Controller needs tuning in case of SDR104 and DDR50
2125 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2126 * the Capabilities register.
2127 * If the Host Controller supports the HS200 mode then the
2128 * tuning function has to be executed.
2130 switch (host->timing) {
2131 /* HS400 tuning is done in HS200 mode */
2132 case MMC_TIMING_MMC_HS400:
2136 case MMC_TIMING_MMC_HS200:
2138 * Periodic re-tuning for HS400 is not expected to be needed, so
2145 case MMC_TIMING_UHS_SDR104:
2146 case MMC_TIMING_UHS_DDR50:
2149 case MMC_TIMING_UHS_SDR50:
2150 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2158 if (host->ops->platform_execute_tuning) {
2159 spin_unlock_irqrestore(&host->lock, flags);
2160 err = host->ops->platform_execute_tuning(host, opcode);
2161 spin_lock_irqsave(&host->lock, flags);
2165 host->mmc->retune_period = tuning_count;
2167 sdhci_start_tuning(host);
2169 __sdhci_execute_tuning(host, opcode, flags);
2171 sdhci_end_tuning(host);
2173 host->flags &= ~SDHCI_HS400_TUNING;
2174 spin_unlock_irqrestore(&host->lock, flags);
2178 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2180 static int sdhci_select_drive_strength(struct mmc_card *card,
2181 unsigned int max_dtr, int host_drv,
2182 int card_drv, int *drv_type)
2184 struct sdhci_host *host = mmc_priv(card->host);
2186 if (!host->ops->select_drive_strength)
2189 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2190 card_drv, drv_type);
2193 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2195 /* Host Controller v3.00 defines preset value registers */
2196 if (host->version < SDHCI_SPEC_300)
2200 * We only enable or disable Preset Value if they are not already
2201 * enabled or disabled respectively. Otherwise, we bail out.
2203 if (host->preset_enabled != enable) {
2204 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2207 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2209 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2211 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2214 host->flags |= SDHCI_PV_ENABLED;
2216 host->flags &= ~SDHCI_PV_ENABLED;
2218 host->preset_enabled = enable;
2222 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2225 struct sdhci_host *host = mmc_priv(mmc);
2226 struct mmc_data *data = mrq->data;
2228 if (data->host_cookie != COOKIE_UNMAPPED)
2229 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2230 data->flags & MMC_DATA_WRITE ?
2231 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2233 data->host_cookie = COOKIE_UNMAPPED;
2236 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2238 struct sdhci_host *host = mmc_priv(mmc);
2240 mrq->data->host_cookie = COOKIE_UNMAPPED;
2242 if (host->flags & SDHCI_REQ_USE_DMA)
2243 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2246 static inline bool sdhci_has_requests(struct sdhci_host *host)
2248 return host->cmd || host->data_cmd;
2251 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2253 if (host->data_cmd) {
2254 host->data_cmd->error = err;
2255 sdhci_finish_mrq(host, host->data_cmd->mrq);
2259 host->cmd->error = err;
2260 sdhci_finish_mrq(host, host->cmd->mrq);
2264 static void sdhci_card_event(struct mmc_host *mmc)
2266 struct sdhci_host *host = mmc_priv(mmc);
2267 unsigned long flags;
2270 /* First check if client has provided their own card event */
2271 if (host->ops->card_event)
2272 host->ops->card_event(host);
2274 present = mmc->ops->get_cd(mmc);
2276 spin_lock_irqsave(&host->lock, flags);
2278 /* Check sdhci_has_requests() first in case we are runtime suspended */
2279 if (sdhci_has_requests(host) && !present) {
2280 pr_err("%s: Card removed during transfer!\n",
2281 mmc_hostname(host->mmc));
2282 pr_err("%s: Resetting controller.\n",
2283 mmc_hostname(host->mmc));
2285 sdhci_do_reset(host, SDHCI_RESET_CMD);
2286 sdhci_do_reset(host, SDHCI_RESET_DATA);
2288 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2291 spin_unlock_irqrestore(&host->lock, flags);
2294 static const struct mmc_host_ops sdhci_ops = {
2295 .request = sdhci_request,
2296 .post_req = sdhci_post_req,
2297 .pre_req = sdhci_pre_req,
2298 .set_ios = sdhci_set_ios,
2299 .get_cd = sdhci_get_cd,
2300 .get_ro = sdhci_get_ro,
2301 .hw_reset = sdhci_hw_reset,
2302 .enable_sdio_irq = sdhci_enable_sdio_irq,
2303 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2304 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2305 .execute_tuning = sdhci_execute_tuning,
2306 .select_drive_strength = sdhci_select_drive_strength,
2307 .card_event = sdhci_card_event,
2308 .card_busy = sdhci_card_busy,
2311 /*****************************************************************************\
2315 \*****************************************************************************/
2317 static bool sdhci_request_done(struct sdhci_host *host)
2319 unsigned long flags;
2320 struct mmc_request *mrq;
2323 spin_lock_irqsave(&host->lock, flags);
2325 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2326 mrq = host->mrqs_done[i];
2332 spin_unlock_irqrestore(&host->lock, flags);
2336 sdhci_del_timer(host, mrq);
2339 * Always unmap the data buffers if they were mapped by
2340 * sdhci_prepare_data() whenever we finish with a request.
2341 * This avoids leaking DMA mappings on error.
2343 if (host->flags & SDHCI_REQ_USE_DMA) {
2344 struct mmc_data *data = mrq->data;
2346 if (data && data->host_cookie == COOKIE_MAPPED) {
2347 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2348 (data->flags & MMC_DATA_READ) ?
2349 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2350 data->host_cookie = COOKIE_UNMAPPED;
2355 * The controller needs a reset of internal state machines
2356 * upon error conditions.
2358 if (sdhci_needs_reset(host, mrq)) {
2360 * Do not finish until command and data lines are available for
2361 * reset. Note there can only be one other mrq, so it cannot
2362 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2363 * would both be null.
2365 if (host->cmd || host->data_cmd) {
2366 spin_unlock_irqrestore(&host->lock, flags);
2370 /* Some controllers need this kick or reset won't work here */
2371 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2372 /* This is to force an update */
2373 host->ops->set_clock(host, host->clock);
2375 /* Spec says we should do both at the same time, but Ricoh
2376 controllers do not like that. */
2377 sdhci_do_reset(host, SDHCI_RESET_CMD);
2378 sdhci_do_reset(host, SDHCI_RESET_DATA);
2380 host->pending_reset = false;
2383 if (!sdhci_has_requests(host))
2384 sdhci_led_deactivate(host);
2386 host->mrqs_done[i] = NULL;
2389 spin_unlock_irqrestore(&host->lock, flags);
2391 mmc_request_done(host->mmc, mrq);
2396 static void sdhci_tasklet_finish(unsigned long param)
2398 struct sdhci_host *host = (struct sdhci_host *)param;
2400 while (!sdhci_request_done(host))
2404 static void sdhci_timeout_timer(unsigned long data)
2406 struct sdhci_host *host;
2407 unsigned long flags;
2409 host = (struct sdhci_host*)data;
2411 spin_lock_irqsave(&host->lock, flags);
2413 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2414 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2415 mmc_hostname(host->mmc));
2416 sdhci_dumpregs(host);
2418 host->cmd->error = -ETIMEDOUT;
2419 sdhci_finish_mrq(host, host->cmd->mrq);
2423 spin_unlock_irqrestore(&host->lock, flags);
2426 static void sdhci_timeout_data_timer(unsigned long data)
2428 struct sdhci_host *host;
2429 unsigned long flags;
2431 host = (struct sdhci_host *)data;
2433 spin_lock_irqsave(&host->lock, flags);
2435 if (host->data || host->data_cmd ||
2436 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2437 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2438 mmc_hostname(host->mmc));
2439 sdhci_dumpregs(host);
2442 host->data->error = -ETIMEDOUT;
2443 sdhci_finish_data(host);
2444 } else if (host->data_cmd) {
2445 host->data_cmd->error = -ETIMEDOUT;
2446 sdhci_finish_mrq(host, host->data_cmd->mrq);
2448 host->cmd->error = -ETIMEDOUT;
2449 sdhci_finish_mrq(host, host->cmd->mrq);
2454 spin_unlock_irqrestore(&host->lock, flags);
2457 /*****************************************************************************\
2459 * Interrupt handling *
2461 \*****************************************************************************/
2463 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2467 * SDHCI recovers from errors by resetting the cmd and data
2468 * circuits. Until that is done, there very well might be more
2469 * interrupts, so ignore them in that case.
2471 if (host->pending_reset)
2473 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2474 mmc_hostname(host->mmc), (unsigned)intmask);
2475 sdhci_dumpregs(host);
2479 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2480 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2481 if (intmask & SDHCI_INT_TIMEOUT)
2482 host->cmd->error = -ETIMEDOUT;
2484 host->cmd->error = -EILSEQ;
2487 * If this command initiates a data phase and a response
2488 * CRC error is signalled, the card can start transferring
2489 * data - the card may have received the command without
2490 * error. We must not terminate the mmc_request early.
2492 * If the card did not receive the command or returned an
2493 * error which prevented it sending data, the data phase
2496 if (host->cmd->data &&
2497 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2503 sdhci_finish_mrq(host, host->cmd->mrq);
2507 if (intmask & SDHCI_INT_RESPONSE)
2508 sdhci_finish_command(host);
2511 #ifdef CONFIG_MMC_DEBUG
2512 static void sdhci_adma_show_error(struct sdhci_host *host)
2514 const char *name = mmc_hostname(host->mmc);
2515 void *desc = host->adma_table;
2517 sdhci_dumpregs(host);
2520 struct sdhci_adma2_64_desc *dma_desc = desc;
2522 if (host->flags & SDHCI_USE_64_BIT_DMA)
2523 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2524 name, desc, le32_to_cpu(dma_desc->addr_hi),
2525 le32_to_cpu(dma_desc->addr_lo),
2526 le16_to_cpu(dma_desc->len),
2527 le16_to_cpu(dma_desc->cmd));
2529 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2530 name, desc, le32_to_cpu(dma_desc->addr_lo),
2531 le16_to_cpu(dma_desc->len),
2532 le16_to_cpu(dma_desc->cmd));
2534 desc += host->desc_sz;
2536 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2541 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2544 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2548 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2549 if (intmask & SDHCI_INT_DATA_AVAIL) {
2550 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2551 if (command == MMC_SEND_TUNING_BLOCK ||
2552 command == MMC_SEND_TUNING_BLOCK_HS200) {
2553 host->tuning_done = 1;
2554 wake_up(&host->buf_ready_int);
2560 struct mmc_command *data_cmd = host->data_cmd;
2563 * The "data complete" interrupt is also used to
2564 * indicate that a busy state has ended. See comment
2565 * above in sdhci_cmd_irq().
2567 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2568 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2569 host->data_cmd = NULL;
2570 data_cmd->error = -ETIMEDOUT;
2571 sdhci_finish_mrq(host, data_cmd->mrq);
2574 if (intmask & SDHCI_INT_DATA_END) {
2575 host->data_cmd = NULL;
2577 * Some cards handle busy-end interrupt
2578 * before the command completed, so make
2579 * sure we do things in the proper order.
2581 if (host->cmd == data_cmd)
2584 sdhci_finish_mrq(host, data_cmd->mrq);
2590 * SDHCI recovers from errors by resetting the cmd and data
2591 * circuits. Until that is done, there very well might be more
2592 * interrupts, so ignore them in that case.
2594 if (host->pending_reset)
2597 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2598 mmc_hostname(host->mmc), (unsigned)intmask);
2599 sdhci_dumpregs(host);
2604 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2605 host->data->error = -ETIMEDOUT;
2606 else if (intmask & SDHCI_INT_DATA_END_BIT)
2607 host->data->error = -EILSEQ;
2608 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2609 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2611 host->data->error = -EILSEQ;
2612 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2613 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2614 sdhci_adma_show_error(host);
2615 host->data->error = -EIO;
2616 if (host->ops->adma_workaround)
2617 host->ops->adma_workaround(host, intmask);
2620 if (host->data->error)
2621 sdhci_finish_data(host);
2623 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2624 sdhci_transfer_pio(host);
2627 * We currently don't do anything fancy with DMA
2628 * boundaries, but as we can't disable the feature
2629 * we need to at least restart the transfer.
2631 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2632 * should return a valid address to continue from, but as
2633 * some controllers are faulty, don't trust them.
2635 if (intmask & SDHCI_INT_DMA_END) {
2636 u32 dmastart, dmanow;
2637 dmastart = sg_dma_address(host->data->sg);
2638 dmanow = dmastart + host->data->bytes_xfered;
2640 * Force update to the next DMA block boundary.
2643 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2644 SDHCI_DEFAULT_BOUNDARY_SIZE;
2645 host->data->bytes_xfered = dmanow - dmastart;
2646 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2648 mmc_hostname(host->mmc), dmastart,
2649 host->data->bytes_xfered, dmanow);
2650 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2653 if (intmask & SDHCI_INT_DATA_END) {
2654 if (host->cmd == host->data_cmd) {
2656 * Data managed to finish before the
2657 * command completed. Make sure we do
2658 * things in the proper order.
2660 host->data_early = 1;
2662 sdhci_finish_data(host);
2668 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2670 irqreturn_t result = IRQ_NONE;
2671 struct sdhci_host *host = dev_id;
2672 u32 intmask, mask, unexpected = 0;
2675 spin_lock(&host->lock);
2677 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2678 spin_unlock(&host->lock);
2682 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2683 if (!intmask || intmask == 0xffffffff) {
2689 /* Clear selected interrupts. */
2690 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2691 SDHCI_INT_BUS_POWER);
2692 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2694 DBG("*** %s got interrupt: 0x%08x\n",
2695 mmc_hostname(host->mmc), intmask);
2697 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2698 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2702 * There is a observation on i.mx esdhc. INSERT
2703 * bit will be immediately set again when it gets
2704 * cleared, if a card is inserted. We have to mask
2705 * the irq to prevent interrupt storm which will
2706 * freeze the system. And the REMOVE gets the
2709 * More testing are needed here to ensure it works
2710 * for other platforms though.
2712 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2713 SDHCI_INT_CARD_REMOVE);
2714 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2715 SDHCI_INT_CARD_INSERT;
2716 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2717 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2719 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2720 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2722 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2723 SDHCI_INT_CARD_REMOVE);
2724 result = IRQ_WAKE_THREAD;
2727 if (intmask & SDHCI_INT_CMD_MASK)
2728 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2730 if (intmask & SDHCI_INT_DATA_MASK)
2731 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2733 if (intmask & SDHCI_INT_BUS_POWER)
2734 pr_err("%s: Card is consuming too much power!\n",
2735 mmc_hostname(host->mmc));
2737 if (intmask & SDHCI_INT_RETUNE)
2738 mmc_retune_needed(host->mmc);
2740 if ((intmask & SDHCI_INT_CARD_INT) &&
2741 (host->ier & SDHCI_INT_CARD_INT)) {
2742 sdhci_enable_sdio_irq_nolock(host, false);
2743 host->thread_isr |= SDHCI_INT_CARD_INT;
2744 result = IRQ_WAKE_THREAD;
2747 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2748 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2749 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2750 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
2753 unexpected |= intmask;
2754 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2757 if (result == IRQ_NONE)
2758 result = IRQ_HANDLED;
2760 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2761 } while (intmask && --max_loops);
2763 spin_unlock(&host->lock);
2766 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2767 mmc_hostname(host->mmc), unexpected);
2768 sdhci_dumpregs(host);
2774 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2776 struct sdhci_host *host = dev_id;
2777 unsigned long flags;
2780 spin_lock_irqsave(&host->lock, flags);
2781 isr = host->thread_isr;
2782 host->thread_isr = 0;
2783 spin_unlock_irqrestore(&host->lock, flags);
2785 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2786 struct mmc_host *mmc = host->mmc;
2788 mmc->ops->card_event(mmc);
2789 mmc_detect_change(mmc, msecs_to_jiffies(200));
2792 if (isr & SDHCI_INT_CARD_INT) {
2793 sdio_run_irqs(host->mmc);
2795 spin_lock_irqsave(&host->lock, flags);
2796 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2797 sdhci_enable_sdio_irq_nolock(host, true);
2798 spin_unlock_irqrestore(&host->lock, flags);
2801 return isr ? IRQ_HANDLED : IRQ_NONE;
2804 /*****************************************************************************\
2808 \*****************************************************************************/
2812 * To enable wakeup events, the corresponding events have to be enabled in
2813 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2814 * Table' in the SD Host Controller Standard Specification.
2815 * It is useless to restore SDHCI_INT_ENABLE state in
2816 * sdhci_disable_irq_wakeups() since it will be set by
2817 * sdhci_enable_card_detection() or sdhci_init().
2819 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2822 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2823 | SDHCI_WAKE_ON_INT;
2824 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2827 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2829 /* Avoid fake wake up */
2830 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
2831 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2832 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2834 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2835 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
2837 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2839 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2842 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2843 | SDHCI_WAKE_ON_INT;
2845 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2847 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2850 int sdhci_suspend_host(struct sdhci_host *host)
2852 sdhci_disable_card_detection(host);
2854 mmc_retune_timer_stop(host->mmc);
2855 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2856 mmc_retune_needed(host->mmc);
2858 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2860 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2861 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2862 free_irq(host->irq, host);
2864 sdhci_enable_irq_wakeups(host);
2865 enable_irq_wake(host->irq);
2870 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2872 int sdhci_resume_host(struct sdhci_host *host)
2874 struct mmc_host *mmc = host->mmc;
2877 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2878 if (host->ops->enable_dma)
2879 host->ops->enable_dma(host);
2882 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2883 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2884 /* Card keeps power but host controller does not */
2885 sdhci_init(host, 0);
2888 mmc->ops->set_ios(mmc, &mmc->ios);
2890 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2894 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2895 ret = request_threaded_irq(host->irq, sdhci_irq,
2896 sdhci_thread_irq, IRQF_SHARED,
2897 mmc_hostname(host->mmc), host);
2901 sdhci_disable_irq_wakeups(host);
2902 disable_irq_wake(host->irq);
2905 sdhci_enable_card_detection(host);
2910 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2912 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2914 unsigned long flags;
2916 mmc_retune_timer_stop(host->mmc);
2917 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2918 mmc_retune_needed(host->mmc);
2920 spin_lock_irqsave(&host->lock, flags);
2921 host->ier &= SDHCI_INT_CARD_INT;
2922 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2923 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2924 spin_unlock_irqrestore(&host->lock, flags);
2926 synchronize_hardirq(host->irq);
2928 spin_lock_irqsave(&host->lock, flags);
2929 host->runtime_suspended = true;
2930 spin_unlock_irqrestore(&host->lock, flags);
2934 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2936 int sdhci_runtime_resume_host(struct sdhci_host *host)
2938 struct mmc_host *mmc = host->mmc;
2939 unsigned long flags;
2940 int host_flags = host->flags;
2942 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2943 if (host->ops->enable_dma)
2944 host->ops->enable_dma(host);
2947 sdhci_init(host, 0);
2949 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED) {
2950 /* Force clock and power re-program */
2953 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2954 mmc->ops->set_ios(mmc, &mmc->ios);
2956 if ((host_flags & SDHCI_PV_ENABLED) &&
2957 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2958 spin_lock_irqsave(&host->lock, flags);
2959 sdhci_enable_preset_value(host, true);
2960 spin_unlock_irqrestore(&host->lock, flags);
2963 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
2964 mmc->ops->hs400_enhanced_strobe)
2965 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
2968 spin_lock_irqsave(&host->lock, flags);
2970 host->runtime_suspended = false;
2972 /* Enable SDIO IRQ */
2973 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2974 sdhci_enable_sdio_irq_nolock(host, true);
2976 /* Enable Card Detection */
2977 sdhci_enable_card_detection(host);
2979 spin_unlock_irqrestore(&host->lock, flags);
2983 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2985 #endif /* CONFIG_PM */
2987 /*****************************************************************************\
2989 * Device allocation/registration *
2991 \*****************************************************************************/
2993 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2996 struct mmc_host *mmc;
2997 struct sdhci_host *host;
2999 WARN_ON(dev == NULL);
3001 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3003 return ERR_PTR(-ENOMEM);
3005 host = mmc_priv(mmc);
3007 host->mmc_host_ops = sdhci_ops;
3008 mmc->ops = &host->mmc_host_ops;
3010 host->flags = SDHCI_SIGNALING_330;
3015 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3017 static int sdhci_set_dma_mask(struct sdhci_host *host)
3019 struct mmc_host *mmc = host->mmc;
3020 struct device *dev = mmc_dev(mmc);
3023 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3024 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3026 /* Try 64-bit mask if hardware is capable of it */
3027 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3028 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3030 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3032 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3036 /* 32-bit mask as default & fallback */
3038 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3040 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3047 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3050 u64 dt_caps_mask = 0;
3053 if (host->read_caps)
3056 host->read_caps = true;
3059 host->quirks = debug_quirks;
3062 host->quirks2 = debug_quirks2;
3064 sdhci_do_reset(host, SDHCI_RESET_ALL);
3066 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3067 "sdhci-caps-mask", &dt_caps_mask);
3068 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3069 "sdhci-caps", &dt_caps);
3071 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3072 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3074 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3080 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3081 host->caps &= ~lower_32_bits(dt_caps_mask);
3082 host->caps |= lower_32_bits(dt_caps);
3085 if (host->version < SDHCI_SPEC_300)
3089 host->caps1 = *caps1;
3091 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3092 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3093 host->caps1 |= upper_32_bits(dt_caps);
3096 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3098 int sdhci_setup_host(struct sdhci_host *host)
3100 struct mmc_host *mmc;
3101 u32 max_current_caps;
3102 unsigned int ocr_avail;
3103 unsigned int override_timeout_clk;
3107 WARN_ON(host == NULL);
3114 * If there are external regulators, get them. Note this must be done
3115 * early before resetting the host and reading the capabilities so that
3116 * the host can take the appropriate action if regulators are not
3119 ret = mmc_regulator_get_supply(mmc);
3120 if (ret == -EPROBE_DEFER)
3123 sdhci_read_caps(host);
3125 override_timeout_clk = host->timeout_clk;
3127 if (host->version > SDHCI_SPEC_300) {
3128 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3129 mmc_hostname(mmc), host->version);
3132 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3133 host->flags |= SDHCI_USE_SDMA;
3134 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3135 DBG("Controller doesn't have SDMA capability\n");
3137 host->flags |= SDHCI_USE_SDMA;
3139 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3140 (host->flags & SDHCI_USE_SDMA)) {
3141 DBG("Disabling DMA as it is marked broken\n");
3142 host->flags &= ~SDHCI_USE_SDMA;
3145 if ((host->version >= SDHCI_SPEC_200) &&
3146 (host->caps & SDHCI_CAN_DO_ADMA2))
3147 host->flags |= SDHCI_USE_ADMA;
3149 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3150 (host->flags & SDHCI_USE_ADMA)) {
3151 DBG("Disabling ADMA as it is marked broken\n");
3152 host->flags &= ~SDHCI_USE_ADMA;
3156 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3157 * and *must* do 64-bit DMA. A driver has the opportunity to change
3158 * that during the first call to ->enable_dma(). Similarly
3159 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3162 if (host->caps & SDHCI_CAN_64BIT)
3163 host->flags |= SDHCI_USE_64_BIT_DMA;
3165 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3166 ret = sdhci_set_dma_mask(host);
3168 if (!ret && host->ops->enable_dma)
3169 ret = host->ops->enable_dma(host);
3172 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3174 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3180 /* SDMA does not support 64-bit DMA */
3181 if (host->flags & SDHCI_USE_64_BIT_DMA)
3182 host->flags &= ~SDHCI_USE_SDMA;
3184 if (host->flags & SDHCI_USE_ADMA) {
3189 * The DMA descriptor table size is calculated as the maximum
3190 * number of segments times 2, to allow for an alignment
3191 * descriptor for each segment, plus 1 for a nop end descriptor,
3192 * all multipled by the descriptor size.
3194 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3195 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3196 SDHCI_ADMA2_64_DESC_SZ;
3197 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3199 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3200 SDHCI_ADMA2_32_DESC_SZ;
3201 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3204 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3205 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3206 host->adma_table_sz, &dma, GFP_KERNEL);
3208 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3210 host->flags &= ~SDHCI_USE_ADMA;
3211 } else if ((dma + host->align_buffer_sz) &
3212 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3213 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3215 host->flags &= ~SDHCI_USE_ADMA;
3216 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3217 host->adma_table_sz, buf, dma);
3219 host->align_buffer = buf;
3220 host->align_addr = dma;
3222 host->adma_table = buf + host->align_buffer_sz;
3223 host->adma_addr = dma + host->align_buffer_sz;
3228 * If we use DMA, then it's up to the caller to set the DMA
3229 * mask, but PIO does not need the hw shim so we set a new
3230 * mask here in that case.
3232 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3233 host->dma_mask = DMA_BIT_MASK(64);
3234 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3237 if (host->version >= SDHCI_SPEC_300)
3238 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3239 >> SDHCI_CLOCK_BASE_SHIFT;
3241 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3242 >> SDHCI_CLOCK_BASE_SHIFT;
3244 host->max_clk *= 1000000;
3245 if (host->max_clk == 0 || host->quirks &
3246 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3247 if (!host->ops->get_max_clock) {
3248 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3253 host->max_clk = host->ops->get_max_clock(host);
3257 * In case of Host Controller v3.00, find out whether clock
3258 * multiplier is supported.
3260 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3261 SDHCI_CLOCK_MUL_SHIFT;
3264 * In case the value in Clock Multiplier is 0, then programmable
3265 * clock mode is not supported, otherwise the actual clock
3266 * multiplier is one more than the value of Clock Multiplier
3267 * in the Capabilities Register.
3273 * Set host parameters.
3275 max_clk = host->max_clk;
3277 if (host->ops->get_min_clock)
3278 mmc->f_min = host->ops->get_min_clock(host);
3279 else if (host->version >= SDHCI_SPEC_300) {
3280 if (host->clk_mul) {
3281 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3282 max_clk = host->max_clk * host->clk_mul;
3284 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3286 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3288 if (!mmc->f_max || mmc->f_max > max_clk)
3289 mmc->f_max = max_clk;
3291 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3292 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3293 SDHCI_TIMEOUT_CLK_SHIFT;
3294 if (host->timeout_clk == 0) {
3295 if (host->ops->get_timeout_clock) {
3297 host->ops->get_timeout_clock(host);
3299 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3306 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3307 host->timeout_clk *= 1000;
3309 if (override_timeout_clk)
3310 host->timeout_clk = override_timeout_clk;
3312 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3313 host->ops->get_max_timeout_count(host) : 1 << 27;
3314 mmc->max_busy_timeout /= host->timeout_clk;
3317 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3318 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3320 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3321 host->flags |= SDHCI_AUTO_CMD12;
3323 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3324 if ((host->version >= SDHCI_SPEC_300) &&
3325 ((host->flags & SDHCI_USE_ADMA) ||
3326 !(host->flags & SDHCI_USE_SDMA)) &&
3327 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3328 host->flags |= SDHCI_AUTO_CMD23;
3329 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3331 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3335 * A controller may support 8-bit width, but the board itself
3336 * might not have the pins brought out. Boards that support
3337 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3338 * their platform code before calling sdhci_add_host(), and we
3339 * won't assume 8-bit width for hosts without that CAP.
3341 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3342 mmc->caps |= MMC_CAP_4_BIT_DATA;
3344 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3345 mmc->caps &= ~MMC_CAP_CMD23;
3347 if (host->caps & SDHCI_CAN_DO_HISPD)
3348 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3350 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3351 mmc_card_is_removable(mmc) &&
3352 mmc_gpio_get_cd(host->mmc) < 0)
3353 mmc->caps |= MMC_CAP_NEEDS_POLL;
3355 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3356 if (!IS_ERR(mmc->supply.vqmmc)) {
3357 ret = regulator_enable(mmc->supply.vqmmc);
3358 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3360 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3361 SDHCI_SUPPORT_SDR50 |
3362 SDHCI_SUPPORT_DDR50);
3364 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3365 mmc_hostname(mmc), ret);
3366 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3370 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3371 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3372 SDHCI_SUPPORT_DDR50);
3375 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3376 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3377 SDHCI_SUPPORT_DDR50))
3378 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3380 /* SDR104 supports also implies SDR50 support */
3381 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
3382 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3383 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3384 * field can be promoted to support HS200.
3386 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3387 mmc->caps2 |= MMC_CAP2_HS200;
3388 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
3389 mmc->caps |= MMC_CAP_UHS_SDR50;
3392 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3393 (host->caps1 & SDHCI_SUPPORT_HS400))
3394 mmc->caps2 |= MMC_CAP2_HS400;
3396 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3397 (IS_ERR(mmc->supply.vqmmc) ||
3398 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3400 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3402 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3403 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3404 mmc->caps |= MMC_CAP_UHS_DDR50;
3406 /* Does the host need tuning for SDR50? */
3407 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
3408 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3410 /* Driver Type(s) (A, C, D) supported by the host */
3411 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
3412 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3413 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
3414 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3415 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
3416 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3418 /* Initial value for re-tuning timer count */
3419 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3420 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3423 * In case Re-tuning Timer is not disabled, the actual value of
3424 * re-tuning timer will be 2 ^ (n - 1).
3426 if (host->tuning_count)
3427 host->tuning_count = 1 << (host->tuning_count - 1);
3429 /* Re-tuning mode supported by the Host Controller */
3430 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3431 SDHCI_RETUNING_MODE_SHIFT;
3436 * According to SD Host Controller spec v3.00, if the Host System
3437 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3438 * the value is meaningful only if Voltage Support in the Capabilities
3439 * register is set. The actual current value is 4 times the register
3442 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3443 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3444 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3447 /* convert to SDHCI_MAX_CURRENT format */
3448 curr = curr/1000; /* convert to mA */
3449 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3451 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3453 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3454 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3455 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3459 if (host->caps & SDHCI_CAN_VDD_330) {
3460 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3462 mmc->max_current_330 = ((max_current_caps &
3463 SDHCI_MAX_CURRENT_330_MASK) >>
3464 SDHCI_MAX_CURRENT_330_SHIFT) *
3465 SDHCI_MAX_CURRENT_MULTIPLIER;
3467 if (host->caps & SDHCI_CAN_VDD_300) {
3468 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3470 mmc->max_current_300 = ((max_current_caps &
3471 SDHCI_MAX_CURRENT_300_MASK) >>
3472 SDHCI_MAX_CURRENT_300_SHIFT) *
3473 SDHCI_MAX_CURRENT_MULTIPLIER;
3475 if (host->caps & SDHCI_CAN_VDD_180) {
3476 ocr_avail |= MMC_VDD_165_195;
3478 mmc->max_current_180 = ((max_current_caps &
3479 SDHCI_MAX_CURRENT_180_MASK) >>
3480 SDHCI_MAX_CURRENT_180_SHIFT) *
3481 SDHCI_MAX_CURRENT_MULTIPLIER;
3484 /* If OCR set by host, use it instead. */
3486 ocr_avail = host->ocr_mask;
3488 /* If OCR set by external regulators, give it highest prio. */
3490 ocr_avail = mmc->ocr_avail;
3492 mmc->ocr_avail = ocr_avail;
3493 mmc->ocr_avail_sdio = ocr_avail;
3494 if (host->ocr_avail_sdio)
3495 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3496 mmc->ocr_avail_sd = ocr_avail;
3497 if (host->ocr_avail_sd)
3498 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3499 else /* normal SD controllers don't support 1.8V */
3500 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3501 mmc->ocr_avail_mmc = ocr_avail;
3502 if (host->ocr_avail_mmc)
3503 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3505 if (mmc->ocr_avail == 0) {
3506 pr_err("%s: Hardware doesn't report any support voltages.\n",
3512 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3513 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3514 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3515 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3516 host->flags |= SDHCI_SIGNALING_180;
3518 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3519 host->flags |= SDHCI_SIGNALING_120;
3521 spin_lock_init(&host->lock);
3524 * Maximum number of segments. Depends on if the hardware
3525 * can do scatter/gather or not.
3527 if (host->flags & SDHCI_USE_ADMA)
3528 mmc->max_segs = SDHCI_MAX_SEGS;
3529 else if (host->flags & SDHCI_USE_SDMA)
3532 mmc->max_segs = SDHCI_MAX_SEGS;
3535 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3536 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3539 mmc->max_req_size = 524288;
3542 * Maximum segment size. Could be one segment with the maximum number
3543 * of bytes. When doing hardware scatter/gather, each entry cannot
3544 * be larger than 64 KiB though.
3546 if (host->flags & SDHCI_USE_ADMA) {
3547 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3548 mmc->max_seg_size = 65535;
3550 mmc->max_seg_size = 65536;
3552 mmc->max_seg_size = mmc->max_req_size;
3556 * Maximum block size. This varies from controller to controller and
3557 * is specified in the capabilities register.
3559 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3560 mmc->max_blk_size = 2;
3562 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
3563 SDHCI_MAX_BLOCK_SHIFT;
3564 if (mmc->max_blk_size >= 3) {
3565 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3567 mmc->max_blk_size = 0;
3571 mmc->max_blk_size = 512 << mmc->max_blk_size;
3574 * Maximum block count.
3576 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3581 if (!IS_ERR(mmc->supply.vqmmc))
3582 regulator_disable(mmc->supply.vqmmc);
3584 if (host->align_buffer)
3585 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3586 host->adma_table_sz, host->align_buffer,
3588 host->adma_table = NULL;
3589 host->align_buffer = NULL;
3593 EXPORT_SYMBOL_GPL(sdhci_setup_host);
3595 int __sdhci_add_host(struct sdhci_host *host)
3597 struct mmc_host *mmc = host->mmc;
3603 tasklet_init(&host->finish_tasklet,
3604 sdhci_tasklet_finish, (unsigned long)host);
3606 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3607 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3608 (unsigned long)host);
3610 init_waitqueue_head(&host->buf_ready_int);
3612 sdhci_init(host, 0);
3614 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3615 IRQF_SHARED, mmc_hostname(mmc), host);
3617 pr_err("%s: Failed to request IRQ %d: %d\n",
3618 mmc_hostname(mmc), host->irq, ret);
3622 #ifdef CONFIG_MMC_DEBUG
3623 sdhci_dumpregs(host);
3626 ret = sdhci_led_register(host);
3628 pr_err("%s: Failed to register LED device: %d\n",
3629 mmc_hostname(mmc), ret);
3635 ret = mmc_add_host(mmc);
3639 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3640 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3641 (host->flags & SDHCI_USE_ADMA) ?
3642 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3643 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3645 sdhci_enable_card_detection(host);
3650 sdhci_led_unregister(host);
3652 sdhci_do_reset(host, SDHCI_RESET_ALL);
3653 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3654 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3655 free_irq(host->irq, host);
3657 tasklet_kill(&host->finish_tasklet);
3659 if (!IS_ERR(mmc->supply.vqmmc))
3660 regulator_disable(mmc->supply.vqmmc);
3662 if (host->align_buffer)
3663 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3664 host->adma_table_sz, host->align_buffer,
3666 host->adma_table = NULL;
3667 host->align_buffer = NULL;
3671 EXPORT_SYMBOL_GPL(__sdhci_add_host);
3673 int sdhci_add_host(struct sdhci_host *host)
3677 ret = sdhci_setup_host(host);
3681 return __sdhci_add_host(host);
3683 EXPORT_SYMBOL_GPL(sdhci_add_host);
3685 void sdhci_remove_host(struct sdhci_host *host, int dead)
3687 struct mmc_host *mmc = host->mmc;
3688 unsigned long flags;
3691 spin_lock_irqsave(&host->lock, flags);
3693 host->flags |= SDHCI_DEVICE_DEAD;
3695 if (sdhci_has_requests(host)) {
3696 pr_err("%s: Controller removed during "
3697 " transfer!\n", mmc_hostname(mmc));
3698 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3701 spin_unlock_irqrestore(&host->lock, flags);
3704 sdhci_disable_card_detection(host);
3706 mmc_remove_host(mmc);
3708 sdhci_led_unregister(host);
3711 sdhci_do_reset(host, SDHCI_RESET_ALL);
3713 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3714 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3715 free_irq(host->irq, host);
3717 del_timer_sync(&host->timer);
3718 del_timer_sync(&host->data_timer);
3720 tasklet_kill(&host->finish_tasklet);
3722 if (!IS_ERR(mmc->supply.vqmmc))
3723 regulator_disable(mmc->supply.vqmmc);
3725 if (host->align_buffer)
3726 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3727 host->adma_table_sz, host->align_buffer,
3730 host->adma_table = NULL;
3731 host->align_buffer = NULL;
3734 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3736 void sdhci_free_host(struct sdhci_host *host)
3738 mmc_free_host(host->mmc);
3741 EXPORT_SYMBOL_GPL(sdhci_free_host);
3743 /*****************************************************************************\
3745 * Driver init/exit *
3747 \*****************************************************************************/
3749 static int __init sdhci_drv_init(void)
3752 ": Secure Digital Host Controller Interface driver\n");
3753 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3758 static void __exit sdhci_drv_exit(void)
3762 module_init(sdhci_drv_init);
3763 module_exit(sdhci_drv_exit);
3765 module_param(debug_quirks, uint, 0444);
3766 module_param(debug_quirks2, uint, 0444);
3768 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3769 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3770 MODULE_LICENSE("GPL");
3772 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3773 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");