2 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
5 * Copyright 2007, Freescale Semiconductor, Inc
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/regs-ssp.h>
34 #include <asm/arch/regs-clkctrl.h>
35 #include <imx_ssp_mmc.h>
37 #undef IMX_SSP_MMC_DEBUG
39 static inline int ssp_mmc_read(struct mmc *mmc, uint reg)
41 struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv;
42 return REG_RD(cfg->ssp_mmc_base, reg);
45 static inline void ssp_mmc_write(struct mmc *mmc, uint reg, uint val)
47 struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv;
48 REG_WR(cfg->ssp_mmc_base, reg, val);
51 static inline void mdelay(unsigned long msec)
54 for (i = 0; i < msec; i++)
58 static inline void sdelay(unsigned long sec)
61 for (i = 0; i < sec; i++)
66 * Sends a command out on the bus. Takes the mmc pointer,
67 * a command pointer, and an optional data pointer.
70 ssp_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
74 #ifdef IMX_SSP_MMC_DEBUG
75 printf("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
80 while (ssp_mmc_read(mmc, HW_SSP_STATUS) & (BM_SSP_STATUS_BUSY |
81 BM_SSP_STATUS_DATA_BUSY | BM_SSP_STATUS_CMD_BUSY)) {
85 printf("MMC%d: Bus busy timeout!\n",
91 /* See if card is present */
92 if (ssp_mmc_read(mmc, HW_SSP_STATUS) & BM_SSP_STATUS_CARD_DETECT) {
93 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
97 /* Clear all control bits except bus width */
98 ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, 0xff3fffff);
101 if (!(cmd->resp_type & MMC_RSP_CRC))
102 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_IGNORE_CRC);
103 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
104 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_GET_RESP);
105 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
106 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_LONG_RESP);
109 ssp_mmc_write(mmc, HW_SSP_CMD0,
110 (ssp_mmc_read(mmc, HW_SSP_CMD0) & ~BM_SSP_CMD0_CMD) |
111 (cmd->cmdidx << BP_SSP_CMD0_CMD));
112 /* Command argument */
113 ssp_mmc_write(mmc, HW_SSP_CMD1, cmd->cmdarg);
118 if (data->flags & MMC_DATA_READ) {
119 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET,
121 } else if (ssp_mmc_is_wp(mmc)) {
122 printf("MMC%d: Can not write a locked card!\n",
126 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_DATA_XFER);
127 ssp_mmc_write(mmc, HW_SSP_BLOCK_SIZE,
128 ((data->blocks - 1) <<
129 BP_SSP_BLOCK_SIZE_BLOCK_COUNT) |
130 ((ffs(data->blocksize) - 1) <<
131 BP_SSP_BLOCK_SIZE_BLOCK_SIZE));
132 ssp_mmc_write(mmc, HW_SSP_XFER_SIZE,
133 data->blocksize * data->blocks);
136 /* Kick off the command */
137 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_WAIT_FOR_IRQ);
138 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_ENABLE);
139 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_RUN);
141 /* Wait for the command to complete */
146 printf("MMC%d: Command %d busy\n",
151 } while (ssp_mmc_read(mmc, HW_SSP_STATUS) &
152 BM_SSP_STATUS_CMD_BUSY);
154 /* Check command timeout */
155 if (ssp_mmc_read(mmc, HW_SSP_STATUS) &
156 BM_SSP_STATUS_RESP_TIMEOUT) {
157 #ifdef IMX_SSP_MMC_DEBUG
158 printf("MMC%d: Command %d timeout\n", mmc->block_dev.dev,
164 /* Check command errors */
165 if (ssp_mmc_read(mmc, HW_SSP_STATUS) &
166 (BM_SSP_STATUS_RESP_CRC_ERR | BM_SSP_STATUS_RESP_ERR)) {
167 printf("MMC%d: Command %d error (status 0x%08x)!\n",
168 mmc->block_dev.dev, cmd->cmdidx,
169 ssp_mmc_read(mmc, HW_SSP_STATUS));
173 /* Copy response to response buffer */
174 if (cmd->resp_type & MMC_RSP_136) {
175 cmd->response[3] = ssp_mmc_read(mmc, HW_SSP_SDRESP0);
176 cmd->response[2] = ssp_mmc_read(mmc, HW_SSP_SDRESP1);
177 cmd->response[1] = ssp_mmc_read(mmc, HW_SSP_SDRESP2);
178 cmd->response[0] = ssp_mmc_read(mmc, HW_SSP_SDRESP3);
180 cmd->response[0] = ssp_mmc_read(mmc, HW_SSP_SDRESP0);
182 /* Return if no data to process */
186 /* Process the data */
187 u32 xfer_cnt = data->blocksize * data->blocks;
190 if (data->flags & MMC_DATA_READ) {
191 tmp_ptr = (u32 *)data->dest;
192 while (xfer_cnt > 0) {
193 if ((ssp_mmc_read(mmc, HW_SSP_STATUS) &
194 BM_SSP_STATUS_FIFO_EMPTY) == 0) {
195 *tmp_ptr++ = ssp_mmc_read(mmc, HW_SSP_DATA);
200 tmp_ptr = (u32 *)data->src;
201 while (xfer_cnt > 0) {
202 if ((ssp_mmc_read(mmc, HW_SSP_STATUS) &
203 BM_SSP_STATUS_FIFO_FULL) == 0) {
204 ssp_mmc_write(mmc, HW_SSP_DATA, *tmp_ptr++);
210 /* Check data errors */
211 if (ssp_mmc_read(mmc, HW_SSP_STATUS) &
212 (BM_SSP_STATUS_TIMEOUT | BM_SSP_STATUS_DATA_CRC_ERR |
213 BM_SSP_STATUS_FIFO_OVRFLW | BM_SSP_STATUS_FIFO_UNDRFLW)) {
214 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
215 mmc->block_dev.dev, cmd->cmdidx,
216 ssp_mmc_read(mmc, HW_SSP_STATUS));
223 static void set_bit_clock(struct mmc *mmc, u32 clock)
225 const u32 sspclk = 480000 * 18 / 29 / 1; /* 297931 KHz */
226 u32 divide, rate, tgtclk;
229 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
230 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
231 * CLOCK_RATE could be any integer from 0 to 255.
233 clock /= 1000; /* KHz */
234 for (divide = 2; divide < 254; divide += 2) {
235 rate = sspclk / clock / divide;
240 tgtclk = sspclk / divide / rate;
241 while (tgtclk > clock) {
243 tgtclk = sspclk / divide / rate;
248 /* Always set timeout the maximum */
249 ssp_mmc_write(mmc, HW_SSP_TIMING, BM_SSP_TIMING_TIMEOUT |
250 divide << BP_SSP_TIMING_CLOCK_DIVIDE |
251 (rate - 1) << BP_SSP_TIMING_CLOCK_RATE);
253 #ifdef IMX_SSP_MMC_DEBUG
254 printf("MMC%d: Set clock rate to %d KHz (requested %d KHz)\n",
255 mmc->block_dev.dev, tgtclk, clock);
259 static void ssp_mmc_set_ios(struct mmc *mmc)
263 /* Set the clock speed */
265 set_bit_clock(mmc, mmc->clock);
267 /* Set the bus width */
268 regval = ssp_mmc_read(mmc, HW_SSP_CTRL0);
269 regval &= ~BM_SSP_CTRL0_BUS_WIDTH;
270 switch (mmc->bus_width) {
272 regval |= (BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT <<
273 BP_SSP_CTRL0_BUS_WIDTH);
276 regval |= (BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT <<
277 BP_SSP_CTRL0_BUS_WIDTH);
280 regval |= (BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT <<
281 BP_SSP_CTRL0_BUS_WIDTH);
283 ssp_mmc_write(mmc, HW_SSP_CTRL0, regval);
285 #ifdef IMX_SSP_MMC_DEBUG
286 printf("MMC%d: Set %d bits bus width\n",
287 mmc->block_dev.dev, mmc->bus_width);
291 static int ssp_mmc_init(struct mmc *mmc)
293 struct imx_ssp_mmc_cfg *cfg = (struct imx_ssp_mmc_cfg *)mmc->priv;
299 /* Set REF_IO0 at 297.731 MHz */
300 regval = REG_RD(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0);
301 regval &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
302 REG_WR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0,
303 regval | (29 << BP_CLKCTRL_FRAC0_IO0FRAC));
305 REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_FRAC0,
306 BM_CLKCTRL_FRAC0_CLKGATEIO0);
308 /* Source SSPCLK from REF_IO0 */
309 REG_CLR(REGS_CLKCTRL_BASE, HW_CLKCTRL_CLKSEQ,
310 cfg->clkctrl_clkseq_ssp_offset);
312 REG_WR(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset,
313 REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset) &
314 ~BM_CLKCTRL_SSP_CLKGATE);
315 /* Set SSPCLK divide 1 */
316 regval = REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset);
317 regval &= ~(BM_CLKCTRL_SSP_DIV_FRAC_EN | BM_CLKCTRL_SSP_DIV);
318 REG_WR(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset,
319 regval | (1 << BP_CLKCTRL_SSP_DIV));
320 /* Wait for new divide ready */
323 } while (REG_RD(REGS_CLKCTRL_BASE, cfg->clkctrl_ssp_offset) &
324 BM_CLKCTRL_SSP_BUSY);
326 /* Prepare for software reset */
327 ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_SFTRST);
328 ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_CLKGATE);
330 ssp_mmc_write(mmc, HW_SSP_CTRL0_SET, BM_SSP_CTRL0_SFTRST);
331 /* Wait for confirmation */
332 while (!(ssp_mmc_read(mmc, HW_SSP_CTRL0) & BM_SSP_CTRL0_CLKGATE))
335 ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_SFTRST);
336 ssp_mmc_write(mmc, HW_SSP_CTRL0_CLR, BM_SSP_CTRL0_CLKGATE);
338 /* 8 bits word length in MMC mode */
339 regval = ssp_mmc_read(mmc, HW_SSP_CTRL1);
340 regval &= ~(BM_SSP_CTRL1_SSP_MODE | BM_SSP_CTRL1_WORD_LENGTH);
341 ssp_mmc_write(mmc, HW_SSP_CTRL1, regval |
342 (BV_SSP_CTRL1_SSP_MODE__SD_MMC << BP_SSP_CTRL1_SSP_MODE) |
343 (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS <<
344 BP_SSP_CTRL1_WORD_LENGTH));
346 /* Set initial bit clock 400 KHz */
347 set_bit_clock(mmc, 400000);
349 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
350 ssp_mmc_write(mmc, HW_SSP_CMD0_SET, BM_SSP_CMD0_CONT_CLKING_EN);
352 ssp_mmc_write(mmc, HW_SSP_CMD0_CLR, BM_SSP_CMD0_CONT_CLKING_EN);
357 int imx_ssp_mmc_initialize(bd_t *bis, struct imx_ssp_mmc_cfg *cfg)
361 mmc = malloc(sizeof(struct mmc));
362 sprintf(mmc->name, "IMX_SSP_MMC");
363 mmc->send_cmd = ssp_mmc_send_cmd;
364 mmc->set_ios = ssp_mmc_set_ios;
365 mmc->init = ssp_mmc_init;
368 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_31_32 | MMC_VDD_30_31 |
369 MMC_VDD_29_30 | MMC_VDD_28_29 | MMC_VDD_27_28;
371 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
372 MMC_MODE_HS_52MHz | MMC_MODE_HS;
375 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
376 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
377 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
378 * CLOCK_RATE could be any integer from 0 to 255.
381 mmc->f_max = 148000000; /* 297.731 MHz / 2 */