2 * Marvell MMC/SD/SDIO driver
4 * (C) Copyright 2012-2014
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Maen Suleiman, Gerald Kerma
8 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <mvebu_mmc.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define DRIVER_NAME "MVEBU_MMC"
24 #define MVEBU_TARGET_DRAM 0
26 #define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
28 static void mvebu_mmc_write(u32 offs, u32 val)
30 writel(val, CONFIG_SYS_MMC_BASE + (offs));
33 static u32 mvebu_mmc_read(u32 offs)
35 return readl(CONFIG_SYS_MMC_BASE + (offs));
38 static int mvebu_mmc_setup_data(struct mmc_data *data)
42 debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
43 (data->flags & MMC_DATA_READ) ? "read" : "write",
44 data->blocks, data->blocksize);
46 /* default to maximum timeout */
47 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
48 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
49 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
51 if (data->flags & MMC_DATA_READ) {
52 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
53 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
55 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
56 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
59 mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
60 mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
65 static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
66 struct mmc_data *data)
74 debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
75 DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
77 debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
78 cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
81 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
82 * register is sometimes not set before a while when some
83 * "unusual" data block sizes are used (such as with the SWITCH
84 * command), even despite the fact that the XFER_DONE interrupt
85 * was raised. And if another data transfer starts before
86 * this bit comes to good sense (which eventually happens by
87 * itself) then the new transfer simply fails with a timeout.
89 if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
90 ushort hw_state, count = 0;
94 hw_state = mvebu_mmc_read(SDIO_HW_STATE);
95 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
96 printf("%s : FIFO_EMPTY bit missing\n",
101 } while (!(hw_state & CMD_FIFO_EMPTY));
102 debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
103 DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
106 /* Set up for a data transfer if we have one */
108 int err = mvebu_mmc_setup_data(data);
111 debug("%s: command DATA error :%x\n",
117 resptype = SDIO_CMD_INDEX(cmd->cmdidx);
119 /* Analyzing resptype/xfertype/waittype for the command */
120 if (cmd->resp_type & MMC_RSP_BUSY)
121 resptype |= SDIO_CMD_RSP_48BUSY;
122 else if (cmd->resp_type & MMC_RSP_136)
123 resptype |= SDIO_CMD_RSP_136;
124 else if (cmd->resp_type & MMC_RSP_PRESENT)
125 resptype |= SDIO_CMD_RSP_48;
127 resptype |= SDIO_CMD_RSP_NONE;
129 if (cmd->resp_type & MMC_RSP_CRC)
130 resptype |= SDIO_CMD_CHECK_CMDCRC;
132 if (cmd->resp_type & MMC_RSP_OPCODE)
133 resptype |= SDIO_CMD_INDX_CHECK;
135 if (cmd->resp_type & MMC_RSP_PRESENT) {
136 resptype |= SDIO_UNEXPECTED_RESP;
137 waittype |= SDIO_NOR_UNEXP_RSP;
141 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
142 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
143 if (data->flags & MMC_DATA_READ) {
144 xfertype |= SDIO_XFER_MODE_TO_HOST;
145 waittype = SDIO_NOR_DMA_INI;
147 waittype |= SDIO_NOR_XFER_DONE;
150 waittype |= SDIO_NOR_CMD_DONE;
153 /* Setting cmd arguments */
154 mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
155 mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
157 /* Setting Xfer mode */
158 mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
160 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
161 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
163 /* Sending command */
164 mvebu_mmc_write(SDIO_CMD, resptype);
166 mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
167 mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
169 start = get_timer(0);
171 while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
172 if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
173 debug("%s: error! cmdidx : %d, err reg: %04x\n",
174 DRIVER_NAME, cmd->cmdidx,
175 mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
176 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
177 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
178 debug("%s: command READ timed out\n",
182 debug("%s: command READ error\n", DRIVER_NAME);
186 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
187 debug("%s: command timed out\n", DRIVER_NAME);
192 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
193 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
196 /* Handling response */
197 if (cmd->resp_type & MMC_RSP_136) {
200 for (resp_indx = 0; resp_indx < 8; resp_indx++)
202 = mvebu_mmc_read(SDIO_RSP(resp_indx));
204 cmd->response[0] = ((response[0] & 0x03ff) << 22) |
205 ((response[1] & 0xffff) << 6) |
206 ((response[2] & 0xfc00) >> 10);
207 cmd->response[1] = ((response[2] & 0x03ff) << 22) |
208 ((response[3] & 0xffff) << 6) |
209 ((response[4] & 0xfc00) >> 10);
210 cmd->response[2] = ((response[4] & 0x03ff) << 22) |
211 ((response[5] & 0xffff) << 6) |
212 ((response[6] & 0xfc00) >> 10);
213 cmd->response[3] = ((response[6] & 0x03ff) << 22) |
214 ((response[7] & 0x3fff) << 8);
215 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
218 for (resp_indx = 0; resp_indx < 3; resp_indx++)
220 = mvebu_mmc_read(SDIO_RSP(resp_indx));
222 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
223 ((response[1] & 0xffff) << (14 - 8)) |
224 ((response[0] & 0x03ff) << (30 - 8));
225 cmd->response[1] = ((response[0] & 0xfc00) >> 10);
226 cmd->response[2] = 0;
227 cmd->response[3] = 0;
230 debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
231 debug("[0x%x] ", cmd->response[0]);
232 debug("[0x%x] ", cmd->response[1]);
233 debug("[0x%x] ", cmd->response[2]);
234 debug("[0x%x] ", cmd->response[3]);
240 static void mvebu_mmc_power_up(void)
242 debug("%s: power up\n", DRIVER_NAME);
244 /* disable interrupts */
245 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
246 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
249 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
251 mvebu_mmc_write(SDIO_XFER_MODE, 0);
254 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
255 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
257 /* enable interrupts status */
258 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
259 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
262 static void mvebu_mmc_set_clk(unsigned int clock)
267 debug("%s: clock off\n", DRIVER_NAME);
268 mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
269 mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
271 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
272 if (m > MVEBU_MMC_BASE_DIV_MAX)
273 m = MVEBU_MMC_BASE_DIV_MAX;
274 mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
275 debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
281 static void mvebu_mmc_set_bus(unsigned int bus)
285 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
286 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
290 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
294 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
297 /* default transfer mode */
298 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
299 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
301 /* default to maximum timeout */
302 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
303 ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
305 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
307 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
309 debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
310 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
311 "push-pull" : "open-drain",
312 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
313 "4bit-width" : "1bit-width",
314 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
317 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
321 static void mvebu_mmc_set_ios(struct mmc *mmc)
323 debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
324 mmc->bus_width, mmc->clock);
325 mvebu_mmc_set_bus(mmc->bus_width);
326 mvebu_mmc_set_clk(mmc->clock);
330 * Set window register.
332 static void mvebu_window_setup(void)
336 for (i = 0; i < 4; i++) {
337 mvebu_mmc_write(WINDOW_CTRL(i), 0);
338 mvebu_mmc_write(WINDOW_BASE(i), 0);
340 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
341 u32 size, base, attrib;
343 /* Enable DRAM bank */
346 attrib = KWCPU_ATTR_DRAM_CS0;
349 attrib = KWCPU_ATTR_DRAM_CS1;
352 attrib = KWCPU_ATTR_DRAM_CS2;
355 attrib = KWCPU_ATTR_DRAM_CS3;
358 /* invalide bank, disable access */
363 size = gd->bd->bi_dram[i].size;
364 base = gd->bd->bi_dram[i].start;
365 if (size && attrib) {
366 mvebu_mmc_write(WINDOW_CTRL(i),
367 MVCPU_WIN_CTRL_DATA(size,
372 mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
374 mvebu_mmc_write(WINDOW_BASE(i), base);
378 static int mvebu_mmc_initialize(struct mmc *mmc)
380 debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
383 * Setting host parameters
384 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
385 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
387 mvebu_mmc_write(SDIO_HOST_CTRL,
388 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
389 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
390 SDIO_HOST_CTRL_BIG_ENDIAN |
391 SDIO_HOST_CTRL_PUSH_PULL_EN |
392 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
394 mvebu_mmc_write(SDIO_CLK_CTRL, 0);
397 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
398 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
400 /* disable interrupts */
401 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
402 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
404 mvebu_window_setup();
407 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
414 static const struct mmc_ops mvebu_mmc_ops = {
415 .send_cmd = mvebu_mmc_send_cmd,
416 .set_ios = mvebu_mmc_set_ios,
417 .init = mvebu_mmc_initialize,
420 static struct mmc_config mvebu_mmc_cfg = {
422 .ops = &mvebu_mmc_ops,
423 .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
424 .f_max = MVEBU_MMC_CLOCKRATE_MAX,
425 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
426 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC |
428 .part_type = PART_TYPE_DOS,
429 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
432 int mvebu_mmc_init(bd_t *bis)
436 mvebu_mmc_power_up();
438 mmc = mmc_create(&mvebu_mmc_cfg, bis);