2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/errno.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
29 #include <bouncebuf.h>
33 struct mxs_ssp_regs *regs;
35 int (*mmc_is_wp)(int);
37 struct mxs_dma_desc *desc;
38 struct mmc_config cfg; /* mmc configuration */
41 #define MXSMMC_MAX_TIMEOUT 10000
42 #define MXSMMC_SMALL_TRANSFER 512
44 static int mxsmmc_cd(struct mxsmmc_priv *priv)
46 struct mxs_ssp_regs *ssp_regs = priv->regs;
49 return priv->mmc_cd(priv->id);
51 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
54 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
56 struct mxs_ssp_regs *ssp_regs = priv->regs;
58 int timeout = MXSMMC_MAX_TIMEOUT;
60 uint32_t data_count = data->blocksize * data->blocks;
62 if (data->flags & MMC_DATA_READ) {
63 data_ptr = (uint32_t *)data->dest;
64 while (data_count && --timeout) {
65 reg = readl(&ssp_regs->hw_ssp_status);
66 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
67 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
69 timeout = MXSMMC_MAX_TIMEOUT;
74 data_ptr = (uint32_t *)data->src;
76 while (data_count && --timeout) {
77 reg = readl(&ssp_regs->hw_ssp_status);
78 if (!(reg & SSP_STATUS_FIFO_FULL)) {
79 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
81 timeout = MXSMMC_MAX_TIMEOUT;
87 return timeout ? 0 : COMM_ERR;
90 static int mxsmmc_send_cmd_dma(struct mmc *mmc, struct mxsmmc_priv *priv,
91 struct mmc_data *data)
93 uint32_t data_count = data->blocksize * data->blocks;
95 struct mxs_dma_desc *desc = priv->desc;
98 struct bounce_buffer bbstate;
99 unsigned long xfer_rate = (mmc->clock ?: 400000) * mmc->bus_width;
100 unsigned long dma_timeout = data_count * 8 /
101 DIV_ROUND_UP(xfer_rate, 1000);
103 memset(desc, 0, sizeof(struct mxs_dma_desc));
104 desc->address = (dma_addr_t)desc;
106 if (data->flags & MMC_DATA_READ) {
107 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
109 flags = GEN_BB_WRITE;
111 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
112 addr = (void *)data->src;
116 bounce_buffer_start(&bbstate, addr, data_count, flags);
118 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
120 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
121 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
123 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
124 mxs_dma_desc_append(dmach, priv->desc);
125 /* set DMA timeout adding 250ms for min timeout according to SD spec. */
126 mxs_dma_set_timeout(dmach, dma_timeout + 250);
127 if (mxs_dma_go(dmach)) {
128 bounce_buffer_stop(&bbstate);
132 bounce_buffer_stop(&bbstate);
138 * Sends a command out on the bus. Takes the mmc pointer,
139 * a command pointer, and an optional data pointer.
142 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
144 struct mxsmmc_priv *priv = mmc->priv;
145 struct mxs_ssp_regs *ssp_regs = priv->regs;
149 const uint32_t busy_stat = SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
153 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
156 timeout = MXSMMC_MAX_TIMEOUT;
157 while ((reg = readl(&ssp_regs->hw_ssp_status)) & busy_stat) {
162 if (reg & busy_stat && readl(&ssp_regs->hw_ssp_status) & busy_stat) {
163 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
167 /* See if card is present */
168 if (!mxsmmc_cd(priv)) {
169 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
173 /* Start building CTRL0 contents */
174 ctrl0 = priv->buswidth;
177 if (!(cmd->resp_type & MMC_RSP_CRC))
178 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
179 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
180 ctrl0 |= SSP_CTRL0_GET_RESP;
181 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
182 ctrl0 |= SSP_CTRL0_LONG_RESP;
184 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
185 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
187 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
190 reg = readl(&ssp_regs->hw_ssp_cmd0);
191 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
192 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
193 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
194 reg |= SSP_CMD0_APPEND_8CYC;
195 writel(reg, &ssp_regs->hw_ssp_cmd0);
197 /* Command argument */
198 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
203 if (data->flags & MMC_DATA_READ) {
204 ctrl0 |= SSP_CTRL0_READ;
205 } else if (priv->mmc_is_wp &&
206 priv->mmc_is_wp(mmc->block_dev.dev)) {
207 printf("MMC%d: Can not write a locked card!\n",
212 ctrl0 |= SSP_CTRL0_DATA_XFER;
214 reg = data->blocksize * data->blocks;
215 #if defined(CONFIG_SOC_MX23)
216 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
218 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
219 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
220 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
221 ((ffs(data->blocksize) - 1) <<
222 SSP_CMD0_BLOCK_SIZE_OFFSET));
223 #elif defined(CONFIG_SOC_MX28)
224 writel(reg, &ssp_regs->hw_ssp_xfer_size);
226 reg = ((data->blocks - 1) <<
227 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
228 ((ffs(data->blocksize) - 1) <<
229 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
230 writel(reg, &ssp_regs->hw_ssp_block_size);
234 /* Kick off the command */
235 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
236 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
238 /* Wait for the command to complete */
239 timeout = MXSMMC_MAX_TIMEOUT;
242 reg = readl(&ssp_regs->hw_ssp_status);
243 if (!(reg & SSP_STATUS_CMD_BUSY))
246 if ((reg & SSP_STATUS_CMD_BUSY) &&
247 (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CMD_BUSY)) {
248 printf("MMC%d: Command %d busy\n",
249 mmc->block_dev.dev, cmd->cmdidx);
253 /* Check command timeout */
254 if (reg & SSP_STATUS_RESP_TIMEOUT) {
255 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
256 mmc->block_dev.dev, cmd->cmdidx, reg);
260 /* Check command errors */
261 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
262 printf("MMC%d: Command %d error (status 0x%08x)!\n",
263 mmc->block_dev.dev, cmd->cmdidx, reg);
267 /* Copy response to response buffer */
268 if (cmd->resp_type & MMC_RSP_136) {
269 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
270 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
271 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
272 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
274 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
276 /* Return if no data to process */
280 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
281 ret = mxsmmc_send_cmd_pio(priv, data);
283 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
284 mmc->block_dev.dev, cmd->cmdidx, reg);
288 ret = mxsmmc_send_cmd_dma(mmc, priv, data);
290 printf("MMC%d: DMA transfer failed\n",
296 /* Check data errors */
297 reg = readl(&ssp_regs->hw_ssp_status);
299 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
300 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
301 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
302 mmc->block_dev.dev, cmd->cmdidx, reg);
309 static void mxsmmc_set_ios(struct mmc *mmc)
311 struct mxsmmc_priv *priv = mmc->priv;
312 struct mxs_ssp_regs *ssp_regs = priv->regs;
314 /* Set the clock speed */
316 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
318 switch (mmc->bus_width) {
320 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
323 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
326 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
330 /* Set the bus width */
331 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
332 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
334 debug("MMC%d: Set %d bits bus width\n",
335 mmc->block_dev.dev, mmc->bus_width);
338 static int mxsmmc_init(struct mmc *mmc)
340 struct mxsmmc_priv *priv = mmc->priv;
341 struct mxs_ssp_regs *ssp_regs = priv->regs;
344 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
346 /* Reconfigure the SSP block for MMC operation */
347 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
348 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
349 SSP_CTRL1_DMA_ENABLE |
351 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
352 SSP_CTRL1_DATA_CRC_IRQ_EN |
353 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
354 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
355 SSP_CTRL1_RESP_ERR_IRQ_EN,
356 &ssp_regs->hw_ssp_ctrl1_set);
358 /* Set initial bit clock 400 KHz */
359 mxs_set_ssp_busclock(priv->id, 400);
361 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
362 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
364 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
369 static const struct mmc_ops mxsmmc_ops = {
370 .send_cmd = mxsmmc_send_cmd,
371 .set_ios = mxsmmc_set_ios,
375 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
378 struct mxsmmc_priv *priv;
380 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
382 if (!mxs_ssp_bus_id_valid(id))
385 priv = calloc(sizeof(struct mxsmmc_priv), 1);
389 priv->desc = mxs_dma_desc_alloc();
395 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
399 priv->mmc_is_wp = wp;
402 priv->regs = mxs_ssp_regs_by_bus(id);
404 priv->cfg.name = "MXS MMC";
405 priv->cfg.ops = &mxsmmc_ops;
407 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
409 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
410 MMC_MODE_HS_52MHz | MMC_MODE_HS |
414 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
415 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
416 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
417 * CLOCK_RATE could be any integer from 0 to 255.
419 priv->cfg.f_min = 400000;
420 priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
421 priv->cfg.b_max = 0x20;
423 mmc = mmc_create(&priv->cfg, priv);
431 mxs_dma_desc_free(priv->desc);