drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <twl6030.h>
  32 #include <asm/io.h>
  33 #include <asm/arch/mmc_host_def.h>
  34 #include <asm/arch/sys_proto.h>
  35
  36 /* If we fail after 1 second wait, something is really bad */
  37 #define MAX_RETRY_MS    1000
  38
  39 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  40 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  41                         unsigned int siz);
  42 static struct mmc hsmmc_dev[2];
  43
  44 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  45 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  46 {
  47         u32 value = 0;
  48         struct omap4_sys_ctrl_regs *const ctrl =
  49                 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
  50
  51
  52         value = readl(&ctrl->control_pbiaslite);
  53         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
  54         writel(value, &ctrl->control_pbiaslite);
  55         /* set VMMC to 3V */
  56         twl6030_power_mmc_init();
  57         value = readl(&ctrl->control_pbiaslite);
  58         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
  59         writel(value, &ctrl->control_pbiaslite);
  60 }
  61 #endif
  62
  63 unsigned char mmc_board_init(struct mmc *mmc)
  64 {
  65 #if defined(CONFIG_TWL4030_POWER)
  66         twl4030_power_mmc_init();
  67 #endif
  68
  69 #if defined(CONFIG_OMAP34XX)
  70         t2_t *t2_base = (t2_t *)T2_BASE;
  71         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  72
  73         writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
  74                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
  75                 &t2_base->pbias_lite);
  76
  77         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  78                 &t2_base->devconf0);
  79
  80         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
  81                 &t2_base->devconf1);
  82
  83         writel(readl(&prcm_base->fclken1_core) |
  84                 EN_MMC1 | EN_MMC2 | EN_MMC3,
  85                 &prcm_base->fclken1_core);
  86
  87         writel(readl(&prcm_base->iclken1_core) |
  88                 EN_MMC1 | EN_MMC2 | EN_MMC3,
  89                 &prcm_base->iclken1_core);
  90 #endif
  91
  92 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  93         /* PBIAS config needed for MMC1 only */
  94         if (mmc->block_dev.dev == 0)
  95                 omap4_vmmc_pbias_config(mmc);
  96 #endif
  97
  98         return 0;
  99 }
 100
 101 void mmc_init_stream(struct hsmmc *mmc_base)
 102 {
 103         ulong start;
 104
 105         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 106
 107         writel(MMC_CMD0, &mmc_base->cmd);
 108         start = get_timer(0);
 109         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 110                 if (get_timer(0) - start > MAX_RETRY_MS) {
 111                         printf("%s: timedout waiting for cc!\n", __func__);
 112                         return;
 113                 }
 114         }
 115         writel(CC_MASK, &mmc_base->stat)
 116                 ;
 117         writel(MMC_CMD0, &mmc_base->cmd)
 118                 ;
 119         start = get_timer(0);
 120         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 121                 if (get_timer(0) - start > MAX_RETRY_MS) {
 122                         printf("%s: timedout waiting for cc2!\n", __func__);
 123                         return;
 124                 }
 125         }
 126         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 127 }
 128
 129
 130 static int mmc_init_setup(struct mmc *mmc)
 131 {
 132         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 133         unsigned int reg_val;
 134         unsigned int dsor;
 135         ulong start;
 136
 137         mmc_board_init(mmc);
 138
 139         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 140                 &mmc_base->sysconfig);
 141         start = get_timer(0);
 142         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 143                 if (get_timer(0) - start > MAX_RETRY_MS) {
 144                         printf("%s: timedout waiting for cc2!\n", __func__);
 145                         return TIMEOUT;
 146                 }
 147         }
 148         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 149         start = get_timer(0);
 150         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 151                 if (get_timer(0) - start > MAX_RETRY_MS) {
 152                         printf("%s: timedout waiting for softresetall!\n",
 153                                 __func__);
 154                         return TIMEOUT;
 155                 }
 156         }
 157         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 158         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 159                 &mmc_base->capa);
 160
 161         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 162
 163         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 164                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 165                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 166
 167         dsor = 240;
 168         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 169                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 170         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 171                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 172         start = get_timer(0);
 173         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 174                 if (get_timer(0) - start > MAX_RETRY_MS) {
 175                         printf("%s: timedout waiting for ics!\n", __func__);
 176                         return TIMEOUT;
 177                 }
 178         }
 179         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 180
 181         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 182
 183         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 184                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 185                 &mmc_base->ie);
 186
 187         mmc_init_stream(mmc_base);
 188
 189         return 0;
 190 }
 191
 192
 193 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 194                         struct mmc_data *data)
 195 {
 196         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 197         unsigned int flags, mmc_stat;
 198         ulong start;
 199
 200         start = get_timer(0);
 201         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 202                 if (get_timer(0) - start > MAX_RETRY_MS) {
 203                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 204                                         __func__);
 205                         return TIMEOUT;
 206                 }
 207         }
 208         writel(0xFFFFFFFF, &mmc_base->stat);
 209         start = get_timer(0);
 210         while (readl(&mmc_base->stat)) {
 211                 if (get_timer(0) - start > MAX_RETRY_MS) {
 212                         printf("%s: timedout waiting for stat!\n", __func__);
 213                         return TIMEOUT;
 214                 }
 215         }
 216         /*
 217          * CMDREG
 218          * CMDIDX[13:8] : Command index
 219          * DATAPRNT[5]  : Data Present Select
 220          * ENCMDIDX[4]  : Command Index Check Enable
 221          * ENCMDCRC[3]  : Command CRC Check Enable
 222          * RSPTYP[1:0]
 223          *      00 = No Response
 224          *      01 = Length 136
 225          *      10 = Length 48
 226          *      11 = Length 48 Check busy after response
 227          */
 228         /* Delay added before checking the status of frq change
 229          * retry not supported by mmc.c(core file)
 230          */
 231         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 232                 udelay(50000); /* wait 50 ms */
 233
 234         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 235                 flags = 0;
 236         else if (cmd->resp_type & MMC_RSP_136)
 237                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 238         else if (cmd->resp_type & MMC_RSP_BUSY)
 239                 flags = RSP_TYPE_LGHT48B;
 240         else
 241                 flags = RSP_TYPE_LGHT48;
 242
 243         /* enable default flags */
 244         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 245                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 246
 247         if (cmd->resp_type & MMC_RSP_CRC)
 248                 flags |= CCCE_CHECK;
 249         if (cmd->resp_type & MMC_RSP_OPCODE)
 250                 flags |= CICE_CHECK;
 251
 252         if (data) {
 253                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 254                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 255                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 256                         data->blocksize = 512;
 257                         writel(data->blocksize | (data->blocks << 16),
 258                                                         &mmc_base->blk);
 259                 } else
 260                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 261
 262                 if (data->flags & MMC_DATA_READ)
 263                         flags |= (DP_DATA | DDIR_READ);
 264                 else
 265                         flags |= (DP_DATA | DDIR_WRITE);
 266         }
 267
 268         writel(cmd->cmdarg, &mmc_base->arg);
 269         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 270
 271         start = get_timer(0);
 272         do {
 273                 mmc_stat = readl(&mmc_base->stat);
 274                 if (get_timer(0) - start > MAX_RETRY_MS) {
 275                         printf("%s : timeout: No status update\n", __func__);
 276                         return TIMEOUT;
 277                 }
 278         } while (!mmc_stat);
 279
 280         if ((mmc_stat & IE_CTO) != 0)
 281                 return TIMEOUT;
 282         else if ((mmc_stat & ERRI_MASK) != 0)
 283                 return -1;
 284
 285         if (mmc_stat & CC_MASK) {
 286                 writel(CC_MASK, &mmc_base->stat);
 287                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 288                         if (cmd->resp_type & MMC_RSP_136) {
 289                                 /* response type 2 */
 290                                 cmd->response[3] = readl(&mmc_base->rsp10);
 291                                 cmd->response[2] = readl(&mmc_base->rsp32);
 292                                 cmd->response[1] = readl(&mmc_base->rsp54);
 293                                 cmd->response[0] = readl(&mmc_base->rsp76);
 294                         } else
 295                                 /* response types 1, 1b, 3, 4, 5, 6 */
 296                                 cmd->response[0] = readl(&mmc_base->rsp10);
 297                 }
 298         }
 299
 300         if (data && (data->flags & MMC_DATA_READ)) {
 301                 mmc_read_data(mmc_base, data->dest,
 302                                 data->blocksize * data->blocks);
 303         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 304                 mmc_write_data(mmc_base, data->src,
 305                                 data->blocksize * data->blocks);
 306         }
 307         return 0;
 308 }
 309
 310 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 311 {
 312         unsigned int *output_buf = (unsigned int *)buf;
 313         unsigned int mmc_stat;
 314         unsigned int count;
 315
 316         /*
 317          * Start Polled Read
 318          */
 319         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 320         count /= 4;
 321
 322         while (size) {
 323                 ulong start = get_timer(0);
 324                 do {
 325                         mmc_stat = readl(&mmc_base->stat);
 326                         if (get_timer(0) - start > MAX_RETRY_MS) {
 327                                 printf("%s: timedout waiting for status!\n",
 328                                                 __func__);
 329                                 return TIMEOUT;
 330                         }
 331                 } while (mmc_stat == 0);
 332
 333                 if ((mmc_stat & ERRI_MASK) != 0)
 334                         return 1;
 335
 336                 if (mmc_stat & BRR_MASK) {
 337                         unsigned int k;
 338
 339                         writel(readl(&mmc_base->stat) | BRR_MASK,
 340                                 &mmc_base->stat);
 341                         for (k = 0; k < count; k++) {
 342                                 *output_buf = readl(&mmc_base->data);
 343                                 output_buf++;
 344                         }
 345                         size -= (count*4);
 346                 }
 347
 348                 if (mmc_stat & BWR_MASK)
 349                         writel(readl(&mmc_base->stat) | BWR_MASK,
 350                                 &mmc_base->stat);
 351
 352                 if (mmc_stat & TC_MASK) {
 353                         writel(readl(&mmc_base->stat) | TC_MASK,
 354                                 &mmc_base->stat);
 355                         break;
 356                 }
 357         }
 358         return 0;
 359 }
 360
 361 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 362                                 unsigned int size)
 363 {
 364         unsigned int *input_buf = (unsigned int *)buf;
 365         unsigned int mmc_stat;
 366         unsigned int count;
 367
 368         /*
 369          * Start Polled Read
 370          */
 371         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 372         count /= 4;
 373
 374         while (size) {
 375                 ulong start = get_timer(0);
 376                 do {
 377                         mmc_stat = readl(&mmc_base->stat);
 378                         if (get_timer(0) - start > MAX_RETRY_MS) {
 379                                 printf("%s: timedout waiting for status!\n",
 380                                                 __func__);
 381                                 return TIMEOUT;
 382                         }
 383                 } while (mmc_stat == 0);
 384
 385                 if ((mmc_stat & ERRI_MASK) != 0)
 386                         return 1;
 387
 388                 if (mmc_stat & BWR_MASK) {
 389                         unsigned int k;
 390
 391                         writel(readl(&mmc_base->stat) | BWR_MASK,
 392                                         &mmc_base->stat);
 393                         for (k = 0; k < count; k++) {
 394                                 writel(*input_buf, &mmc_base->data);
 395                                 input_buf++;
 396                         }
 397                         size -= (count*4);
 398                 }
 399
 400                 if (mmc_stat & BRR_MASK)
 401                         writel(readl(&mmc_base->stat) | BRR_MASK,
 402                                 &mmc_base->stat);
 403
 404                 if (mmc_stat & TC_MASK) {
 405                         writel(readl(&mmc_base->stat) | TC_MASK,
 406                                 &mmc_base->stat);
 407                         break;
 408                 }
 409         }
 410         return 0;
 411 }
 412
 413 static void mmc_set_ios(struct mmc *mmc)
 414 {
 415         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 416         unsigned int dsor = 0;
 417         ulong start;
 418
 419         /* configue bus width */
 420         switch (mmc->bus_width) {
 421         case 8:
 422                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 423                         &mmc_base->con);
 424                 break;
 425
 426         case 4:
 427                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 428                         &mmc_base->con);
 429                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 430                         &mmc_base->hctl);
 431                 break;
 432
 433         case 1:
 434         default:
 435                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 436                         &mmc_base->con);
 437                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 438                         &mmc_base->hctl);
 439                 break;
 440         }
 441
 442         /* configure clock with 96Mhz system clock.
 443          */
 444         if (mmc->clock != 0) {
 445                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 446                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 447                         dsor++;
 448         }
 449
 450         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 451                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 452
 453         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 454                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 455
 456         start = get_timer(0);
 457         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 458                 if (get_timer(0) - start > MAX_RETRY_MS) {
 459                         printf("%s: timedout waiting for ics!\n", __func__);
 460                         return;
 461                 }
 462         }
 463         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 464 }
 465
 466 int omap_mmc_init(int dev_index)
 467 {
 468         struct mmc *mmc;
 469
 470         mmc = &hsmmc_dev[dev_index];
 471
 472         sprintf(mmc->name, "OMAP SD/MMC");
 473         mmc->send_cmd = mmc_send_cmd;
 474         mmc->set_ios = mmc_set_ios;
 475         mmc->init = mmc_init_setup;
 476         mmc->getcd = NULL;
 477
 478         switch (dev_index) {
 479         case 0:
 480                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 481                 break;
 482 #ifdef OMAP_HSMMC2_BASE
 483         case 1:
 484                 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
 485                 break;
 486 #endif
 487 #ifdef OMAP_HSMMC3_BASE
 488         case 2:
 489                 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
 490                 break;
 491 #endif
 492         default:
 493                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 494                 return 1;
 495         }
 496         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 497         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 498                                 MMC_MODE_HC;
 499
 500         mmc->f_min = 400000;
 501         mmc->f_max = 52000000;
 502
 503         mmc->b_max = 0;
 504
 505 #if defined(CONFIG_OMAP34XX)
 506         /*
 507          * Silicon revs 2.1 and older do not support multiblock transfers.
 508          */
 509         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 510                 mmc->b_max = 1;
 511 #endif
 512
 513         mmc_register(mmc);
 514
 515         return 0;
 516 }