2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/err.h>
14 #if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) || \
15 defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)
16 #include <asm/arch/imx-regs.h>
19 static struct mxc_nand_host mxc_host;
20 static struct mxc_nand_host *host = &mxc_host;
22 #ifdef CONFIG_SOC_MX27
23 static int is_16bit_nand(void)
25 struct system_control_regs *sc_regs =
26 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
28 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
33 #elif defined(CONFIG_SOC_MX31)
34 static int is_16bit_nand(void)
36 struct clock_control_regs *sc_regs =
37 (struct clock_control_regs *)CCM_BASE;
39 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
44 #elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35)
45 static int is_16bit_nand(void)
47 struct ccm_regs *ccm =
48 (struct ccm_regs *)IMX_CCM_BASE;
50 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
55 #elif defined(CONFIG_SOC_MX51)
56 static int is_16bit_nand(void)
58 struct src *src = (struct src *)SRC_BASE_ADDR;
60 if (readl(&src->sbmr) & (1 << 2))
65 #elif defined(CONFIG_SOC_MX53)
66 /* BOOT_CFG[1..3][0..7] */
67 #define SRC_BOOT_CFG(m, n) (1 << ((m) * 8 + (n)))
68 static int is_16bit_nand(void)
70 struct src *src = (struct src *)SRC_BASE_ADDR;
72 if (readl(&src->sbmr) & SRC_BOOT_CFG(2, 5))
78 #warning "8/16 bit NAND autodetection not supported"
79 static int is_16bit_nand(void)
85 #define MXC_NAND_TIMEOUT (1 * HZ)
87 #define DRIVER_NAME "mxc_nand"
89 #ifndef CONFIG_MXC_NAND_REGS_BASE
90 #error CONFIG_MXC_NAND_REGS_BASE not defined
93 #if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX31)
95 #define nfc_is_v21() 0
96 #define nfc_is_v3_2() 0
97 #define nfc_is_v3() nfc_is_v3_2()
98 #define NFC_VERSION "V1"
99 #elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35)
100 #define nfc_is_v1() 0
101 #define nfc_is_v21() 1
102 #define nfc_is_v3_2() 0
103 #define nfc_is_v3() nfc_is_v3_2()
104 #define NFC_VERSION "V2"
105 #elif defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)
106 #define nfc_is_v1() 0
107 #define nfc_is_v21() 0
108 #define nfc_is_v3_2() 1
109 #define nfc_is_v3() nfc_is_v3_2()
110 #define NFC_VERSION "V3"
111 #ifndef CONFIG_MXC_NAND_IP_REGS_BASE
112 #error CONFIG_MXC_NAND_IP_REGS_BASE not defined
115 #error mxc_nand driver not supported on this platform
116 #define NFC_VERSION "unknown"
119 /* Addresses for NFC registers */
120 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
121 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
122 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
123 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
124 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
125 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
126 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
127 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
128 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
129 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
130 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
131 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
132 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
133 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
134 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
135 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
136 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
137 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
138 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
139 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
140 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
141 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
143 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
144 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
145 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
146 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
147 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
148 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
149 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
150 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
151 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
152 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
154 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
157 * Operation modes for the NFC. Valid for v1, v2 and v3
160 #define NFC_CMD (1 << 0)
161 #define NFC_ADDR (1 << 1)
162 #define NFC_INPUT (1 << 2)
163 #define NFC_OUTPUT (1 << 3)
164 #define NFC_ID (1 << 4)
165 #define NFC_STATUS (1 << 5)
167 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
168 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
170 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
171 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
172 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
174 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
176 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
178 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
179 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
180 #define NFC_V3_WRPROT_LOCK (1 << 1)
181 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
182 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
184 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
186 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
187 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
188 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
189 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
190 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
191 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
192 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
193 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
194 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
195 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
196 #define MX53_CONFIG2_PPB(x) (((x) & 0x3) << 8)
197 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
198 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
199 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
200 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
202 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
203 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
204 #define NFC_V3_CONFIG3_FW8 (1 << 3)
205 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
206 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
207 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
208 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
210 #define NFC_V3_IPC (host->regs_ip + 0x2C)
211 #define NFC_V3_IPC_CREQ (1 << 0)
212 #define NFC_V3_IPC_CACK (1 << 1)
213 #define NFC_V3_IPC_INT (1 << 31)
215 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
217 struct mxc_nand_host {
219 struct nand_chip nand;
226 void __iomem *regs_axi;
227 void __iomem *regs_ip;
233 unsigned int buf_start;
236 void (*preset)(struct mtd_info *);
237 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
238 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
239 void (*send_page)(struct mtd_info *, unsigned int);
240 void (*send_read_id)(struct mxc_nand_host *);
241 uint16_t (*get_dev_status)(struct mxc_nand_host *);
242 int (*check_int)(struct mxc_nand_host *);
245 /* OOB placement block for use with hardware ecc generation */
246 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
248 .eccpos = {6, 7, 8, 9, 10},
249 .oobfree = {{0, 5}, {12, 4}, }
252 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
254 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
255 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
256 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
259 /* OOB description for 512 byte pages with 16 byte OOB */
260 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
263 7, 8, 9, 10, 11, 12, 13, 14, 15
266 {.offset = 0, .length = 5}
270 /* OOB description for 2048 byte pages with 64 byte OOB */
271 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
274 7, 8, 9, 10, 11, 12, 13, 14, 15,
275 23, 24, 25, 26, 27, 28, 29, 30, 31,
276 39, 40, 41, 42, 43, 44, 45, 46, 47,
277 55, 56, 57, 58, 59, 60, 61, 62, 63
280 {.offset = 2, .length = 4},
281 {.offset = 16, .length = 7},
282 {.offset = 32, .length = 7},
283 {.offset = 48, .length = 7}
287 /* OOB description for 4096 byte pages with 128 byte OOB */
288 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
291 7, 8, 9, 10, 11, 12, 13, 14, 15,
292 23, 24, 25, 26, 27, 28, 29, 30, 31,
293 39, 40, 41, 42, 43, 44, 45, 46, 47,
294 55, 56, 57, 58, 59, 60, 61, 62, 63,
295 71, 72, 73, 74, 75, 76, 77, 78, 79,
296 87, 88, 89, 90, 91, 92, 93, 94, 95,
297 103, 104, 105, 106, 107, 108, 109, 110, 111,
298 119, 120, 121, 122, 123, 124, 125, 126, 127,
301 {.offset = 2, .length = 4},
302 {.offset = 16, .length = 7},
303 {.offset = 32, .length = 7},
304 {.offset = 48, .length = 7},
305 {.offset = 64, .length = 7},
306 {.offset = 80, .length = 7},
307 {.offset = 96, .length = 7},
308 {.offset = 112, .length = 7},
312 static int check_int_v3(struct mxc_nand_host *host)
316 tmp = readl(NFC_V3_IPC);
317 if (!(tmp & NFC_V3_IPC_INT))
320 tmp &= ~NFC_V3_IPC_INT;
321 writel(tmp, NFC_V3_IPC);
326 static int check_int_v1_v2(struct mxc_nand_host *host)
330 tmp = readw(NFC_V1_V2_CONFIG2);
331 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
334 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
339 /* This function polls the NANDFC to wait for the basic operation to
340 * complete by checking the INT bit of config2 register.
342 static void wait_op_done(struct mxc_nand_host *host, bool useirq)
344 int max_retries = 8000;
346 while (max_retries-- > 0) {
347 if (host->check_int(host))
353 pr_debug("%s: INT not set\n", __func__);
356 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
359 writel(cmd, NFC_V3_FLASH_CMD);
361 /* send out command */
362 writel(NFC_CMD, NFC_V3_LAUNCH);
364 /* Wait for operation to complete */
365 wait_op_done(host, useirq);
368 /* This function issues the specified command to the NAND device and
369 * waits for completion. */
370 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
372 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
374 writew(cmd, NFC_V1_V2_FLASH_CMD);
375 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
377 /* Wait for operation to complete */
378 wait_op_done(host, useirq);
381 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
384 writel(addr, NFC_V3_FLASH_ADDR0);
386 /* send out address */
387 writel(NFC_ADDR, NFC_V3_LAUNCH);
389 wait_op_done(host, islast);
392 /* This function sends an address (or partial address) to the
393 * NAND device. The address is used to select the source/destination for
395 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
397 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
399 writew(addr, NFC_V1_V2_FLASH_ADDR);
400 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
402 /* Wait for operation to complete */
403 wait_op_done(host, islast);
406 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
408 struct nand_chip *nand_chip = mtd->priv;
409 struct mxc_nand_host *host = nand_chip->priv;
412 tmp = readl(NFC_V3_CONFIG1);
414 writel(tmp, NFC_V3_CONFIG1);
416 /* transfer data from NFC ram to nand */
417 writel(ops, NFC_V3_LAUNCH);
419 wait_op_done(host, false);
422 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
424 struct nand_chip *nand_chip = mtd->priv;
425 struct mxc_nand_host *host = nand_chip->priv;
428 if (nfc_is_v1() && mtd->writesize > 512)
433 for (i = 0; i < bufs; i++) {
435 /* NANDFC buffer 0 is used for page read/write */
436 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
438 writew(ops, NFC_V1_V2_CONFIG2);
440 /* Wait for operation to complete */
441 wait_op_done(host, true);
445 static void send_read_id_v3(struct mxc_nand_host *host)
447 /* Read ID into main buffer */
448 writel(NFC_ID, NFC_V3_LAUNCH);
450 wait_op_done(host, true);
452 memcpy(host->data_buf, host->main_area0, 16);
454 pr_debug("read ID %02x %02x %02x %02x\n",
455 host->data_buf[0], host->data_buf[1],
456 host->data_buf[2], host->data_buf[3]);
459 /* Request the NANDFC to perform a read of the NAND device ID. */
460 static void send_read_id_v1_v2(struct mxc_nand_host *host)
462 struct nand_chip *this = &host->nand;
464 /* NANDFC buffer 0 is used for device ID output */
465 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
467 writew(NFC_ID, NFC_V1_V2_CONFIG2);
469 /* Wait for operation to complete */
470 wait_op_done(host, true);
472 memcpy(host->data_buf, host->main_area0, 16);
474 if (this->options & NAND_BUSWIDTH_16) {
475 /* compress the ID info */
476 host->data_buf[1] = host->data_buf[2];
477 host->data_buf[2] = host->data_buf[4];
478 host->data_buf[3] = host->data_buf[6];
479 host->data_buf[4] = host->data_buf[8];
480 host->data_buf[5] = host->data_buf[10];
484 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
486 writel(NFC_STATUS, NFC_V3_LAUNCH);
487 wait_op_done(host, true);
489 return readl(NFC_V3_CONFIG1) >> 16;
492 /* This function requests the NANDFC to perform a read of the
493 * NAND device status and returns the current status. */
494 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
496 void __iomem *main_buf = host->main_area0;
500 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
503 * The device status is stored in main_area0. To
504 * prevent corruption of the buffer save the value
505 * and restore it afterwards.
507 store = readl(main_buf);
509 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
510 wait_op_done(host, true);
512 ret = readw(main_buf);
514 writel(store, main_buf);
519 /* This functions is used by upper layer to checks if device is ready */
520 static int mxc_nand_dev_ready(struct mtd_info *mtd)
523 * NFC handles R/B internally. Therefore, this function
524 * always returns status as ready.
529 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
532 * If HW ECC is enabled, we turn it on during init. There is
533 * no need to enable again here.
537 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
538 u_char *read_ecc, u_char *calc_ecc)
540 struct nand_chip *nand_chip = mtd->priv;
541 struct mxc_nand_host *host = nand_chip->priv;
544 * 1-Bit errors are automatically corrected in HW. No need for
545 * additional correction. 2-Bit errors cannot be corrected by
546 * HW ECC, so we need to return failure
548 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
550 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
551 printk("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
558 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
559 u_char *read_ecc, u_char *calc_ecc)
561 struct nand_chip *nand_chip = mtd->priv;
562 struct mxc_nand_host *host = nand_chip->priv;
566 u8 ecc_bit_mask, err_limit;
568 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
569 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
571 no_subpages = mtd->writesize >> 9;
574 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
576 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
579 err = ecc_stat & ecc_bit_mask;
580 if (err > err_limit) {
581 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
587 } while (--no_subpages);
589 mtd->ecc_stats.corrected += ret;
591 pr_debug("%d Symbol Correctable RS-ECC Errors\n", ret);
596 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
602 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
604 struct nand_chip *nand_chip = mtd->priv;
605 struct mxc_nand_host *host = nand_chip->priv;
608 /* Check for status request */
609 if (host->status_request)
610 return host->get_dev_status(host) & 0xFF;
612 ret = *(uint8_t *)(host->data_buf + host->buf_start);
618 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
620 struct nand_chip *nand_chip = mtd->priv;
621 struct mxc_nand_host *host = nand_chip->priv;
624 ret = *(uint16_t *)(host->data_buf + host->buf_start);
625 host->buf_start += 2;
630 /* Write data of length len to buffer buf. The data to be
631 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
632 * Operation by the NFC, the data is written to NAND Flash */
633 static void mxc_nand_write_buf(struct mtd_info *mtd,
634 const u_char *buf, int len)
636 struct nand_chip *nand_chip = mtd->priv;
637 struct mxc_nand_host *host = nand_chip->priv;
638 u16 col = host->buf_start;
639 int n = mtd->oobsize + mtd->writesize - col;
643 memcpy(host->data_buf + col, buf, n);
645 host->buf_start += n;
648 /* Read the data buffer from the NAND Flash. To read the data from NAND
649 * Flash first the data output cycle is initiated by the NFC, which copies
650 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
652 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
654 struct nand_chip *nand_chip = mtd->priv;
655 struct mxc_nand_host *host = nand_chip->priv;
656 u16 col = host->buf_start;
657 int n = mtd->oobsize + mtd->writesize - col;
661 memcpy(buf, host->data_buf + col, n);
663 host->buf_start += n;
666 #if defined(__UBOOT__) && defined(CONFIG_MTD_NAND_VERIFY_WRITE)
667 /* Used by the upper layer to verify the data in NAND Flash
668 * with the data in the buf. */
669 static int mxc_nand_verify_buf(struct mtd_info *mtd,
670 const u_char *buf, int len)
676 /* This function is used by upper layer for select and
677 * deselect of the NAND chip */
678 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
680 struct nand_chip *nand_chip = mtd->priv;
681 struct mxc_nand_host *host = nand_chip->priv;
684 host->active_cs = chip;
685 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
690 * Function to transfer data to/from spare area.
692 static void copy_spare(struct mtd_info *mtd, bool bfrom)
694 struct nand_chip *this = mtd->priv;
695 struct mxc_nand_host *host = this->priv;
697 u16 n = mtd->writesize >> 9;
698 u8 *d = host->data_buf + mtd->writesize;
699 u8 *s = host->spare0;
700 u16 t = host->spare_len;
702 j = (mtd->oobsize / n >> 1) << 1;
705 for (i = 0; i < n - 1; i++)
706 memcpy(d + i * j, s + i * t, j);
708 /* the last section */
709 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
711 for (i = 0; i < n - 1; i++)
712 memcpy(&s[i * t], &d[i * j], j);
714 /* the last section */
715 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
719 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
721 struct nand_chip *nand_chip = mtd->priv;
722 struct mxc_nand_host *host = nand_chip->priv;
724 /* Write out column address, if necessary */
727 * MXC NANDFC can only perform full page+spare or
728 * spare-only read/write. When the upper layers
729 * perform a read/write buf operation, the saved column
730 * address is used to index into the full page.
732 host->send_addr(host, 0, page_addr == -1);
733 if (mtd->writesize > 512)
734 /* another col addr cycle for 2k page */
735 host->send_addr(host, 0, false);
738 /* Write out page address, if necessary */
739 if (page_addr != -1) {
740 /* paddr_0 - p_addr_7 */
741 host->send_addr(host, (page_addr & 0xff), false);
743 if (mtd->writesize > 512) {
744 if (mtd->size >= 0x10000000) {
745 /* paddr_8 - paddr_15 */
746 host->send_addr(host, (page_addr >> 8) & 0xff, false);
747 host->send_addr(host, (page_addr >> 16) & 0xff, true);
749 /* paddr_8 - paddr_15 */
750 host->send_addr(host, (page_addr >> 8) & 0xff, true);
752 /* One more address cycle for higher density devices */
753 if (mtd->size >= 0x4000000) {
754 /* paddr_8 - paddr_15 */
755 host->send_addr(host, (page_addr >> 8) & 0xff, false);
756 host->send_addr(host, (page_addr >> 16) & 0xff, true);
758 /* paddr_8 - paddr_15 */
759 host->send_addr(host, (page_addr >> 8) & 0xff, true);
765 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
766 * on how much oob the nand chip has. For 8bit ecc we need at least
767 * 26 bytes of oob data per 512 byte block.
769 static int get_eccsize(struct mtd_info *mtd)
771 int oobbytes_per_512 = 0;
773 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
775 if (oobbytes_per_512 < 26)
781 static void preset_v1_v2(struct mtd_info *mtd)
783 struct nand_chip *nand_chip = mtd->priv;
784 struct mxc_nand_host *host = nand_chip->priv;
785 uint16_t config1 = 0;
787 if (nand_chip->ecc.mode == NAND_ECC_HW)
788 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
791 config1 |= NFC_V2_CONFIG1_FP_INT;
793 if (nfc_is_v21() && mtd->writesize) {
794 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
796 host->eccsize = get_eccsize(mtd);
797 if (host->eccsize == 4)
798 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
800 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
805 writew(config1, NFC_V1_V2_CONFIG1);
806 /* preset operation */
808 /* Unlock the internal RAM Buffer */
809 writew(0x2, NFC_V1_V2_CONFIG);
811 /* Blocks to be unlocked */
813 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
814 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
815 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
816 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
817 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
818 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
819 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
820 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
821 } else if (nfc_is_v1()) {
822 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
823 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
827 /* Unlock Block Command for given address range */
828 writew(0x4, NFC_V1_V2_WRPROT);
831 static void preset_v3(struct mtd_info *mtd)
833 struct nand_chip *chip = mtd->priv;
834 struct mxc_nand_host *host = chip->priv;
835 uint32_t config2, config3;
838 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
839 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
840 WARN_ON(!(readl(NFC_V3_IPC) & NFC_V3_IPC_CACK));
842 /* Unlock the internal RAM Buffer */
843 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
846 /* Blocks to be unlocked */
847 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++)
848 writel(0x0 | (0xffff << 16),
849 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
851 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
852 NFC_V3_CONFIG2_2CMD_PHASES |
853 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
854 NFC_V3_CONFIG2_ST_CMD(0x70) |
855 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
857 if (chip->ecc.mode == NAND_ECC_HW)
858 config2 |= NFC_V3_CONFIG2_ECC_EN;
860 addr_phases = fls(chip->pagemask) >> 3;
862 if (mtd->writesize == 2048) {
863 config2 |= NFC_V3_CONFIG2_PS_2048;
864 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
865 } else if (mtd->writesize == 4096) {
866 config2 |= NFC_V3_CONFIG2_PS_4096;
867 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
869 config2 |= NFC_V3_CONFIG2_PS_512;
870 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
873 if (mtd->writesize) {
874 #if defined CONFIG_SOC_MX53
875 config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
877 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
879 host->eccsize = get_eccsize(mtd);
880 if (host->eccsize == 8)
881 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
884 writel(config2, NFC_V3_CONFIG2);
886 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
887 NFC_V3_CONFIG3_NO_SDMA |
888 NFC_V3_CONFIG3_RBB_MODE |
889 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
890 NFC_V3_CONFIG3_ADD_OP(0);
892 if (!(chip->options & NAND_BUSWIDTH_16))
893 config3 |= NFC_V3_CONFIG3_FW8;
895 writel(config3, NFC_V3_CONFIG3);
897 writel(0, NFC_V3_DELAY_LINE);
898 writel(0, NFC_V3_IPC);
901 /* Used by the upper layer to write command to NAND Flash for
902 * different operations to be carried out on NAND Flash */
903 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
904 int column, int page_addr)
906 struct nand_chip *nand_chip = mtd->priv;
907 struct mxc_nand_host *host = nand_chip->priv;
909 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
910 command, column, page_addr);
912 /* Reset command state information */
913 host->status_request = false;
915 /* Command pre-processing step */
919 host->send_cmd(host, command, false);
922 case NAND_CMD_STATUS:
924 host->status_request = true;
926 host->send_cmd(host, command, true);
927 mxc_do_addr_cycle(mtd, column, page_addr);
931 case NAND_CMD_READOOB:
932 if (command == NAND_CMD_READ0)
933 host->buf_start = column;
935 host->buf_start = column + mtd->writesize;
937 command = NAND_CMD_READ0; /* only READ0 is valid */
939 host->send_cmd(host, command, false);
940 mxc_do_addr_cycle(mtd, column, page_addr);
942 if (mtd->writesize > 512)
943 host->send_cmd(host, NAND_CMD_READSTART, true);
945 host->send_page(mtd, NFC_OUTPUT);
947 memcpy(host->data_buf, host->main_area0, mtd->writesize);
948 copy_spare(mtd, true);
952 if (column >= mtd->writesize)
953 /* call ourself to read a page */
954 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
956 host->buf_start = column;
958 host->send_cmd(host, command, false);
959 mxc_do_addr_cycle(mtd, column, page_addr);
962 case NAND_CMD_PAGEPROG:
963 memcpy(host->main_area0, host->data_buf, mtd->writesize);
964 copy_spare(mtd, false);
965 host->send_page(mtd, NFC_INPUT);
966 host->send_cmd(host, command, true);
967 mxc_do_addr_cycle(mtd, column, page_addr);
970 case NAND_CMD_READID:
971 host->send_cmd(host, command, true);
972 mxc_do_addr_cycle(mtd, column, page_addr);
973 host->send_read_id(host);
974 host->buf_start = column;
977 case NAND_CMD_ERASE1:
978 case NAND_CMD_ERASE2:
979 host->send_cmd(host, command, false);
980 mxc_do_addr_cycle(mtd, column, page_addr);
987 * The generic flash bbt decriptors overlap with our ecc
988 * hardware, so define some i.MX specific ones.
990 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
991 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
993 static struct nand_bbt_descr bbt_main_descr = {
994 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
995 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1000 .pattern = bbt_pattern,
1003 static struct nand_bbt_descr bbt_mirror_descr = {
1004 .options = NAND_BBT_LASTBLOCK | NAND_BBT_WRITE |
1005 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1010 .pattern = mirror_pattern,
1013 static void mxc_nand_chip_init(int devno)
1016 struct nand_chip *this;
1017 struct mtd_info *mtd = &nand_info[devno];
1018 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1020 /* allocate a minimal buffer for the read_id command */
1021 host->data_buf = malloc(16);
1022 if (!host->data_buf) {
1023 printk("Failed to allocate ID buffer\n");
1027 /* structures must be linked */
1031 mtd->name = DRIVER_NAME;
1033 /* 50 us command delay time */
1034 this->chip_delay = 5;
1037 this->dev_ready = mxc_nand_dev_ready;
1038 this->cmdfunc = mxc_nand_command;
1039 this->select_chip = mxc_nand_select_chip;
1040 this->read_byte = mxc_nand_read_byte;
1041 this->read_word = mxc_nand_read_word;
1042 this->write_buf = mxc_nand_write_buf;
1043 this->read_buf = mxc_nand_read_buf;
1044 #if defined(__UBOOT__) && defined(CONFIG_MTD_NAND_VERIFY_WRITE)
1045 this->verify_buf = mxc_nand_verify_buf;
1047 host->base = (void __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1052 host->main_area0 = host->base;
1054 if (nfc_is_v1() || nfc_is_v21()) {
1055 host->preset = preset_v1_v2;
1056 host->send_cmd = send_cmd_v1_v2;
1057 host->send_addr = send_addr_v1_v2;
1058 host->send_page = send_page_v1_v2;
1059 host->send_read_id = send_read_id_v1_v2;
1060 host->get_dev_status = get_dev_status_v1_v2;
1061 host->check_int = check_int_v1_v2;
1065 host->regs = host->base + 0x1e00;
1066 host->spare0 = host->base + 0x1000;
1067 host->spare_len = 64;
1068 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1069 oob_largepage = &nandv2_hw_eccoob_largepage;
1070 this->ecc.bytes = 9;
1071 } else if (nfc_is_v1()) {
1072 host->regs = host->base + 0xe00;
1073 host->spare0 = host->base + 0x800;
1074 host->spare_len = 16;
1075 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1076 oob_largepage = &nandv1_hw_eccoob_largepage;
1077 this->ecc.bytes = 3;
1079 } else if (nfc_is_v3_2()) {
1080 host->regs_ip = (void __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1081 host->regs_axi = host->base + 0x1e00;
1082 host->spare0 = host->base + 0x1000;
1083 host->spare_len = 64;
1084 host->preset = preset_v3;
1085 host->send_cmd = send_cmd_v3;
1086 host->send_addr = send_addr_v3;
1087 host->send_page = send_page_v3;
1088 host->send_read_id = send_read_id_v3;
1089 host->check_int = check_int_v3;
1090 host->get_dev_status = get_dev_status_v3;
1091 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1092 oob_largepage = &nandv2_hw_eccoob_largepage;
1093 this->ecc.strength = 4;
1097 this->ecc.size = 512;
1098 this->ecc.layout = oob_smallpage;
1100 #ifdef CONFIG_MXC_NAND_HWECC
1101 this->ecc.calculate = mxc_nand_calculate_ecc;
1102 this->ecc.hwctl = mxc_nand_enable_hwecc;
1104 this->ecc.correct = mxc_nand_correct_data_v1;
1106 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1107 this->ecc.mode = NAND_ECC_HW;
1109 this->ecc.mode = NAND_ECC_SOFT;
1111 /* NAND bus width determines access funtions used by upper layer */
1112 if (is_16bit_nand())
1113 this->options |= NAND_BUSWIDTH_16;
1115 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1116 this->bbt_options |= NAND_BBT_USE_FLASH;
1117 this->bbt_td = &bbt_main_descr;
1118 this->bbt_md = &bbt_mirror_descr;
1119 this->bbt_td->options |= NAND_BBT_CREATE;
1120 this->bbt_md->options |= NAND_BBT_CREATE;
1123 /* first scan to find the device and get the page size */
1124 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1128 host->data_buf = realloc(host->data_buf,
1129 mtd->writesize + mtd->oobsize);
1130 if (!host->data_buf) {
1131 printk("Failed to allocate data buffer of %u byte\n",
1132 mtd->writesize + mtd->oobsize);
1135 pr_debug("Allocated %u byte data buffer\n",
1136 mtd->writesize + mtd->oobsize);
1138 /* Call preset again, with correct writesize this time */
1141 if (mtd->writesize == 2048)
1142 this->ecc.layout = oob_largepage;
1143 if (nfc_is_v21() && mtd->writesize == 4096)
1144 this->ecc.layout = &nandv2_hw_eccoob_4k;
1146 /* second phase scan */
1147 err = nand_scan_tail(mtd);
1149 printk("Nand scan failed: %d\n", err);
1153 err = nand_register(devno);
1158 void board_nand_init(void)
1162 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1163 mxc_nand_chip_init(i);