2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/types.h>
22 #include <asm/errno.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/imx-common/regs-bch.h>
27 #include <asm/imx-common/regs-gpmi.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/imx-common/dma.h>
31 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
33 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
34 #if defined(CONFIG_MX6)
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
39 #define MXS_NAND_METADATA_SIZE 10
41 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
43 /* BCH timeout in microseconds */
44 #define MXS_NAND_BCH_TIMEOUT 10000
46 static struct bch_regs *bch_regs = (void *)BCH_BASE_ADDRESS;
47 static struct gpmi_regs *gpmi_regs = (void *)GPMI_BASE_ADDRESS;
48 struct mxs_nand_info {
51 uint32_t cmd_queue_len;
52 uint32_t data_buf_size;
58 uint8_t marking_block_bad;
61 /* Functions with altered behaviour */
62 int (*hooked_read_oob)(struct mtd_info *mtd,
63 loff_t from, struct mtd_oob_ops *ops);
64 int (*hooked_write_oob)(struct mtd_info *mtd,
65 loff_t to, struct mtd_oob_ops *ops);
66 int (*hooked_block_markbad)(struct mtd_info *mtd,
70 struct mxs_dma_desc **desc;
75 #define dump_reg(b, r) __dump_reg(&b->r, #r)
76 static inline void __dump_reg(void *addr, const char *name)
78 printf("%16s[%p]=%08x\n", name, addr, readl(addr));
81 #define dump_bch_reg(n) __dump_reg(&bch_regs->hw_bch_##n, #n)
82 #define dump_gpmi_reg(n) __dump_reg(&gpmi_regs->hw_gpmi_##n, #n)
83 static inline void dump_regs(void)
87 dump_bch_reg(status0);
90 dump_bch_reg(dbgkesread);
91 dump_bch_reg(dbgcsferead);
92 dump_bch_reg(dbgsyndegread);
93 dump_bch_reg(dbgahbmread);
94 dump_bch_reg(blockname);
95 dump_bch_reg(version);
99 dump_gpmi_reg(eccctrl);
100 dump_gpmi_reg(ecccount);
101 dump_gpmi_reg(payload);
102 dump_gpmi_reg(auxiliary);
103 dump_gpmi_reg(ctrl1);
106 dump_gpmi_reg(debug);
107 dump_gpmi_reg(version);
108 dump_gpmi_reg(debug2);
109 dump_gpmi_reg(debug3);
112 static inline int dbg_addr(void *addr)
114 if (((unsigned long)addr & ~0xfff) == BCH_BASE_ADDRESS)
119 static inline u32 mxs_readl(void *addr,
120 const char *fn, int ln)
122 u32 val = readl(addr);
123 static void *last_addr;
129 if (addr != last_addr || last_val != val) {
130 printf("%s@%d: Read %08x from %p\n", fn, ln, val, addr);
137 static inline void mxs_writel(u32 val, void *addr,
138 const char *fn, int ln)
141 printf("%s@%d: Writing %08x to %p...", fn, ln, val, addr);
144 printf(" result: %08x\n", readl(addr));
148 #define readl(a) mxs_readl(a, __func__, __LINE__)
151 #define writel(v, a) mxs_writel(v, a, __func__, __LINE__)
152 static inline void memdump(const void *addr, size_t len)
154 const char *buf = addr;
157 for (i = 0; i < len; i++) {
161 printf("%p:", &buf[i]);
163 printf(" %02x", buf[i]);
168 static inline void memdump(void *addr, size_t len)
172 static inline void dump_regs(void)
177 struct nand_ecclayout fake_ecc_layout;
180 * Cache management functions
182 #ifndef CONFIG_SYS_DCACHE_OFF
183 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
185 uint32_t addr = (uint32_t)info->data_buf;
187 flush_dcache_range(addr, addr + info->data_buf_size);
190 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
192 uint32_t addr = (uint32_t)info->data_buf;
194 invalidate_dcache_range(addr, addr + info->data_buf_size);
197 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
199 uint32_t addr = (uint32_t)info->cmd_buf;
201 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
204 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
205 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
206 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
209 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
211 struct mxs_dma_desc *desc;
213 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
214 printf("MXS NAND: Too many DMA descriptors requested\n");
218 desc = info->desc[info->desc_index];
224 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
227 struct mxs_dma_desc *desc;
229 for (i = 0; i < info->desc_index; i++) {
230 desc = info->desc[i];
231 memset(desc, 0, sizeof(struct mxs_dma_desc));
232 desc->address = (dma_addr_t)desc;
235 info->desc_index = 0;
238 static uint32_t mxs_nand_ecc_chunk_cnt(struct mtd_info *mtd)
240 struct nand_chip *nand = mtd->priv;
241 return mtd->writesize / nand->ecc.size;
244 static inline uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
246 return ecc_strength * 13;
249 static uint32_t mxs_nand_aux_status_offset(void)
251 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
254 static int mxs_nand_gpmi_init(void)
258 /* Reset the GPMI block. */
259 ret = mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
264 * Choose NAND mode, set IRQ polarity, disable write protection and
267 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
268 GPMI_CTRL1_GPMI_MODE,
269 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
270 GPMI_CTRL1_BCH_MODE);
271 writel(0x500 << 16, &gpmi_regs->hw_gpmi_timing1);
275 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
276 uint32_t page_oob_size)
278 if (page_data_size == 2048)
281 if (page_data_size == 4096) {
282 if (page_oob_size == 128)
285 if (page_oob_size == 218)
292 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
293 uint32_t ecc_strength)
295 uint32_t chunk_data_size_in_bits;
296 uint32_t chunk_ecc_size_in_bits;
297 uint32_t chunk_total_size_in_bits;
298 uint32_t block_mark_chunk_number;
299 uint32_t block_mark_chunk_bit_offset;
300 uint32_t block_mark_bit_offset;
302 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
303 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
305 chunk_total_size_in_bits =
306 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
308 /* Compute the bit offset of the block mark within the physical page. */
309 block_mark_bit_offset = page_data_size * 8;
311 /* Subtract the metadata bits. */
312 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
315 * Compute the chunk number (starting at zero) in which the block mark
318 block_mark_chunk_number =
319 block_mark_bit_offset / chunk_total_size_in_bits;
322 * Compute the bit offset of the block mark within its chunk, and
325 block_mark_chunk_bit_offset = block_mark_bit_offset -
326 (block_mark_chunk_number * chunk_total_size_in_bits);
328 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
332 * Now that we know the chunk number in which the block mark appears,
333 * we can subtract all the ECC bits that appear before it.
335 block_mark_bit_offset -=
336 block_mark_chunk_number * chunk_ecc_size_in_bits;
338 return block_mark_bit_offset;
341 static inline uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
343 uint32_t ecc_strength;
344 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
345 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
348 static inline uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
350 uint32_t ecc_strength;
351 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
352 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
356 * Wait for BCH complete IRQ and clear the IRQ
358 static int mxs_nand_wait_for_bch_complete(void)
360 int timeout = MXS_NAND_BCH_TIMEOUT;
363 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
364 BCH_CTRL_COMPLETE_IRQ, timeout);
366 debug("%s@%d: %d\n", __func__, __LINE__, ret);
367 mxs_nand_gpmi_init();
370 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
376 * This is the function that we install in the cmd_ctrl function pointer of the
377 * owning struct nand_chip. The only functions in the reference implementation
378 * that use these functions pointers are cmdfunc and select_chip.
380 * In this driver, we implement our own select_chip, so this function will only
381 * be called by the reference implementation's cmdfunc. For this reason, we can
382 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
385 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
387 struct nand_chip *nand = mtd->priv;
388 struct mxs_nand_info *nand_info = nand->priv;
389 struct mxs_dma_desc *d;
390 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
394 * If this condition is true, something is _VERY_ wrong in MTD
397 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
398 printf("MXS NAND: Command queue too long\n");
403 * Every operation begins with a command byte and a series of zero or
404 * more address bytes. These are distinguished by either the Address
405 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
406 * asserted. When MTD is ready to execute the command, it will
407 * deasert both latch enables.
409 * Rather than run a separate DMA operation for every single byte, we
410 * queue them up and run a single DMA operation for the entire series
411 * of command and data bytes.
413 if (ctrl & (NAND_ALE | NAND_CLE)) {
414 if (data != NAND_CMD_NONE)
415 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
420 * If control arrives here, MTD has deasserted both the ALE and CLE,
421 * which means it's ready to run an operation. Check if we have any
424 if (nand_info->cmd_queue_len == 0)
427 /* Compile the DMA descriptor -- a descriptor that sends command. */
428 d = mxs_nand_get_dma_desc(nand_info);
430 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
431 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
432 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
433 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
435 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
437 d->cmd.pio_words[0] =
438 GPMI_CTRL0_COMMAND_MODE_WRITE |
439 GPMI_CTRL0_WORD_LENGTH |
440 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
441 GPMI_CTRL0_ADDRESS_NAND_CLE |
442 GPMI_CTRL0_ADDRESS_INCREMENT |
443 nand_info->cmd_queue_len;
445 mxs_dma_desc_append(channel, d);
448 mxs_nand_flush_cmd_buf(nand_info);
450 /* Execute the DMA chain. */
451 ret = mxs_dma_go(channel);
455 printf("MXS NAND: Error sending command %08lx\n", d->cmd.pio_words[0]);
456 for (i = 0; i < nand_info->cmd_queue_len; i++) {
457 printf("%02x ", nand_info->cmd_buf[i]);
462 mxs_nand_return_dma_descs(nand_info);
464 /* Reset the command queue. */
465 nand_info->cmd_queue_len = 0;
469 * Test if the NAND flash is ready.
471 static int mxs_nand_device_ready(struct mtd_info *mtd)
473 struct nand_chip *chip = mtd->priv;
474 struct mxs_nand_info *nand_info = chip->priv;
477 tmp = readl(&gpmi_regs->hw_gpmi_stat);
478 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
484 * Select the NAND chip.
486 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
488 struct nand_chip *nand = mtd->priv;
489 struct mxs_nand_info *nand_info = nand->priv;
491 nand_info->cur_chip = chip;
495 * Handle block mark swapping.
497 * Note that, when this function is called, it doesn't know whether it's
498 * swapping the block mark, or swapping it *back* -- but it doesn't matter
499 * because the the operation is the same.
501 #ifndef CONFIG_NAND_MXS_NO_BBM_SWAP
502 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
503 uint8_t *data_buf, uint8_t *oob_buf)
511 bit_offset = mxs_nand_mark_bit_offset(mtd);
512 buf_offset = mxs_nand_mark_byte_offset(mtd);
515 * Get the byte from the data area that overlays the block mark. Since
516 * the ECC engine applies its own view to the bits in the page, the
517 * physical block mark won't (in general) appear on a byte boundary in
520 src = data_buf[buf_offset] >> bit_offset;
521 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
525 debug("Swapping byte %02x @ %03x.%d with %02x @ %03x\n",
526 src & 0xff, buf_offset, bit_offset, dst & 0xff, 0);
530 data_buf[buf_offset] &= ~(0xff << bit_offset);
531 data_buf[buf_offset + 1] &= 0xff << bit_offset;
533 data_buf[buf_offset] |= dst << bit_offset;
534 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
537 static inline void mxs_nand_swap_block_mark(struct mtd_info *mtd,
538 uint8_t *data_buf, uint8_t *oob_buf)
544 * Read data from NAND.
546 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
548 struct nand_chip *nand = mtd->priv;
549 struct mxs_nand_info *nand_info = nand->priv;
550 struct mxs_dma_desc *d;
551 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
554 if (length > NAND_MAX_PAGESIZE) {
555 printf("MXS NAND: DMA buffer too big\n");
560 printf("MXS NAND: DMA buffer is NULL\n");
564 memset(buf, 0xee, length);
566 /* Compile the DMA descriptor - a descriptor that reads data. */
567 d = mxs_nand_get_dma_desc(nand_info);
569 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
570 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
571 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
572 (length << MXS_DMA_DESC_BYTES_OFFSET);
574 d->cmd.address = (dma_addr_t)nand_info->data_buf;
576 d->cmd.pio_words[0] =
577 GPMI_CTRL0_COMMAND_MODE_READ |
578 GPMI_CTRL0_WORD_LENGTH |
579 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
580 GPMI_CTRL0_ADDRESS_NAND_DATA |
583 mxs_dma_desc_append(channel, d);
586 * A DMA descriptor that waits for the command to end and the chip to
589 * I think we actually should *not* be waiting for the chip to become
590 * ready because, after all, we don't care. I think the original code
591 * did that and no one has re-thought it yet.
593 d = mxs_nand_get_dma_desc(nand_info);
595 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
596 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
597 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
601 d->cmd.pio_words[0] =
602 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
603 GPMI_CTRL0_WORD_LENGTH |
604 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
605 GPMI_CTRL0_ADDRESS_NAND_DATA;
607 mxs_dma_desc_append(channel, d);
609 /* Execute the DMA chain. */
610 ret = mxs_dma_go(channel);
612 printf("%s: DMA read error\n", __func__);
616 /* Invalidate caches */
617 mxs_nand_inval_data_buf(nand_info);
619 memcpy(buf, nand_info->data_buf, length);
622 mxs_nand_return_dma_descs(nand_info);
626 * Write data to NAND.
628 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
631 struct nand_chip *nand = mtd->priv;
632 struct mxs_nand_info *nand_info = nand->priv;
633 struct mxs_dma_desc *d;
634 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
637 if (length > NAND_MAX_PAGESIZE) {
638 printf("MXS NAND: DMA buffer too big\n");
643 printf("MXS NAND: DMA buffer is NULL\n");
647 memcpy(nand_info->data_buf, buf, length);
649 /* Compile the DMA descriptor - a descriptor that writes data. */
650 d = mxs_nand_get_dma_desc(nand_info);
652 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
653 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
654 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
655 (length << MXS_DMA_DESC_BYTES_OFFSET);
657 d->cmd.address = (dma_addr_t)nand_info->data_buf;
659 d->cmd.pio_words[0] =
660 GPMI_CTRL0_COMMAND_MODE_WRITE |
661 GPMI_CTRL0_WORD_LENGTH |
662 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
663 GPMI_CTRL0_ADDRESS_NAND_DATA |
666 mxs_dma_desc_append(channel, d);
669 mxs_nand_flush_data_buf(nand_info);
671 /* Execute the DMA chain. */
672 ret = mxs_dma_go(channel);
674 printf("%s: DMA write error\n", __func__);
676 mxs_nand_return_dma_descs(nand_info);
680 * Read a single byte from NAND.
682 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
685 mxs_nand_read_buf(mtd, &buf, 1);
689 static void flush_buffers(struct mtd_info *mtd, struct mxs_nand_info *nand_info)
691 flush_dcache_range((unsigned long)nand_info->data_buf,
692 (unsigned long)nand_info->data_buf +
694 flush_dcache_range((unsigned long)nand_info->oob_buf,
695 (unsigned long)nand_info->oob_buf +
700 * Read a page from NAND.
702 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
703 uint8_t *buf, int oob_required,
706 struct mxs_nand_info *nand_info = nand->priv;
707 struct mxs_dma_desc *d;
708 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
709 uint32_t corrected = 0, failed = 0;
713 /* Compile the DMA descriptor - wait for ready. */
714 d = mxs_nand_get_dma_desc(nand_info);
716 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
717 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
718 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
722 d->cmd.pio_words[0] =
723 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
724 GPMI_CTRL0_WORD_LENGTH |
725 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
726 GPMI_CTRL0_ADDRESS_NAND_DATA;
728 mxs_dma_desc_append(channel, d);
730 /* Compile the DMA descriptor - enable the BCH block and read. */
731 d = mxs_nand_get_dma_desc(nand_info);
733 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
734 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
738 d->cmd.pio_words[0] =
739 GPMI_CTRL0_COMMAND_MODE_READ |
740 GPMI_CTRL0_WORD_LENGTH |
741 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
742 GPMI_CTRL0_ADDRESS_NAND_DATA |
743 (mtd->writesize + mtd->oobsize);
744 d->cmd.pio_words[1] = 0;
745 d->cmd.pio_words[2] =
746 GPMI_ECCCTRL_ENABLE_ECC |
747 GPMI_ECCCTRL_ECC_CMD_DECODE |
748 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
749 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
750 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
751 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
753 flush_buffers(mtd, nand_info);
755 mxs_dma_desc_append(channel, d);
757 /* Compile the DMA descriptor - disable the BCH block. */
758 d = mxs_nand_get_dma_desc(nand_info);
760 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
761 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
762 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
766 d->cmd.pio_words[0] =
767 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
768 GPMI_CTRL0_WORD_LENGTH |
769 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
770 GPMI_CTRL0_ADDRESS_NAND_DATA |
771 (mtd->writesize + mtd->oobsize);
772 d->cmd.pio_words[1] = 0;
773 d->cmd.pio_words[2] = 0;
775 mxs_dma_desc_append(channel, d);
777 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
778 d = mxs_nand_get_dma_desc(nand_info);
780 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
781 MXS_DMA_DESC_DEC_SEM;
785 mxs_dma_desc_append(channel, d);
787 /* Execute the DMA chain. */
788 ret = mxs_dma_go(channel);
790 printf("%s: DMA read error\n", __func__);
794 ret = mxs_nand_wait_for_bch_complete();
796 printf("MXS NAND: BCH read timeout\n");
800 /* Invalidate caches */
801 mxs_nand_inval_data_buf(nand_info);
803 /* Read DMA completed, now do the mark swapping. */
804 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
806 /* Loop over status bytes, accumulating ECC status. */
807 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
808 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd); i++) {
809 if (status[i] == 0x00)
812 if (status[i] == 0xff)
815 if (status[i] == 0xfe) {
820 corrected += status[i];
823 /* Propagate ECC status to the owning MTD. */
824 mtd->ecc_stats.failed += failed;
825 mtd->ecc_stats.corrected += corrected;
828 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
829 * details about our policy for delivering the OOB.
831 * We fill the caller's buffer with set bits, and then copy the block
832 * mark to the caller's buffer. Note that, if block mark swapping was
833 * necessary, it has already been done, so we can rely on the first
834 * byte of the auxiliary buffer to contain the block mark.
836 memset(nand->oob_poi, 0xff, mtd->oobsize);
838 nand->oob_poi[0] = nand_info->oob_buf[0];
840 memcpy(buf, nand_info->data_buf, mtd->writesize);
843 mxs_nand_return_dma_descs(nand_info);
849 * Write a page to NAND.
851 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
852 struct nand_chip *nand, const uint8_t *buf,
855 struct mxs_nand_info *nand_info = nand->priv;
856 struct mxs_dma_desc *d;
857 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
860 memcpy(nand_info->data_buf, buf, mtd->writesize);
861 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
863 /* Handle block mark swapping. */
864 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
866 /* Compile the DMA descriptor - write data. */
867 d = mxs_nand_get_dma_desc(nand_info);
869 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
870 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
871 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
875 d->cmd.pio_words[0] =
876 GPMI_CTRL0_COMMAND_MODE_WRITE |
877 GPMI_CTRL0_WORD_LENGTH |
878 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
879 GPMI_CTRL0_ADDRESS_NAND_DATA;
880 d->cmd.pio_words[1] = 0;
881 d->cmd.pio_words[2] =
882 GPMI_ECCCTRL_ENABLE_ECC |
883 GPMI_ECCCTRL_ECC_CMD_ENCODE |
884 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
885 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
886 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
887 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
889 flush_buffers(mtd, nand_info);
891 mxs_dma_desc_append(channel, d);
894 mxs_nand_flush_data_buf(nand_info);
896 /* Execute the DMA chain. */
897 ret = mxs_dma_go(channel);
899 printf("%s: DMA write error\n", __func__);
903 ret = mxs_nand_wait_for_bch_complete();
905 printf("%s: BCH write timeout\n", __func__);
910 mxs_nand_return_dma_descs(nand_info);
915 * Read OOB from NAND.
917 * This function is a veneer that replaces the function originally installed by
918 * the NAND Flash MTD code.
920 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
921 struct mtd_oob_ops *ops)
923 struct nand_chip *chip = mtd->priv;
924 struct mxs_nand_info *nand_info = chip->priv;
927 if (ops->mode == MTD_OPS_RAW)
928 nand_info->raw_oob_mode = 1;
930 nand_info->raw_oob_mode = 0;
932 ret = nand_info->hooked_read_oob(mtd, from, ops);
934 nand_info->raw_oob_mode = 0;
942 * This function is a veneer that replaces the function originally installed by
943 * the NAND Flash MTD code.
945 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
946 struct mtd_oob_ops *ops)
948 struct nand_chip *chip = mtd->priv;
949 struct mxs_nand_info *nand_info = chip->priv;
952 if (ops->mode == MTD_OPS_RAW)
953 nand_info->raw_oob_mode = 1;
955 nand_info->raw_oob_mode = 0;
957 ret = nand_info->hooked_write_oob(mtd, to, ops);
959 nand_info->raw_oob_mode = 0;
965 * Mark a block bad in NAND.
967 * This function is a veneer that replaces the function originally installed by
968 * the NAND Flash MTD code.
970 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
972 struct nand_chip *chip = mtd->priv;
973 struct mxs_nand_info *nand_info = chip->priv;
976 nand_info->marking_block_bad = 1;
978 ret = nand_info->hooked_block_markbad(mtd, ofs);
980 nand_info->marking_block_bad = 0;
986 * There are several places in this driver where we have to handle the OOB and
987 * block marks. This is the function where things are the most complicated, so
988 * this is where we try to explain it all. All the other places refer back to
991 * These are the rules, in order of decreasing importance:
993 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
994 * write operations take measures to protect it.
996 * 2) In read operations, the first byte of the OOB we return must reflect the
997 * true state of the block mark, no matter where that block mark appears in
1000 * 3) ECC-based read operations return an OOB full of set bits (since we never
1001 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1004 * 4) "Raw" read operations return a direct view of the physical bytes in the
1005 * page, using the conventional definition of which bytes are data and which
1006 * are OOB. This gives the caller a way to see the actual, physical bytes
1007 * in the page, without the distortions applied by our ECC engine.
1009 * What we do for this specific read operation depends on whether we're doing
1010 * "raw" read, or an ECC-based read.
1012 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1013 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1014 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1015 * ECC-based or raw view of the page is implicit in which function it calls
1016 * (there is a similar pair of ECC-based/raw functions for writing).
1018 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
1019 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
1020 * caller wants an ECC-based or raw view of the page is not propagated down to
1023 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
1024 * ecc.read_oob and ecc.write_oob function pointers in the owning
1025 * struct mtd_info with our own functions. These hook functions set the
1026 * raw_oob_mode field so that, when control finally arrives here, we'll know
1029 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
1032 struct mxs_nand_info *nand_info = nand->priv;
1035 * First, fill in the OOB buffer. If we're doing a raw read, we need to
1036 * get the bytes from the physical page. If we're not doing a raw read,
1037 * we need to fill the buffer with set bits.
1039 if (nand_info->raw_oob_mode) {
1041 * If control arrives here, we're doing a "raw" read. Send the
1042 * command to read the conventional OOB and read it.
1044 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1045 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
1048 * If control arrives here, we're not doing a "raw" read. Fill
1049 * the OOB buffer with set bits and correct the block mark.
1051 memset(nand->oob_poi, 0xff, mtd->oobsize);
1053 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
1054 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
1062 * Write OOB data to NAND.
1064 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
1067 struct mxs_nand_info *nand_info = nand->priv;
1068 uint8_t block_mark = 0;
1071 * There are fundamental incompatibilities between the i.MX GPMI NFC and
1072 * the NAND Flash MTD model that make it essentially impossible to write
1073 * the out-of-band bytes.
1075 * We permit *ONE* exception. If the *intent* of writing the OOB is to
1076 * mark a block bad, we can do that.
1079 if (!nand_info->marking_block_bad) {
1080 printf("NXS NAND: Writing OOB isn't supported\n");
1084 /* Write the block mark. */
1085 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1086 nand->write_buf(mtd, &block_mark, 1);
1087 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1089 /* Check if it worked. */
1090 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1097 * Claims all blocks are good.
1099 * In principle, this function is *only* called when the NAND Flash MTD system
1100 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1101 * the driver for bad block information.
1103 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1104 * this function is *only* called when we take it away.
1106 * Thus, this function is only called when we want *all* blocks to look good,
1107 * so it *always* return success.
1109 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
1115 * Nominally, the purpose of this function is to look for or create the bad
1116 * block table. In fact, since the we call this function at the very end of
1117 * the initialization process started by nand_scan(), and we don't have a
1118 * more formal mechanism, we "hook" this function to continue init process.
1120 * At this point, the physical NAND Flash chips have been identified and
1121 * counted, so we know the physical geometry. This enables us to make some
1122 * important configuration decisions.
1124 * The return value of this function propogates directly back to this driver's
1125 * call to nand_scan(). Anything other than zero will cause this driver to
1126 * tear everything down and declare failure.
1128 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
1130 struct nand_chip *nand = mtd->priv;
1131 struct mxs_nand_info *nand_info = nand->priv;
1134 /* Configure BCH and set NFC geometry */
1135 if (readl(&bch_regs->hw_bch_ctrl_reg) &
1136 (BCH_CTRL_SFTRST | BCH_CTRL_CLKGATE))
1137 /* When booting from NAND the BCH engine will already
1138 * be operational and obviously does not like being reset here.
1139 * There will be occasional read errors upon boot when this
1142 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1143 readl(&bch_regs->hw_bch_ctrl_reg);
1145 debug("mtd->writesize=%d\n", mtd->writesize);
1146 debug("mtd->oobsize=%d\n", mtd->oobsize);
1147 debug("ecc_strength=%d\n", mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize));
1149 /* Configure layout 0 */
1150 tmp = (mxs_nand_ecc_chunk_cnt(mtd) - 1)
1151 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1152 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1153 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1154 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1155 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1156 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1157 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1159 tmp = (mtd->writesize + mtd->oobsize)
1160 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1161 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1162 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1163 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1164 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1165 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1167 /* Set *all* chip selects to use layout 0 */
1168 writel(0, &bch_regs->hw_bch_layoutselect);
1170 /* Enable BCH complete interrupt */
1171 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1173 /* Hook some operations at the MTD level. */
1174 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1175 nand_info->hooked_read_oob = mtd->_read_oob;
1176 mtd->_read_oob = mxs_nand_hook_read_oob;
1179 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1180 nand_info->hooked_write_oob = mtd->_write_oob;
1181 mtd->_write_oob = mxs_nand_hook_write_oob;
1184 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1185 nand_info->hooked_block_markbad = mtd->_block_markbad;
1186 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1189 /* We use the reference implementation for bad block management. */
1190 return nand_default_bbt(mtd);
1194 * Allocate DMA buffers
1196 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1199 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1201 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1204 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1206 printf("%s: Error allocating DMA buffers\n", __func__);
1210 memset(buf, 0, nand_info->data_buf_size);
1212 nand_info->data_buf = buf;
1213 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1214 /* Command buffers */
1215 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1216 MXS_NAND_COMMAND_BUFFER_SIZE);
1217 if (!nand_info->cmd_buf) {
1219 printf("MXS NAND: Error allocating command buffers\n");
1222 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1223 nand_info->cmd_queue_len = 0;
1229 * Initializes the NFC hardware.
1231 int mxs_nand_init(struct mxs_nand_info *info)
1236 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1237 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1239 printf("MXS NAND: Unable to allocate DMA descriptor table\n");
1246 /* Allocate the DMA descriptors. */
1247 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1248 info->desc[i] = mxs_dma_desc_alloc();
1249 if (!info->desc[i]) {
1250 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1256 /* Init the DMA controller. */
1257 for (i = 0; i < CONFIG_SYS_NAND_MAX_CHIPS; i++) {
1258 const int chan = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + i;
1260 ret = mxs_dma_init_channel(chan);
1262 printf("Failed to initialize DMA channel %d\n", chan);
1267 ret = mxs_nand_gpmi_init();
1274 for (--i; i >= 0; i--)
1275 mxs_dma_release(i + MXS_DMA_CHANNEL_AHB_APBH_GPMI0);
1276 i = MXS_NAND_DMA_DESCRIPTOR_COUNT - 1;
1279 for (--i; i >= 0; i--)
1280 mxs_dma_desc_free(info->desc[i]);
1286 * This function is called during the driver binding process.
1288 * @param pdev the device structure used to store device specific
1289 * information that is used by the suspend, resume and
1292 * @return The function always returns 0.
1294 int board_nand_init(struct nand_chip *nand)
1296 struct mxs_nand_info *nand_info;
1299 nand_info = malloc(sizeof(struct mxs_nand_info));
1301 printf("MXS NAND: Failed to allocate private data\n");
1304 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1306 err = mxs_nand_alloc_buffers(nand_info);
1310 err = mxs_nand_init(nand_info);
1314 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1316 nand->priv = nand_info;
1317 nand->options |= NAND_NO_SUBPAGE_WRITE;
1318 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1319 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1321 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1323 nand->dev_ready = mxs_nand_device_ready;
1324 nand->select_chip = mxs_nand_select_chip;
1325 nand->block_bad = mxs_nand_block_bad;
1326 nand->scan_bbt = mxs_nand_scan_bbt;
1328 nand->read_byte = mxs_nand_read_byte;
1330 nand->read_buf = mxs_nand_read_buf;
1331 nand->write_buf = mxs_nand_write_buf;
1333 nand->ecc.read_page = mxs_nand_ecc_read_page;
1334 nand->ecc.write_page = mxs_nand_ecc_write_page;
1335 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1336 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1338 nand->ecc.layout = &fake_ecc_layout;
1339 nand->ecc.mode = NAND_ECC_HW;
1340 nand->ecc.bytes = 9;
1341 nand->ecc.size = 512;
1342 nand->ecc.strength = 8;
1347 free(nand_info->data_buf);
1348 free(nand_info->cmd_buf);