5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #define ENOTSUPP 524 /* Operation is not supported */
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
47 #ifdef CONFIG_MTD_PARTITIONS
48 #include <linux/mtd/partitions.h>
52 #include <asm/errno.h>
55 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
56 * a flash. NAND flash is initialized prior to interrupts so standard timers
57 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
58 * which is greater than (max NAND reset time / NAND status read time).
59 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
61 #ifndef CONFIG_SYS_NAND_RESET_CNT
62 #define CONFIG_SYS_NAND_RESET_CNT 200000
65 /* Define default oob placement schemes for large and small page devices */
66 static struct nand_ecclayout nand_oob_8 = {
76 static struct nand_ecclayout nand_oob_16 = {
78 .eccpos = {0, 1, 2, 3, 6, 7},
84 static struct nand_ecclayout nand_oob_64 = {
87 40, 41, 42, 43, 44, 45, 46, 47,
88 48, 49, 50, 51, 52, 53, 54, 55,
89 56, 57, 58, 59, 60, 61, 62, 63},
95 static struct nand_ecclayout nand_oob_128 = {
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100, 101, 102, 103,
101 104, 105, 106, 107, 108, 109, 110, 111,
102 112, 113, 114, 115, 116, 117, 118, 119,
103 120, 121, 122, 123, 124, 125, 126, 127},
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
119 * nand_release_device - [GENERIC] release chip
120 * @mtd: MTD device structure
122 * Deselect, release chip lock and wake up anyone waiting on the device
124 static void nand_release_device (struct mtd_info *mtd)
126 struct nand_chip *this = mtd->priv;
127 this->select_chip(mtd, -1); /* De-select the NAND device */
131 * nand_read_byte - [DEFAULT] read one byte from the chip
132 * @mtd: MTD device structure
134 * Default read function for 8bit buswith
136 static uint8_t nand_read_byte(struct mtd_info *mtd)
138 struct nand_chip *chip = mtd->priv;
139 return readb(chip->IO_ADDR_R);
143 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
144 * @mtd: MTD device structure
146 * Default read function for 16bit buswith with
147 * endianess conversion
149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
156 * nand_read_word - [DEFAULT] read one word from the chip
157 * @mtd: MTD device structure
159 * Default read function for 16bit buswith without
160 * endianess conversion
162 static u16 nand_read_word(struct mtd_info *mtd)
164 struct nand_chip *chip = mtd->priv;
165 return readw(chip->IO_ADDR_R);
169 * nand_select_chip - [DEFAULT] control CE line
170 * @mtd: MTD device structure
171 * @chipnr: chipnumber to select, -1 for deselect
173 * Default select function for 1 chip devices.
175 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
177 struct nand_chip *chip = mtd->priv;
181 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
192 * nand_write_buf - [DEFAULT] write buffer to chip
193 * @mtd: MTD device structure
195 * @len: number of bytes to write
197 * Default write function for 8bit buswith
199 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
202 struct nand_chip *chip = mtd->priv;
204 for (i = 0; i < len; i++)
205 writeb(buf[i], chip->IO_ADDR_W);
209 * nand_read_buf - [DEFAULT] read chip data into buffer
210 * @mtd: MTD device structure
211 * @buf: buffer to store date
212 * @len: number of bytes to read
214 * Default read function for 8bit buswith
216 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
219 struct nand_chip *chip = mtd->priv;
221 for (i = 0; i < len; i++)
222 buf[i] = readb(chip->IO_ADDR_R);
226 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
227 * @mtd: MTD device structure
228 * @buf: buffer containing the data to compare
229 * @len: number of bytes to compare
231 * Default verify function for 8bit buswith
233 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
236 struct nand_chip *chip = mtd->priv;
238 for (i = 0; i < len; i++)
239 if (buf[i] != readb(chip->IO_ADDR_R))
245 * nand_write_buf16 - [DEFAULT] write buffer to chip
246 * @mtd: MTD device structure
248 * @len: number of bytes to write
250 * Default write function for 16bit buswith
252 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
255 struct nand_chip *chip = mtd->priv;
256 u16 *p = (u16 *) buf;
259 for (i = 0; i < len; i++)
260 writew(p[i], chip->IO_ADDR_W);
265 * nand_read_buf16 - [DEFAULT] read chip data into buffer
266 * @mtd: MTD device structure
267 * @buf: buffer to store date
268 * @len: number of bytes to read
270 * Default read function for 16bit buswith
272 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
279 for (i = 0; i < len; i++)
280 p[i] = readw(chip->IO_ADDR_R);
284 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
285 * @mtd: MTD device structure
286 * @buf: buffer containing the data to compare
287 * @len: number of bytes to compare
289 * Default verify function for 16bit buswith
291 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
294 struct nand_chip *chip = mtd->priv;
295 u16 *p = (u16 *) buf;
298 for (i = 0; i < len; i++)
299 if (p[i] != readw(chip->IO_ADDR_R))
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
307 * @mtd: MTD device structure
308 * @ofs: offset from device start
309 * @getchip: 0, if the chip is already selected
311 * Check, if the block is bad.
313 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
315 int page, chipnr, res = 0;
316 struct nand_chip *chip = mtd->priv;
319 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322 chipnr = (int)(ofs >> chip->chip_shift);
324 nand_get_device(chip, mtd, FL_READING);
326 /* Select the NAND device */
327 chip->select_chip(mtd, chipnr);
330 if (chip->options & NAND_BUSWIDTH_16) {
331 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
333 bad = cpu_to_le16(chip->read_word(mtd));
334 if (chip->badblockpos & 0x1)
336 if ((bad & 0xFF) != 0xff)
339 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
340 if (chip->read_byte(mtd) != 0xff)
345 nand_release_device(mtd);
351 * nand_default_block_markbad - [DEFAULT] mark a block bad
352 * @mtd: MTD device structure
353 * @ofs: offset from device start
355 * This is the default implementation, which can be overridden by
356 * a hardware specific driver.
358 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
360 struct nand_chip *chip = mtd->priv;
361 uint8_t buf[2] = { 0, 0 };
364 /* Get block number */
365 block = (int)(ofs >> chip->bbt_erase_shift);
367 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
369 /* Do we have a flash based bad block table ? */
370 if (chip->options & NAND_USE_FLASH_BBT)
371 ret = nand_update_bbt(mtd, ofs);
373 /* We write two bytes, so we dont have to mess with 16 bit
376 nand_get_device(chip, mtd, FL_WRITING);
378 chip->ops.len = chip->ops.ooblen = 2;
379 chip->ops.datbuf = NULL;
380 chip->ops.oobbuf = buf;
381 chip->ops.ooboffs = chip->badblockpos & ~0x01;
383 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
384 nand_release_device(mtd);
387 mtd->ecc_stats.badblocks++;
393 * nand_check_wp - [GENERIC] check if the chip is write protected
394 * @mtd: MTD device structure
395 * Check, if the device is write protected
397 * The function expects, that the device is already selected
399 static int nand_check_wp(struct mtd_info *mtd)
401 struct nand_chip *chip = mtd->priv;
402 /* Check the WP bit */
403 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
404 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
408 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
409 * @mtd: MTD device structure
410 * @ofs: offset from device start
411 * @getchip: 0, if the chip is already selected
412 * @allowbbt: 1, if its allowed to access the bbt area
414 * Check, if the block is bad. Either by reading the bad block table or
415 * calling of the scan function.
417 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420 struct nand_chip *chip = mtd->priv;
422 if (!(chip->options & NAND_BBT_SCANNED)) {
423 chip->options |= NAND_BBT_SCANNED;
428 return chip->block_bad(mtd, ofs, getchip);
430 /* Return info from the table */
431 return nand_isbad_bbt(mtd, ofs, allowbbt);
435 * Wait for the ready pin, after a command
436 * The timeout is catched later.
438 void nand_wait_ready(struct mtd_info *mtd)
440 struct nand_chip *chip = mtd->priv;
441 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
444 time_start = get_timer(0);
446 /* wait until command is processed or timeout occures */
447 while (get_timer(time_start) < timeo) {
449 if (chip->dev_ready(mtd))
455 * nand_command - [DEFAULT] Send command to NAND device
456 * @mtd: MTD device structure
457 * @command: the command to be sent
458 * @column: the column address for this command, -1 if none
459 * @page_addr: the page address for this command, -1 if none
461 * Send command to NAND device. This function is used for small page
462 * devices (256/512 Bytes per page)
464 static void nand_command(struct mtd_info *mtd, unsigned int command,
465 int column, int page_addr)
467 register struct nand_chip *chip = mtd->priv;
468 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
469 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
472 * Write out the command to the device.
474 if (command == NAND_CMD_SEQIN) {
477 if (column >= mtd->writesize) {
479 column -= mtd->writesize;
480 readcmd = NAND_CMD_READOOB;
481 } else if (column < 256) {
482 /* First 256 bytes --> READ0 */
483 readcmd = NAND_CMD_READ0;
486 readcmd = NAND_CMD_READ1;
488 chip->cmd_ctrl(mtd, readcmd, ctrl);
489 ctrl &= ~NAND_CTRL_CHANGE;
491 chip->cmd_ctrl(mtd, command, ctrl);
494 * Address cycle, when necessary
496 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
497 /* Serially input address */
499 /* Adjust columns for 16 bit buswidth */
500 if (chip->options & NAND_BUSWIDTH_16)
502 chip->cmd_ctrl(mtd, column, ctrl);
503 ctrl &= ~NAND_CTRL_CHANGE;
505 if (page_addr != -1) {
506 chip->cmd_ctrl(mtd, page_addr, ctrl);
507 ctrl &= ~NAND_CTRL_CHANGE;
508 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
509 /* One more address cycle for devices > 32MiB */
510 if (chip->chipsize > (32 << 20))
511 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
513 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
516 * program and erase have their own busy handlers
517 * status and sequential in needs no delay
521 case NAND_CMD_PAGEPROG:
522 case NAND_CMD_ERASE1:
523 case NAND_CMD_ERASE2:
525 case NAND_CMD_STATUS:
531 udelay(chip->chip_delay);
532 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
533 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
535 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
536 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
540 /* This applies to read commands */
543 * If we don't have access to the busy pin, we apply the given
546 if (!chip->dev_ready) {
547 udelay(chip->chip_delay);
551 /* Apply this short delay always to ensure that we do wait tWB in
552 * any case on any machine. */
555 nand_wait_ready(mtd);
559 * nand_command_lp - [DEFAULT] Send command to NAND large page device
560 * @mtd: MTD device structure
561 * @command: the command to be sent
562 * @column: the column address for this command, -1 if none
563 * @page_addr: the page address for this command, -1 if none
565 * Send command to NAND device. This is the version for the new large page
566 * devices We dont have the separate regions as we have in the small page
567 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
569 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
570 int column, int page_addr)
572 register struct nand_chip *chip = mtd->priv;
573 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
575 /* Emulate NAND_CMD_READOOB */
576 if (command == NAND_CMD_READOOB) {
577 column += mtd->writesize;
578 command = NAND_CMD_READ0;
581 /* Command latch cycle */
582 chip->cmd_ctrl(mtd, command & 0xff,
583 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
585 if (column != -1 || page_addr != -1) {
586 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
588 /* Serially input address */
590 /* Adjust columns for 16 bit buswidth */
591 if (chip->options & NAND_BUSWIDTH_16)
593 chip->cmd_ctrl(mtd, column, ctrl);
594 ctrl &= ~NAND_CTRL_CHANGE;
595 chip->cmd_ctrl(mtd, column >> 8, ctrl);
597 if (page_addr != -1) {
598 chip->cmd_ctrl(mtd, page_addr, ctrl);
599 chip->cmd_ctrl(mtd, page_addr >> 8,
600 NAND_NCE | NAND_ALE);
601 /* One more address cycle for devices > 128MiB */
602 if (chip->chipsize > (128 << 20))
603 chip->cmd_ctrl(mtd, page_addr >> 16,
604 NAND_NCE | NAND_ALE);
607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
610 * program and erase have their own busy handlers
611 * status, sequential in, and deplete1 need no delay
615 case NAND_CMD_CACHEDPROG:
616 case NAND_CMD_PAGEPROG:
617 case NAND_CMD_ERASE1:
618 case NAND_CMD_ERASE2:
621 case NAND_CMD_STATUS:
622 case NAND_CMD_DEPLETE1:
626 * read error status commands require only a short delay
628 case NAND_CMD_STATUS_ERROR:
629 case NAND_CMD_STATUS_ERROR0:
630 case NAND_CMD_STATUS_ERROR1:
631 case NAND_CMD_STATUS_ERROR2:
632 case NAND_CMD_STATUS_ERROR3:
633 udelay(chip->chip_delay);
639 udelay(chip->chip_delay);
640 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
641 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
642 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
643 NAND_NCE | NAND_CTRL_CHANGE);
644 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
648 case NAND_CMD_RNDOUT:
649 /* No ready / busy check necessary */
650 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
651 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
652 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
653 NAND_NCE | NAND_CTRL_CHANGE);
657 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
658 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
659 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
660 NAND_NCE | NAND_CTRL_CHANGE);
662 /* This applies to read commands */
665 * If we don't have access to the busy pin, we apply the given
668 if (!chip->dev_ready) {
669 udelay(chip->chip_delay);
674 /* Apply this short delay always to ensure that we do wait tWB in
675 * any case on any machine. */
678 nand_wait_ready(mtd);
682 * nand_get_device - [GENERIC] Get chip for selected access
683 * @chip: the nand chip descriptor
684 * @mtd: MTD device structure
685 * @new_state: the state which is requested
687 * Get the device and lock it for exclusive access
689 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
691 this->state = new_state;
696 * nand_wait - [DEFAULT] wait until the command is done
697 * @mtd: MTD device structure
698 * @chip: NAND chip structure
700 * Wait for command done. This applies to erase and program only
701 * Erase can take up to 400ms and program up to 20ms according to
702 * general NAND and SmartMedia specs
704 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
707 int state = this->state;
710 if (state == FL_ERASING)
711 timeo = (CONFIG_SYS_HZ * 400) / 1000;
713 timeo = (CONFIG_SYS_HZ * 20) / 1000;
715 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
716 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
718 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
720 time_start = get_timer(0);
723 if (get_timer(time_start) > timeo) {
728 if (this->dev_ready) {
729 if (this->dev_ready(mtd))
732 if (this->read_byte(mtd) & NAND_STATUS_READY)
736 #ifdef PPCHAMELON_NAND_TIMER_HACK
737 time_start = get_timer(0);
738 while (get_timer(time_start) < 10)
740 #endif /* PPCHAMELON_NAND_TIMER_HACK */
742 return this->read_byte(mtd);
746 * nand_read_page_raw - [Intern] read raw page data without ecc
747 * @mtd: mtd info structure
748 * @chip: nand chip info structure
749 * @buf: buffer to store read data
750 * @page: page number to read
752 * Not for syndrome calculating ecc controllers, which use a special oob layout
754 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
755 uint8_t *buf, int page)
757 chip->read_buf(mtd, buf, mtd->writesize);
758 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
763 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
764 * @mtd: mtd info structure
765 * @chip: nand chip info structure
766 * @buf: buffer to store read data
767 * @page: page number to read
769 * We need a special oob layout and handling even when OOB isn't used.
771 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
772 uint8_t *buf, int page)
774 int eccsize = chip->ecc.size;
775 int eccbytes = chip->ecc.bytes;
776 uint8_t *oob = chip->oob_poi;
779 for (steps = chip->ecc.steps; steps > 0; steps--) {
780 chip->read_buf(mtd, buf, eccsize);
783 if (chip->ecc.prepad) {
784 chip->read_buf(mtd, oob, chip->ecc.prepad);
785 oob += chip->ecc.prepad;
788 chip->read_buf(mtd, oob, eccbytes);
791 if (chip->ecc.postpad) {
792 chip->read_buf(mtd, oob, chip->ecc.postpad);
793 oob += chip->ecc.postpad;
797 size = mtd->oobsize - (oob - chip->oob_poi);
799 chip->read_buf(mtd, oob, size);
805 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
806 * @mtd: mtd info structure
807 * @chip: nand chip info structure
808 * @buf: buffer to store read data
809 * @page: page number to read
811 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
812 uint8_t *buf, int page)
814 int i, eccsize = chip->ecc.size;
815 int eccbytes = chip->ecc.bytes;
816 int eccsteps = chip->ecc.steps;
818 uint8_t *ecc_calc = chip->buffers->ecccalc;
819 uint8_t *ecc_code = chip->buffers->ecccode;
820 uint32_t *eccpos = chip->ecc.layout->eccpos;
822 chip->ecc.read_page_raw(mtd, chip, buf, page);
824 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
825 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
827 for (i = 0; i < chip->ecc.total; i++)
828 ecc_code[i] = chip->oob_poi[eccpos[i]];
830 eccsteps = chip->ecc.steps;
833 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
836 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
838 mtd->ecc_stats.failed++;
840 mtd->ecc_stats.corrected += stat;
846 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
847 * @mtd: mtd info structure
848 * @chip: nand chip info structure
849 * @data_offs: offset of requested data within the page
850 * @readlen: data length
851 * @bufpoi: buffer to store read data
853 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
855 int start_step, end_step, num_steps;
856 uint32_t *eccpos = chip->ecc.layout->eccpos;
858 int data_col_addr, i, gaps = 0;
859 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
860 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
862 /* Column address wihin the page aligned to ECC size (256bytes). */
863 start_step = data_offs / chip->ecc.size;
864 end_step = (data_offs + readlen - 1) / chip->ecc.size;
865 num_steps = end_step - start_step + 1;
867 /* Data size aligned to ECC ecc.size*/
868 datafrag_len = num_steps * chip->ecc.size;
869 eccfrag_len = num_steps * chip->ecc.bytes;
871 data_col_addr = start_step * chip->ecc.size;
872 /* If we read not a page aligned data */
873 if (data_col_addr != 0)
874 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
876 p = bufpoi + data_col_addr;
877 chip->read_buf(mtd, p, datafrag_len);
880 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
881 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
883 /* The performance is faster if to position offsets
884 according to ecc.pos. Let make sure here that
885 there are no gaps in ecc positions */
886 for (i = 0; i < eccfrag_len - 1; i++) {
887 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
888 eccpos[i + start_step * chip->ecc.bytes + 1]) {
894 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
895 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
897 /* send the command to read the particular ecc bytes */
898 /* take care about buswidth alignment in read_buf */
899 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
900 aligned_len = eccfrag_len;
901 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
903 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
906 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
907 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
910 for (i = 0; i < eccfrag_len; i++)
911 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
913 p = bufpoi + data_col_addr;
914 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
917 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
919 mtd->ecc_stats.failed++;
921 mtd->ecc_stats.corrected += stat;
927 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
928 * @mtd: mtd info structure
929 * @chip: nand chip info structure
930 * @buf: buffer to store read data
931 * @page: page number to read
933 * Not for syndrome calculating ecc controllers which need a special oob layout
935 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
936 uint8_t *buf, int page)
938 int i, eccsize = chip->ecc.size;
939 int eccbytes = chip->ecc.bytes;
940 int eccsteps = chip->ecc.steps;
942 uint8_t *ecc_calc = chip->buffers->ecccalc;
943 uint8_t *ecc_code = chip->buffers->ecccode;
944 uint32_t *eccpos = chip->ecc.layout->eccpos;
946 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
947 chip->ecc.hwctl(mtd, NAND_ECC_READ);
948 chip->read_buf(mtd, p, eccsize);
949 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
951 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
953 for (i = 0; i < chip->ecc.total; i++)
954 ecc_code[i] = chip->oob_poi[eccpos[i]];
956 eccsteps = chip->ecc.steps;
959 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
962 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
964 mtd->ecc_stats.failed++;
966 mtd->ecc_stats.corrected += stat;
972 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
973 * @mtd: mtd info structure
974 * @chip: nand chip info structure
975 * @buf: buffer to store read data
976 * @page: page number to read
978 * Hardware ECC for large page chips, require OOB to be read first.
979 * For this ECC mode, the write_page method is re-used from ECC_HW.
980 * These methods read/write ECC from the OOB area, unlike the
981 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
982 * "infix ECC" scheme and reads/writes ECC from the data area, by
983 * overwriting the NAND manufacturer bad block markings.
985 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
986 struct nand_chip *chip, uint8_t *buf, int page)
988 int i, eccsize = chip->ecc.size;
989 int eccbytes = chip->ecc.bytes;
990 int eccsteps = chip->ecc.steps;
992 uint8_t *ecc_code = chip->buffers->ecccode;
993 uint32_t *eccpos = chip->ecc.layout->eccpos;
994 uint8_t *ecc_calc = chip->buffers->ecccalc;
996 /* Read the OOB area first */
997 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
998 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
999 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1001 for (i = 0; i < chip->ecc.total; i++)
1002 ecc_code[i] = chip->oob_poi[eccpos[i]];
1004 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1007 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1008 chip->read_buf(mtd, p, eccsize);
1009 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1011 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1013 mtd->ecc_stats.failed++;
1015 mtd->ecc_stats.corrected += stat;
1021 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1022 * @mtd: mtd info structure
1023 * @chip: nand chip info structure
1024 * @buf: buffer to store read data
1025 * @page: page number to read
1027 * The hw generator calculates the error syndrome automatically. Therefor
1028 * we need a special oob layout and handling.
1030 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1031 uint8_t *buf, int page)
1033 int i, eccsize = chip->ecc.size;
1034 int eccbytes = chip->ecc.bytes;
1035 int eccsteps = chip->ecc.steps;
1037 uint8_t *oob = chip->oob_poi;
1039 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1042 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1043 chip->read_buf(mtd, p, eccsize);
1045 if (chip->ecc.prepad) {
1046 chip->read_buf(mtd, oob, chip->ecc.prepad);
1047 oob += chip->ecc.prepad;
1050 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1051 chip->read_buf(mtd, oob, eccbytes);
1052 stat = chip->ecc.correct(mtd, p, oob, NULL);
1055 mtd->ecc_stats.failed++;
1057 mtd->ecc_stats.corrected += stat;
1061 if (chip->ecc.postpad) {
1062 chip->read_buf(mtd, oob, chip->ecc.postpad);
1063 oob += chip->ecc.postpad;
1067 /* Calculate remaining oob bytes */
1068 i = mtd->oobsize - (oob - chip->oob_poi);
1070 chip->read_buf(mtd, oob, i);
1076 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1077 * @chip: nand chip structure
1078 * @oob: oob destination address
1079 * @ops: oob ops structure
1080 * @len: size of oob to transfer
1082 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1083 struct mtd_oob_ops *ops, size_t len)
1089 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1092 case MTD_OOB_AUTO: {
1093 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1094 uint32_t boffs = 0, roffs = ops->ooboffs;
1097 for(; free->length && len; free++, len -= bytes) {
1098 /* Read request not from offset 0 ? */
1099 if (unlikely(roffs)) {
1100 if (roffs >= free->length) {
1101 roffs -= free->length;
1104 boffs = free->offset + roffs;
1105 bytes = min_t(size_t, len,
1106 (free->length - roffs));
1109 bytes = min_t(size_t, len, free->length);
1110 boffs = free->offset;
1112 memcpy(oob, chip->oob_poi + boffs, bytes);
1124 * nand_do_read_ops - [Internal] Read data with ECC
1126 * @mtd: MTD device structure
1127 * @from: offset to read from
1128 * @ops: oob ops structure
1130 * Internal function. Called with chip held.
1132 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1133 struct mtd_oob_ops *ops)
1135 int chipnr, page, realpage, col, bytes, aligned;
1136 struct nand_chip *chip = mtd->priv;
1137 struct mtd_ecc_stats stats;
1138 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1141 uint32_t readlen = ops->len;
1142 uint32_t oobreadlen = ops->ooblen;
1143 uint8_t *bufpoi, *oob, *buf;
1145 stats = mtd->ecc_stats;
1147 chipnr = (int)(from >> chip->chip_shift);
1148 chip->select_chip(mtd, chipnr);
1150 realpage = (int)(from >> chip->page_shift);
1151 page = realpage & chip->pagemask;
1153 col = (int)(from & (mtd->writesize - 1));
1159 bytes = min(mtd->writesize - col, readlen);
1160 aligned = (bytes == mtd->writesize);
1162 /* Is the current page in the buffer ? */
1163 if (realpage != chip->pagebuf || oob) {
1164 bufpoi = aligned ? buf : chip->buffers->databuf;
1166 if (likely(sndcmd)) {
1167 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1171 /* Now read the page into the buffer */
1172 if (unlikely(ops->mode == MTD_OOB_RAW))
1173 ret = chip->ecc.read_page_raw(mtd, chip,
1175 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1176 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1178 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1183 /* Transfer not aligned data */
1185 if (!NAND_SUBPAGE_READ(chip) && !oob)
1186 chip->pagebuf = realpage;
1187 memcpy(buf, chip->buffers->databuf + col, bytes);
1192 if (unlikely(oob)) {
1193 /* Raw mode does data:oob:data:oob */
1194 if (ops->mode != MTD_OOB_RAW) {
1195 int toread = min(oobreadlen,
1196 chip->ecc.layout->oobavail);
1198 oob = nand_transfer_oob(chip,
1200 oobreadlen -= toread;
1203 buf = nand_transfer_oob(chip,
1204 buf, ops, mtd->oobsize);
1207 if (!(chip->options & NAND_NO_READRDY)) {
1209 * Apply delay or wait for ready/busy pin. Do
1210 * this before the AUTOINCR check, so no
1211 * problems arise if a chip which does auto
1212 * increment is marked as NOAUTOINCR by the
1215 if (!chip->dev_ready)
1216 udelay(chip->chip_delay);
1218 nand_wait_ready(mtd);
1221 memcpy(buf, chip->buffers->databuf + col, bytes);
1230 /* For subsequent reads align to page boundary. */
1232 /* Increment page address */
1235 page = realpage & chip->pagemask;
1236 /* Check, if we cross a chip boundary */
1239 chip->select_chip(mtd, -1);
1240 chip->select_chip(mtd, chipnr);
1243 /* Check, if the chip supports auto page increment
1244 * or if we have hit a block boundary.
1246 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1250 ops->retlen = ops->len - (size_t) readlen;
1252 ops->oobretlen = ops->ooblen - oobreadlen;
1257 if (mtd->ecc_stats.failed - stats.failed)
1260 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1264 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1265 * @mtd: MTD device structure
1266 * @from: offset to read from
1267 * @len: number of bytes to read
1268 * @retlen: pointer to variable to store the number of read bytes
1269 * @buf: the databuffer to put data
1271 * Get hold of the chip and call nand_do_read
1273 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1274 size_t *retlen, uint8_t *buf)
1276 struct nand_chip *chip = mtd->priv;
1279 /* Do not allow reads past end of device */
1280 if ((from + len) > mtd->size)
1285 nand_get_device(chip, mtd, FL_READING);
1287 chip->ops.len = len;
1288 chip->ops.datbuf = buf;
1289 chip->ops.oobbuf = NULL;
1291 ret = nand_do_read_ops(mtd, from, &chip->ops);
1293 *retlen = chip->ops.retlen;
1295 nand_release_device(mtd);
1301 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1302 * @mtd: mtd info structure
1303 * @chip: nand chip info structure
1304 * @page: page number to read
1305 * @sndcmd: flag whether to issue read command or not
1307 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1308 int page, int sndcmd)
1311 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1314 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1319 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1321 * @mtd: mtd info structure
1322 * @chip: nand chip info structure
1323 * @page: page number to read
1324 * @sndcmd: flag whether to issue read command or not
1326 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1327 int page, int sndcmd)
1329 uint8_t *buf = chip->oob_poi;
1330 int length = mtd->oobsize;
1331 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1332 int eccsize = chip->ecc.size;
1333 uint8_t *bufpoi = buf;
1334 int i, toread, sndrnd = 0, pos;
1336 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1337 for (i = 0; i < chip->ecc.steps; i++) {
1339 pos = eccsize + i * (eccsize + chunk);
1340 if (mtd->writesize > 512)
1341 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1343 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1346 toread = min_t(int, length, chunk);
1347 chip->read_buf(mtd, bufpoi, toread);
1352 chip->read_buf(mtd, bufpoi, length);
1358 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1359 * @mtd: mtd info structure
1360 * @chip: nand chip info structure
1361 * @page: page number to write
1363 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1367 const uint8_t *buf = chip->oob_poi;
1368 int length = mtd->oobsize;
1370 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1371 chip->write_buf(mtd, buf, length);
1372 /* Send command to program the OOB data */
1373 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1375 status = chip->waitfunc(mtd, chip);
1377 return status & NAND_STATUS_FAIL ? -EIO : 0;
1381 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1382 * with syndrome - only for large page flash !
1383 * @mtd: mtd info structure
1384 * @chip: nand chip info structure
1385 * @page: page number to write
1387 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1388 struct nand_chip *chip, int page)
1390 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1391 int eccsize = chip->ecc.size, length = mtd->oobsize;
1392 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1393 const uint8_t *bufpoi = chip->oob_poi;
1396 * data-ecc-data-ecc ... ecc-oob
1398 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1400 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1401 pos = steps * (eccsize + chunk);
1406 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1407 for (i = 0; i < steps; i++) {
1409 if (mtd->writesize <= 512) {
1410 uint32_t fill = 0xFFFFFFFF;
1414 int num = min_t(int, len, 4);
1415 chip->write_buf(mtd, (uint8_t *)&fill,
1420 pos = eccsize + i * (eccsize + chunk);
1421 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1425 len = min_t(int, length, chunk);
1426 chip->write_buf(mtd, bufpoi, len);
1431 chip->write_buf(mtd, bufpoi, length);
1433 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1434 status = chip->waitfunc(mtd, chip);
1436 return status & NAND_STATUS_FAIL ? -EIO : 0;
1440 * nand_do_read_oob - [Intern] NAND read out-of-band
1441 * @mtd: MTD device structure
1442 * @from: offset to read from
1443 * @ops: oob operations description structure
1445 * NAND read out-of-band data from the spare area
1447 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1448 struct mtd_oob_ops *ops)
1450 int page, realpage, chipnr, sndcmd = 1;
1451 struct nand_chip *chip = mtd->priv;
1452 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1453 int readlen = ops->ooblen;
1455 uint8_t *buf = ops->oobbuf;
1457 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1458 (unsigned long long)from, readlen);
1460 if (ops->mode == MTD_OOB_AUTO)
1461 len = chip->ecc.layout->oobavail;
1465 if (unlikely(ops->ooboffs >= len)) {
1466 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1467 "Attempt to start read outside oob\n");
1471 /* Do not allow reads past end of device */
1472 if (unlikely(from >= mtd->size ||
1473 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1474 (from >> chip->page_shift)) * len)) {
1475 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1476 "Attempt read beyond end of device\n");
1480 chipnr = (int)(from >> chip->chip_shift);
1481 chip->select_chip(mtd, chipnr);
1483 /* Shift to get page */
1484 realpage = (int)(from >> chip->page_shift);
1485 page = realpage & chip->pagemask;
1488 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1490 len = min(len, readlen);
1491 buf = nand_transfer_oob(chip, buf, ops, len);
1493 if (!(chip->options & NAND_NO_READRDY)) {
1495 * Apply delay or wait for ready/busy pin. Do this
1496 * before the AUTOINCR check, so no problems arise if a
1497 * chip which does auto increment is marked as
1498 * NOAUTOINCR by the board driver.
1500 if (!chip->dev_ready)
1501 udelay(chip->chip_delay);
1503 nand_wait_ready(mtd);
1510 /* Increment page address */
1513 page = realpage & chip->pagemask;
1514 /* Check, if we cross a chip boundary */
1517 chip->select_chip(mtd, -1);
1518 chip->select_chip(mtd, chipnr);
1521 /* Check, if the chip supports auto page increment
1522 * or if we have hit a block boundary.
1524 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1528 ops->oobretlen = ops->ooblen;
1533 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1534 * @mtd: MTD device structure
1535 * @from: offset to read from
1536 * @ops: oob operation description structure
1538 * NAND read data and/or out-of-band data
1540 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1541 struct mtd_oob_ops *ops)
1543 struct nand_chip *chip = mtd->priv;
1544 int ret = -ENOTSUPP;
1548 /* Do not allow reads past end of device */
1549 if (ops->datbuf && (from + ops->len) > mtd->size) {
1550 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1551 "Attempt read beyond end of device\n");
1555 nand_get_device(chip, mtd, FL_READING);
1568 ret = nand_do_read_oob(mtd, from, ops);
1570 ret = nand_do_read_ops(mtd, from, ops);
1573 nand_release_device(mtd);
1579 * nand_write_page_raw - [Intern] raw page write function
1580 * @mtd: mtd info structure
1581 * @chip: nand chip info structure
1584 * Not for syndrome calculating ecc controllers, which use a special oob layout
1586 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1589 chip->write_buf(mtd, buf, mtd->writesize);
1590 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1594 * nand_write_page_raw_syndrome - [Intern] raw page write function
1595 * @mtd: mtd info structure
1596 * @chip: nand chip info structure
1599 * We need a special oob layout and handling even when ECC isn't checked.
1601 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1604 int eccsize = chip->ecc.size;
1605 int eccbytes = chip->ecc.bytes;
1606 uint8_t *oob = chip->oob_poi;
1609 for (steps = chip->ecc.steps; steps > 0; steps--) {
1610 chip->write_buf(mtd, buf, eccsize);
1613 if (chip->ecc.prepad) {
1614 chip->write_buf(mtd, oob, chip->ecc.prepad);
1615 oob += chip->ecc.prepad;
1618 chip->read_buf(mtd, oob, eccbytes);
1621 if (chip->ecc.postpad) {
1622 chip->write_buf(mtd, oob, chip->ecc.postpad);
1623 oob += chip->ecc.postpad;
1627 size = mtd->oobsize - (oob - chip->oob_poi);
1629 chip->write_buf(mtd, oob, size);
1632 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1633 * @mtd: mtd info structure
1634 * @chip: nand chip info structure
1637 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1640 int i, eccsize = chip->ecc.size;
1641 int eccbytes = chip->ecc.bytes;
1642 int eccsteps = chip->ecc.steps;
1643 uint8_t *ecc_calc = chip->buffers->ecccalc;
1644 const uint8_t *p = buf;
1645 uint32_t *eccpos = chip->ecc.layout->eccpos;
1647 /* Software ecc calculation */
1648 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1649 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1651 for (i = 0; i < chip->ecc.total; i++)
1652 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1654 chip->ecc.write_page_raw(mtd, chip, buf);
1658 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1659 * @mtd: mtd info structure
1660 * @chip: nand chip info structure
1663 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1666 int i, eccsize = chip->ecc.size;
1667 int eccbytes = chip->ecc.bytes;
1668 int eccsteps = chip->ecc.steps;
1669 uint8_t *ecc_calc = chip->buffers->ecccalc;
1670 const uint8_t *p = buf;
1671 uint32_t *eccpos = chip->ecc.layout->eccpos;
1673 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1674 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1675 chip->write_buf(mtd, p, eccsize);
1676 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1679 for (i = 0; i < chip->ecc.total; i++)
1680 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1682 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1686 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1687 * @mtd: mtd info structure
1688 * @chip: nand chip info structure
1691 * The hw generator calculates the error syndrome automatically. Therefor
1692 * we need a special oob layout and handling.
1694 static void nand_write_page_syndrome(struct mtd_info *mtd,
1695 struct nand_chip *chip, const uint8_t *buf)
1697 int i, eccsize = chip->ecc.size;
1698 int eccbytes = chip->ecc.bytes;
1699 int eccsteps = chip->ecc.steps;
1700 const uint8_t *p = buf;
1701 uint8_t *oob = chip->oob_poi;
1703 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1705 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1706 chip->write_buf(mtd, p, eccsize);
1708 if (chip->ecc.prepad) {
1709 chip->write_buf(mtd, oob, chip->ecc.prepad);
1710 oob += chip->ecc.prepad;
1713 chip->ecc.calculate(mtd, p, oob);
1714 chip->write_buf(mtd, oob, eccbytes);
1717 if (chip->ecc.postpad) {
1718 chip->write_buf(mtd, oob, chip->ecc.postpad);
1719 oob += chip->ecc.postpad;
1723 /* Calculate remaining oob bytes */
1724 i = mtd->oobsize - (oob - chip->oob_poi);
1726 chip->write_buf(mtd, oob, i);
1730 * nand_write_page - [REPLACEABLE] write one page
1731 * @mtd: MTD device structure
1732 * @chip: NAND chip descriptor
1733 * @buf: the data to write
1734 * @page: page number to write
1735 * @cached: cached programming
1736 * @raw: use _raw version of write_page
1738 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1739 const uint8_t *buf, int page, int cached, int raw)
1743 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1746 chip->ecc.write_page_raw(mtd, chip, buf);
1748 chip->ecc.write_page(mtd, chip, buf);
1751 * Cached progamming disabled for now, Not sure if its worth the
1752 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1756 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1758 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1759 status = chip->waitfunc(mtd, chip);
1761 * See if operation failed and additional status checks are
1764 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1765 status = chip->errstat(mtd, chip, FL_WRITING, status,
1768 if (status & NAND_STATUS_FAIL)
1771 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1772 status = chip->waitfunc(mtd, chip);
1775 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1776 /* Send command to read back the data */
1777 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1779 if (chip->verify_buf(mtd, buf, mtd->writesize))
1786 * nand_fill_oob - [Internal] Transfer client buffer to oob
1787 * @chip: nand chip structure
1788 * @oob: oob data buffer
1789 * @ops: oob ops structure
1791 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1792 struct mtd_oob_ops *ops)
1794 size_t len = ops->ooblen;
1800 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1803 case MTD_OOB_AUTO: {
1804 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1805 uint32_t boffs = 0, woffs = ops->ooboffs;
1808 for(; free->length && len; free++, len -= bytes) {
1809 /* Write request not from offset 0 ? */
1810 if (unlikely(woffs)) {
1811 if (woffs >= free->length) {
1812 woffs -= free->length;
1815 boffs = free->offset + woffs;
1816 bytes = min_t(size_t, len,
1817 (free->length - woffs));
1820 bytes = min_t(size_t, len, free->length);
1821 boffs = free->offset;
1823 memcpy(chip->oob_poi + boffs, oob, bytes);
1834 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1837 * nand_do_write_ops - [Internal] NAND write with ECC
1838 * @mtd: MTD device structure
1839 * @to: offset to write to
1840 * @ops: oob operations description structure
1842 * NAND write with ECC
1844 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1845 struct mtd_oob_ops *ops)
1847 int chipnr, realpage, page, blockmask, column;
1848 struct nand_chip *chip = mtd->priv;
1849 uint32_t writelen = ops->len;
1850 uint8_t *oob = ops->oobbuf;
1851 uint8_t *buf = ops->datbuf;
1858 column = to & (mtd->writesize - 1);
1859 subpage = column || (writelen & (mtd->writesize - 1));
1864 chipnr = (int)(to >> chip->chip_shift);
1865 chip->select_chip(mtd, chipnr);
1867 /* Check, if it is write protected */
1868 if (nand_check_wp(mtd)) {
1869 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1873 realpage = (int)(to >> chip->page_shift);
1874 page = realpage & chip->pagemask;
1875 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1877 /* Invalidate the page cache, when we write to the cached page */
1878 if (to <= (chip->pagebuf << chip->page_shift) &&
1879 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1882 /* If we're not given explicit OOB data, let it be 0xFF */
1884 memset(chip->oob_poi, 0xff, mtd->oobsize);
1887 int bytes = mtd->writesize;
1888 int cached = writelen > bytes && page != blockmask;
1889 uint8_t *wbuf = buf;
1891 /* Partial page write ? */
1892 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1894 bytes = min_t(int, bytes - column, (int) writelen);
1896 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1897 memcpy(&chip->buffers->databuf[column], buf, bytes);
1898 wbuf = chip->buffers->databuf;
1902 oob = nand_fill_oob(chip, oob, ops);
1904 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1905 (ops->mode == MTD_OOB_RAW));
1917 page = realpage & chip->pagemask;
1918 /* Check, if we cross a chip boundary */
1921 chip->select_chip(mtd, -1);
1922 chip->select_chip(mtd, chipnr);
1926 ops->retlen = ops->len - writelen;
1928 ops->oobretlen = ops->ooblen;
1933 * nand_write - [MTD Interface] NAND write with ECC
1934 * @mtd: MTD device structure
1935 * @to: offset to write to
1936 * @len: number of bytes to write
1937 * @retlen: pointer to variable to store the number of written bytes
1938 * @buf: the data to write
1940 * NAND write with ECC
1942 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1943 size_t *retlen, const uint8_t *buf)
1945 struct nand_chip *chip = mtd->priv;
1948 /* Do not allow reads past end of device */
1949 if ((to + len) > mtd->size)
1954 nand_get_device(chip, mtd, FL_WRITING);
1956 chip->ops.len = len;
1957 chip->ops.datbuf = (uint8_t *)buf;
1958 chip->ops.oobbuf = NULL;
1960 ret = nand_do_write_ops(mtd, to, &chip->ops);
1962 *retlen = chip->ops.retlen;
1964 nand_release_device(mtd);
1970 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1971 * @mtd: MTD device structure
1972 * @to: offset to write to
1973 * @ops: oob operation description structure
1975 * NAND write out-of-band
1977 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1978 struct mtd_oob_ops *ops)
1980 int chipnr, page, status, len;
1981 struct nand_chip *chip = mtd->priv;
1983 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1984 (unsigned int)to, (int)ops->ooblen);
1986 if (ops->mode == MTD_OOB_AUTO)
1987 len = chip->ecc.layout->oobavail;
1991 /* Do not allow write past end of page */
1992 if ((ops->ooboffs + ops->ooblen) > len) {
1993 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1994 "Attempt to write past end of page\n");
1998 if (unlikely(ops->ooboffs >= len)) {
1999 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2000 "Attempt to start write outside oob\n");
2004 /* Do not allow reads past end of device */
2005 if (unlikely(to >= mtd->size ||
2006 ops->ooboffs + ops->ooblen >
2007 ((mtd->size >> chip->page_shift) -
2008 (to >> chip->page_shift)) * len)) {
2009 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2010 "Attempt write beyond end of device\n");
2014 chipnr = (int)(to >> chip->chip_shift);
2015 chip->select_chip(mtd, chipnr);
2017 /* Shift to get page */
2018 page = (int)(to >> chip->page_shift);
2021 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2022 * of my DiskOnChip 2000 test units) will clear the whole data page too
2023 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2024 * it in the doc2000 driver in August 1999. dwmw2.
2026 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2028 /* Check, if it is write protected */
2029 if (nand_check_wp(mtd))
2032 /* Invalidate the page cache, if we write to the cached page */
2033 if (page == chip->pagebuf)
2036 memset(chip->oob_poi, 0xff, mtd->oobsize);
2037 nand_fill_oob(chip, ops->oobbuf, ops);
2038 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2039 memset(chip->oob_poi, 0xff, mtd->oobsize);
2044 ops->oobretlen = ops->ooblen;
2050 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2051 * @mtd: MTD device structure
2052 * @to: offset to write to
2053 * @ops: oob operation description structure
2055 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2056 struct mtd_oob_ops *ops)
2058 struct nand_chip *chip = mtd->priv;
2059 int ret = -ENOTSUPP;
2063 /* Do not allow writes past end of device */
2064 if (ops->datbuf && (to + ops->len) > mtd->size) {
2065 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2066 "Attempt read beyond end of device\n");
2070 nand_get_device(chip, mtd, FL_WRITING);
2083 ret = nand_do_write_oob(mtd, to, ops);
2085 ret = nand_do_write_ops(mtd, to, ops);
2088 nand_release_device(mtd);
2093 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2094 * @mtd: MTD device structure
2095 * @page: the page address of the block which will be erased
2097 * Standard erase command for NAND chips
2099 static void single_erase_cmd(struct mtd_info *mtd, int page)
2101 struct nand_chip *chip = mtd->priv;
2102 /* Send commands to erase a block */
2103 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2104 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2108 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2109 * @mtd: MTD device structure
2110 * @page: the page address of the block which will be erased
2112 * AND multi block erase command function
2113 * Erase 4 consecutive blocks
2115 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2117 struct nand_chip *chip = mtd->priv;
2118 /* Send commands to erase a block */
2119 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2120 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2121 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2122 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2123 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2127 * nand_erase - [MTD Interface] erase block(s)
2128 * @mtd: MTD device structure
2129 * @instr: erase instruction
2131 * Erase one ore more blocks
2133 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2135 return nand_erase_nand(mtd, instr, 0);
2138 #define BBT_PAGE_MASK 0xffffff3f
2140 * nand_erase_nand - [Internal] erase block(s)
2141 * @mtd: MTD device structure
2142 * @instr: erase instruction
2143 * @allowbbt: allow erasing the bbt area
2145 * Erase one ore more blocks
2147 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2150 int page, status, pages_per_block, ret, chipnr;
2151 struct nand_chip *chip = mtd->priv;
2152 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2153 unsigned int bbt_masked_page = 0xffffffff;
2156 MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2157 "len = %llu\n", (unsigned long long) instr->addr,
2158 (unsigned long long) instr->len);
2160 /* Start address must align on block boundary */
2161 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2162 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2166 /* Length must align on block boundary */
2167 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2168 MTDDEBUG (MTD_DEBUG_LEVEL0,
2169 "nand_erase: Length not block aligned\n");
2173 /* Do not allow erase past end of device */
2174 if ((instr->len + instr->addr) > mtd->size) {
2175 MTDDEBUG (MTD_DEBUG_LEVEL0,
2176 "nand_erase: Erase past end of device\n");
2180 instr->fail_addr = 0xffffffff;
2182 /* Grab the lock and see if the device is available */
2183 nand_get_device(chip, mtd, FL_ERASING);
2185 /* Shift to get first page */
2186 page = (int)(instr->addr >> chip->page_shift);
2187 chipnr = (int)(instr->addr >> chip->chip_shift);
2189 /* Calculate pages in each block */
2190 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2192 /* Select the NAND device */
2193 chip->select_chip(mtd, chipnr);
2195 /* Check, if it is write protected */
2196 if (nand_check_wp(mtd)) {
2197 MTDDEBUG (MTD_DEBUG_LEVEL0,
2198 "nand_erase: Device is write protected!!!\n");
2199 instr->state = MTD_ERASE_FAILED;
2204 * If BBT requires refresh, set the BBT page mask to see if the BBT
2205 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2206 * can not be matched. This is also done when the bbt is actually
2207 * erased to avoid recusrsive updates
2209 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2210 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2212 /* Loop through the pages */
2215 instr->state = MTD_ERASING;
2219 * heck if we have a bad block, we do not erase bad blocks !
2221 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2222 chip->page_shift, 0, allowbbt)) {
2223 printk(KERN_WARNING "nand_erase: attempt to erase a "
2224 "bad block at page 0x%08x\n", page);
2225 instr->state = MTD_ERASE_FAILED;
2230 * Invalidate the page cache, if we erase the block which
2231 * contains the current cached page
2233 if (page <= chip->pagebuf && chip->pagebuf <
2234 (page + pages_per_block))
2237 chip->erase_cmd(mtd, page & chip->pagemask);
2239 status = chip->waitfunc(mtd, chip);
2242 * See if operation failed and additional status checks are
2245 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2246 status = chip->errstat(mtd, chip, FL_ERASING,
2249 /* See if block erase succeeded */
2250 if (status & NAND_STATUS_FAIL) {
2251 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2252 "Failed erase, page 0x%08x\n", page);
2253 instr->state = MTD_ERASE_FAILED;
2254 instr->fail_addr = ((loff_t)page << chip->page_shift);
2259 * If BBT requires refresh, set the BBT rewrite flag to the
2262 if (bbt_masked_page != 0xffffffff &&
2263 (page & BBT_PAGE_MASK) == bbt_masked_page)
2264 rewrite_bbt[chipnr] =
2265 ((loff_t)page << chip->page_shift);
2267 /* Increment page address and decrement length */
2268 len -= (1 << chip->phys_erase_shift);
2269 page += pages_per_block;
2271 /* Check, if we cross a chip boundary */
2272 if (len && !(page & chip->pagemask)) {
2274 chip->select_chip(mtd, -1);
2275 chip->select_chip(mtd, chipnr);
2278 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2279 * page mask to see if this BBT should be rewritten
2281 if (bbt_masked_page != 0xffffffff &&
2282 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2283 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2287 instr->state = MTD_ERASE_DONE;
2291 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2293 /* Deselect and wake up anyone waiting on the device */
2294 nand_release_device(mtd);
2296 /* Do call back function */
2298 mtd_erase_callback(instr);
2301 * If BBT requires refresh and erase was successful, rewrite any
2302 * selected bad block tables
2304 if (bbt_masked_page == 0xffffffff || ret)
2307 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2308 if (!rewrite_bbt[chipnr])
2310 /* update the BBT for chip */
2311 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2312 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2313 chip->bbt_td->pages[chipnr]);
2314 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2317 /* Return more or less happy */
2322 * nand_sync - [MTD Interface] sync
2323 * @mtd: MTD device structure
2325 * Sync is actually a wait for chip ready function
2327 static void nand_sync(struct mtd_info *mtd)
2329 struct nand_chip *chip = mtd->priv;
2331 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2333 /* Grab the lock and see if the device is available */
2334 nand_get_device(chip, mtd, FL_SYNCING);
2335 /* Release it and go back */
2336 nand_release_device(mtd);
2340 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2341 * @mtd: MTD device structure
2342 * @offs: offset relative to mtd start
2344 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2346 /* Check for invalid offset */
2347 if (offs > mtd->size)
2350 return nand_block_checkbad(mtd, offs, 1, 0);
2354 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2355 * @mtd: MTD device structure
2356 * @ofs: offset relative to mtd start
2358 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2360 struct nand_chip *chip = mtd->priv;
2363 if ((ret = nand_block_isbad(mtd, ofs))) {
2364 /* If it was bad already, return success and do nothing. */
2370 return chip->block_markbad(mtd, ofs);
2374 * Set default functions
2376 static void nand_set_defaults(struct nand_chip *chip, int busw)
2378 /* check for proper chip_delay setup, set 20us if not */
2379 if (!chip->chip_delay)
2380 chip->chip_delay = 20;
2382 /* check, if a user supplied command function given */
2383 if (chip->cmdfunc == NULL)
2384 chip->cmdfunc = nand_command;
2386 /* check, if a user supplied wait function given */
2387 if (chip->waitfunc == NULL)
2388 chip->waitfunc = nand_wait;
2390 if (!chip->select_chip)
2391 chip->select_chip = nand_select_chip;
2392 if (!chip->read_byte)
2393 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2394 if (!chip->read_word)
2395 chip->read_word = nand_read_word;
2396 if (!chip->block_bad)
2397 chip->block_bad = nand_block_bad;
2398 if (!chip->block_markbad)
2399 chip->block_markbad = nand_default_block_markbad;
2400 if (!chip->write_buf)
2401 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2402 if (!chip->read_buf)
2403 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2404 if (!chip->verify_buf)
2405 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2406 if (!chip->scan_bbt)
2407 chip->scan_bbt = nand_default_bbt;
2408 if (!chip->controller)
2409 chip->controller = &chip->hwcontrol;
2413 * Get the flash and manufacturer id and lookup if the type is supported
2415 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2416 struct nand_chip *chip,
2417 int busw, int *maf_id,
2418 const struct nand_flash_dev *type)
2420 int dev_id, maf_idx;
2421 int tmp_id, tmp_manf;
2423 /* Select the device */
2424 chip->select_chip(mtd, 0);
2427 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2430 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2432 /* Send the command for reading device ID */
2433 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2435 /* Read manufacturer and device IDs */
2436 *maf_id = chip->read_byte(mtd);
2437 dev_id = chip->read_byte(mtd);
2439 /* Try again to make sure, as some systems the bus-hold or other
2440 * interface concerns can cause random data which looks like a
2441 * possibly credible NAND flash to appear. If the two results do
2442 * not match, ignore the device completely.
2445 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2447 /* Read manufacturer and device IDs */
2449 tmp_manf = chip->read_byte(mtd);
2450 tmp_id = chip->read_byte(mtd);
2452 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2453 printk(KERN_INFO "%s: second ID read did not match "
2454 "%02x,%02x against %02x,%02x\n", __func__,
2455 *maf_id, dev_id, tmp_manf, tmp_id);
2456 return ERR_PTR(-ENODEV);
2460 type = nand_flash_ids;
2462 for (; type->name != NULL; type++)
2463 if (dev_id == type->id)
2467 /* supress warning if there is no nand */
2468 if (*maf_id != 0x00 && *maf_id != 0xff &&
2469 dev_id != 0x00 && dev_id != 0xff)
2470 printk(KERN_INFO "%s: unknown NAND device: "
2471 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2472 __func__, *maf_id, dev_id);
2473 return ERR_PTR(-ENODEV);
2477 mtd->name = type->name;
2479 chip->chipsize = (uint64_t)type->chipsize << 20;
2481 /* Newer devices have all the information in additional id bytes */
2482 if (!type->pagesize) {
2484 /* The 3rd id byte holds MLC / multichip data */
2485 chip->cellinfo = chip->read_byte(mtd);
2486 /* The 4th id byte is the important one */
2487 extid = chip->read_byte(mtd);
2489 mtd->writesize = 1024 << (extid & 0x3);
2492 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2494 /* Calc blocksize. Blocksize is multiples of 64KiB */
2495 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2497 /* Get buswidth information */
2498 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2502 * Old devices have chip data hardcoded in the device id table
2504 mtd->erasesize = type->erasesize;
2505 mtd->writesize = type->pagesize;
2506 mtd->oobsize = mtd->writesize / 32;
2507 busw = type->options & NAND_BUSWIDTH_16;
2510 /* Try to identify manufacturer */
2511 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2512 if (nand_manuf_ids[maf_idx].id == *maf_id)
2517 * Check, if buswidth is correct. Hardware drivers should set
2520 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2521 printk(KERN_INFO "NAND device: Manufacturer ID:"
2522 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2523 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2524 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2525 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2527 return ERR_PTR(-EINVAL);
2530 /* Calculate the address shift from the page size */
2531 chip->page_shift = ffs(mtd->writesize) - 1;
2532 /* Convert chipsize to number of pages per chip -1. */
2533 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2535 chip->bbt_erase_shift = chip->phys_erase_shift =
2536 ffs(mtd->erasesize) - 1;
2537 if (chip->chipsize & 0xffffffff)
2538 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2540 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2542 /* Set the bad block position */
2543 chip->badblockpos = mtd->writesize > 512 ?
2544 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2546 /* Get chip options, preserve non chip based options */
2547 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2548 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2551 * Set chip as a default. Board drivers can override it, if necessary
2553 chip->options |= NAND_NO_AUTOINCR;
2555 /* Check if chip is a not a samsung device. Do not clear the
2556 * options for chips which are not having an extended id.
2558 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2559 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2561 /* Check for AND chips with 4 page planes */
2562 if (chip->options & NAND_4PAGE_ARRAY)
2563 chip->erase_cmd = multi_erase_cmd;
2565 chip->erase_cmd = single_erase_cmd;
2567 /* Do not replace user supplied command function ! */
2568 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2569 chip->cmdfunc = nand_command_lp;
2571 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2572 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2573 nand_manuf_ids[maf_idx].name, type->name);
2579 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2580 * @mtd: MTD device structure
2581 * @maxchips: Number of chips to scan for
2582 * @table: Alternative NAND ID table
2584 * This is the first phase of the normal nand_scan() function. It
2585 * reads the flash ID and sets up MTD fields accordingly.
2587 * The mtd->owner field must be set to the module of the caller.
2589 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2590 const struct nand_flash_dev *table)
2592 int i, busw, nand_maf_id;
2593 struct nand_chip *chip = mtd->priv;
2594 const struct nand_flash_dev *type;
2596 /* Get buswidth to select the correct functions */
2597 busw = chip->options & NAND_BUSWIDTH_16;
2598 /* Set the default functions */
2599 nand_set_defaults(chip, busw);
2601 /* Read the flash type */
2602 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table);
2605 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2606 printk(KERN_WARNING "No NAND device found!!!\n");
2608 chip->select_chip(mtd, -1);
2609 return PTR_ERR(type);
2612 /* Check for a chip array */
2613 for (i = 1; i < maxchips; i++) {
2614 chip->select_chip(mtd, i);
2615 /* See comment in nand_get_flash_type for reset */
2616 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2617 /* Send the command for reading device ID */
2618 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2619 /* Read manufacturer and device IDs */
2620 if (nand_maf_id != chip->read_byte(mtd) ||
2621 type->id != chip->read_byte(mtd))
2626 printk(KERN_INFO "%d NAND chips detected\n", i);
2629 /* Store the number of chips and calc total size for mtd */
2631 mtd->size = i * chip->chipsize;
2638 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2639 * @mtd: MTD device structure
2641 * This is the second phase of the normal nand_scan() function. It
2642 * fills out all the uninitialized function pointers with the defaults
2643 * and scans for a bad block table if appropriate.
2645 int nand_scan_tail(struct mtd_info *mtd)
2648 struct nand_chip *chip = mtd->priv;
2650 if (!(chip->options & NAND_OWN_BUFFERS))
2651 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2655 /* Set the internal oob buffer location, just after the page data */
2656 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2659 * If no default placement scheme is given, select an appropriate one
2661 if (!chip->ecc.layout) {
2662 switch (mtd->oobsize) {
2664 chip->ecc.layout = &nand_oob_8;
2667 chip->ecc.layout = &nand_oob_16;
2670 chip->ecc.layout = &nand_oob_64;
2673 chip->ecc.layout = &nand_oob_128;
2676 printk(KERN_WARNING "No oob scheme defined for "
2677 "oobsize %d\n", mtd->oobsize);
2681 if (!chip->write_page)
2682 chip->write_page = nand_write_page;
2685 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2686 * selected and we have 256 byte pagesize fallback to software ECC
2689 switch (chip->ecc.mode) {
2690 case NAND_ECC_HW_OOB_FIRST:
2691 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2692 if (!chip->ecc.calculate || !chip->ecc.correct ||
2694 printk(KERN_WARNING "No ECC functions supplied, "
2695 "Hardware ECC not possible\n");
2698 if (!chip->ecc.read_page)
2699 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2702 /* Use standard hwecc read page function ? */
2703 if (!chip->ecc.read_page)
2704 chip->ecc.read_page = nand_read_page_hwecc;
2705 if (!chip->ecc.write_page)
2706 chip->ecc.write_page = nand_write_page_hwecc;
2707 if (!chip->ecc.read_page_raw)
2708 chip->ecc.read_page_raw = nand_read_page_raw;
2709 if (!chip->ecc.write_page_raw)
2710 chip->ecc.write_page_raw = nand_write_page_raw;
2711 if (!chip->ecc.read_oob)
2712 chip->ecc.read_oob = nand_read_oob_std;
2713 if (!chip->ecc.write_oob)
2714 chip->ecc.write_oob = nand_write_oob_std;
2716 case NAND_ECC_HW_SYNDROME:
2717 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2718 !chip->ecc.hwctl) &&
2719 (!chip->ecc.read_page ||
2720 chip->ecc.read_page == nand_read_page_hwecc ||
2721 !chip->ecc.write_page ||
2722 chip->ecc.write_page == nand_write_page_hwecc)) {
2723 printk(KERN_WARNING "No ECC functions supplied, "
2724 "Hardware ECC not possible\n");
2727 /* Use standard syndrome read/write page function ? */
2728 if (!chip->ecc.read_page)
2729 chip->ecc.read_page = nand_read_page_syndrome;
2730 if (!chip->ecc.write_page)
2731 chip->ecc.write_page = nand_write_page_syndrome;
2732 if (!chip->ecc.read_page_raw)
2733 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2734 if (!chip->ecc.write_page_raw)
2735 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2736 if (!chip->ecc.read_oob)
2737 chip->ecc.read_oob = nand_read_oob_syndrome;
2738 if (!chip->ecc.write_oob)
2739 chip->ecc.write_oob = nand_write_oob_syndrome;
2741 if (mtd->writesize >= chip->ecc.size)
2743 printk(KERN_WARNING "%d byte HW ECC not possible on "
2744 "%d byte page size, fallback to SW ECC\n",
2745 chip->ecc.size, mtd->writesize);
2746 chip->ecc.mode = NAND_ECC_SOFT;
2749 chip->ecc.calculate = nand_calculate_ecc;
2750 chip->ecc.correct = nand_correct_data;
2751 chip->ecc.read_page = nand_read_page_swecc;
2752 chip->ecc.read_subpage = nand_read_subpage;
2753 chip->ecc.write_page = nand_write_page_swecc;
2754 chip->ecc.read_page_raw = nand_read_page_raw;
2755 chip->ecc.write_page_raw = nand_write_page_raw;
2756 chip->ecc.read_oob = nand_read_oob_std;
2757 chip->ecc.write_oob = nand_write_oob_std;
2758 chip->ecc.size = 256;
2759 chip->ecc.bytes = 3;
2763 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2764 "This is not recommended !!\n");
2765 chip->ecc.read_page = nand_read_page_raw;
2766 chip->ecc.write_page = nand_write_page_raw;
2767 chip->ecc.read_oob = nand_read_oob_std;
2768 chip->ecc.read_page_raw = nand_read_page_raw;
2769 chip->ecc.write_page_raw = nand_write_page_raw;
2770 chip->ecc.write_oob = nand_write_oob_std;
2771 chip->ecc.size = mtd->writesize;
2772 chip->ecc.bytes = 0;
2776 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2782 * The number of bytes available for a client to place data into
2783 * the out of band area
2785 chip->ecc.layout->oobavail = 0;
2786 for (i = 0; chip->ecc.layout->oobfree[i].length
2787 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2788 chip->ecc.layout->oobavail +=
2789 chip->ecc.layout->oobfree[i].length;
2790 mtd->oobavail = chip->ecc.layout->oobavail;
2793 * Set the number of read / write steps for one page depending on ECC
2796 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2797 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2798 printk(KERN_WARNING "Invalid ecc parameters\n");
2801 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2804 * Allow subpage writes up to ecc.steps. Not possible for MLC
2807 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2808 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2809 switch(chip->ecc.steps) {
2811 mtd->subpage_sft = 1;
2816 mtd->subpage_sft = 2;
2820 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2822 /* Initialize state */
2823 chip->state = FL_READY;
2825 /* De-select the device */
2826 chip->select_chip(mtd, -1);
2828 /* Invalidate the pagebuffer reference */
2831 /* Fill in remaining MTD driver data */
2832 mtd->type = MTD_NANDFLASH;
2833 mtd->flags = MTD_CAP_NANDFLASH;
2834 mtd->erase = nand_erase;
2836 mtd->unpoint = NULL;
2837 mtd->read = nand_read;
2838 mtd->write = nand_write;
2839 mtd->read_oob = nand_read_oob;
2840 mtd->write_oob = nand_write_oob;
2841 mtd->sync = nand_sync;
2844 mtd->block_isbad = nand_block_isbad;
2845 mtd->block_markbad = nand_block_markbad;
2847 /* propagate ecc.layout to mtd_info */
2848 mtd->ecclayout = chip->ecc.layout;
2850 /* Check, if we should skip the bad block table scan */
2851 if (chip->options & NAND_SKIP_BBTSCAN)
2852 chip->options |= NAND_BBT_SCANNED;
2858 * nand_scan - [NAND Interface] Scan for the NAND device
2859 * @mtd: MTD device structure
2860 * @maxchips: Number of chips to scan for
2862 * This fills out all the uninitialized function pointers
2863 * with the defaults.
2864 * The flash ID is read and the mtd/chip structures are
2865 * filled with the appropriate values.
2866 * The mtd->owner field must be set to the module of the caller
2869 int nand_scan(struct mtd_info *mtd, int maxchips)
2873 ret = nand_scan_ident(mtd, maxchips, NULL);
2875 ret = nand_scan_tail(mtd);
2880 * nand_release - [NAND Interface] Free resources held by the NAND device
2881 * @mtd: MTD device structure
2883 void nand_release(struct mtd_info *mtd)
2885 struct nand_chip *chip = mtd->priv;
2887 #ifdef CONFIG_MTD_PARTITIONS
2888 /* Deregister partitions */
2889 del_mtd_partitions(mtd);
2892 /* Free bad block table memory */
2894 if (!(chip->options & NAND_OWN_BUFFERS))
2895 kfree(chip->buffers);